JP2940474B2 - Read only memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a read-only memory device for reading and using data programmed in a memory cell and a method of manufacturing the same, and more particularly to a read-only memory device having a NOR type cell and a method of manufacturing the same.

[0002]

2. Description of the Related Art A read-only memory device (ROM) for storing a large amount of data and reading it out when necessary is used.
With the widespread use of A-devices and computers, their integration is required. By the way, as an example of a structure for realizing such high integration, in the case of a circuit configuration of a NAND cell, a gate electrode layer composed of two polysilicon layers and a shallow trench (a so-called shallow trench structure) are provided. There is known a mask ROM having a so-called multi-gate structure (for example, monthly Semiconductor World October 1987, 33-38).
See “8M and 16M Mask ROM Using Shallow Trench”
Further, as an example having a NOR type cell, a mask ROM in which a source / drain region is constituted by a diffusion region is known (for example, 1988 Symposium on).
VLSIcircuits (Japan Society of Applied Physics) material, VL-7, 85-86
Page “16Mb ROM DESIGN USING BANK SELECT ARCHITECTUR
E ”).

FIG. 18 is a circuit diagram of a main part of a mask ROM having the NOR type cells. In this mask ROM, word lines W ₁ to W ₁ are arranged in a matrix. W
₈ are each one MOS cell
The source / drain region composed of a transistor and composed of a diffusion region is shared by bit lines 205, 2
06 and 207. In this mask ROM, virtual ground lines 201 and main bit lines 202 are alternately formed, and the longitudinal direction is a direction perpendicular to the extending direction of the word lines. These virtual ground line 201 and main bit line 202
Are wired so as to be shifted by one bit line so as to be connected to different columns in one and the other blocks of the memory cell. Therefore, the selection transistors 203, 2
By selectively selecting 04 (bank select), the same bit line is connected to the virtual ground line 201 or to the main bit line 202. In reading, by selecting a certain column by the column selection transistor 208 and selecting one word line, data is read through the main bit line 202 and the sense amplifier 209, and data appears at an output terminal. .

FIG. 19 shows a layout of the mask ROM shown in FIG. In the figure, the regions with scattered points are the polysilicon layers, which are formed in parallel with each other with the X direction as the longitudinal direction. A pair of contact holes 2 in the Y direction
The region sandwiched by 11 is a memory block, and the diffusion region 213 in the region where the contact hole 211 is formed has a substantially H-shaped pattern. The diffusion regions 205 to 207... Surrounded by thick solid lines are bit lines that function as source / drain regions. Channel transistor of each cell is formed in the lower portion of the word line W ₁ to _W-8.
Then, programming is performed by introducing an impurity into this channel using the mask pattern 212. The selection transistor 20 used for bank selection
3 gate electrodes SE _i , SE _i-1 and select transistor 20
4 gate electrodes SO _i and SO _{i + 1} are connected to the word lines W ₁ to W ₁ .
W ₈ and is parallel to extending and disposed so as to sandwich the memory block.

[0005]

However, the above N
In the AND type cell, when the number of transistors connected in series is increased for higher integration, the driving power of the memory cell is reduced. On the other hand, the mask R of the NOR type cell
The OM has the following problems in layout.

That is, the channel of the transistor in each cell is formed below the word lines W _{1 to} W ₈ , and the channel direction is the X direction in the figure. However, the selection electrodes 203 and 204 for bank selection have their gate electrodes SE _i , SE _i−1 , SO _i and SO _{i + 1 connected} to the word line W _1.
To _W-8 and despite being parallel extended, since the channel is formed between the bit lines 205 to 207, ... substantially H-shaped diffusion region 213, in the channel direction FIG Y
Direction. Accordingly, in the selection transistors 203 and 204 for bank selection, the gate electrodes SE _i and S
It is necessary to form a channel stopper region between E _i-1 , SO _i , and SO _{i + 1} and adjacent channels. For this reason, in the memory cell region, ion implantation for the channel stopper may be performed in alignment with the word lines W _{1 to} W _8.
In regions 3 and 204, ion implantation is required separately from the memory cell region, and the channel stopper region cannot be formed in conformity with the polysilicon layer. Therefore, a margin in consideration of mask shift is indispensable. You. As a result of the need for such a margin, the area on the memory block side is constrained, which makes it difficult to improve the degree of integration.

It is therefore an object of the present invention to provide a read-only memory device capable of achieving high integration and downsizing, and a method of manufacturing the same.

[0008]

SUMMARY OF THE INVENTION A read-only memory device according to the present invention comprises a first memory device for solving the above-mentioned problems.
Semiconductor substrate, a thick oxide film formed in a band shape parallel to the surface of the first conductivity type semiconductor substrate, and a first conductive film formed on the semiconductor substrate in contact with the bottom of the thick oxide film. A source / drain region of a second conductivity type having a conductivity type opposite to the conductivity type, a first electrode layer formed in a strip shape substantially perpendicular to the thick oxide film, and a first electrode layer parallel to the first electrode layer; A second electrode layer formed in a strip shape having a portion overlapping with the first electrode layer on a semiconductor substrate sandwiched between the first electrode layers, and a thick oxide film formed between the second electrode layer and the first electrode layer; Between a thick gate oxide film and a thick oxide film on the surface of a certain semiconductor substrate, a thinner than the thick oxide film is formed on the surface of the semiconductor substrate under the second electrode layer. And a gate oxide film formed. Also, between the thick oxide films of the read-only memory device, a groove region formed in a self-aligned manner with respect to the first electrode layer and the thick oxide film is formed in a semiconductor substrate region under the second electrode layer. A gate insulating film is formed on a surface of a semiconductor substrate. Here, the first conductivity type is, for example, a p-type, and the second conductivity type is an n-type.

Further, a method of manufacturing a read-only memory device according to the present invention is directed to a first method for solving the above-mentioned problems.
A first step of forming an oxidation-resistant film on the surface of the conductive semiconductor substrate, a second step of forming a strip-shaped resist layer parallel to the oxidation-resistant film, and forming the oxidation-resistant film using the resist layer as a mask. A third step of etching, and a fourth step of introducing an impurity of a second conductivity type, which has a conductivity type opposite to the first conductivity type, into the semiconductor substrate using the laminated film of the resist layer and the oxidation-resistant film as a mask. A step, a fifth step of removing the resist layer, a sixth step of oxidizing the semiconductor surface using the oxidation resistant film as a mask to form a thick oxide film, and a seventh step of removing the oxidation resistant film, An eighth step of forming a gate oxide film thinner than the thick oxide film on the surface of the semiconductor substrate between the thick oxide films, and selectively implanting impurities of the first conductivity type in a region where the gate oxide film is formed. The ninth step to be introduced is substantially perpendicular to the longitudinal direction of the thick oxide film An eleventh step of etching the tenth step of forming a first electrode layer of the strip, a gate oxide film and the semiconductor substrate a first electrode layer as a mask counter,
A twelfth step of selectively introducing an impurity of the first conductivity type into the semiconductor substrate corresponding to the etched region; and a thicker oxide film on the semiconductor substrate and the first electrode layer corresponding to the etched region. A thirteenth step of forming a thin gate oxide film; and forming a first electrode on a semiconductor substrate corresponding to an etched region parallel to the first electrode layer and sandwiched by the first electrode layer. A fourteenth step of selectively forming a second electrode layer having a portion overlapping the layer. Here, for example, the first conductivity type is p-type, and the second conductivity type is n-type.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a read-only memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings.

First Embodiment A read-only memory device according to the present invention has memory cells arranged in rows and columns, and a source / drain region common to each column of MOS transistors of the memory cells has a sub-bit line. Read only memory device (ROM) in which the sub bit lines and the sub column lines are alternately arranged.
Used as Impurities are selectively ion-implanted into the channel region of each MOS transistor of the memory cell, and programming is performed.

General Description (FIG. 3) The read-only memory device has an overall circuit configuration as shown in FIG. 3, for example. That is, the read-only memory device has a cell array 4 in which memory cells are arranged in a matrix, as will be described later. Have. A signal is sent from the address buffer 5 to the row decoder 6 and the column decoder 7. Signal from the address buffer 5 is generated based on the address signal A _X from the outside. Data from the cell array 4 is amplified by a sense amplifier 8 via a column decoder 7 and sent to an output buffer 9. Then, an output signal Dout is taken out from the output buffer 9 to the outside.

Next, the configuration of the cell array portion of the ROM of this embodiment will be described with reference to FIG. In addition, FIG.
Only a part of the structure continuously repeated in the direction in which the word lines extend is taken out and shown. Although the number of word lines is described as four in FIG. 1 for convenience, the number is actually set to eight as described later.

First, in the memory cell block 1, cells are arranged in a matrix. Each cell is composed of one n-channel MOS transistor. The threshold voltage of each MOS transistor is selectively adjusted to a high threshold voltage and a low threshold voltage according to the programmed data. The gate electrodes of these MOS transistors are word lines W _{1 to} W ₄ , which extend in the horizontal direction in the figure as a longitudinal direction, and are commonly used in each row. One of the source / drain regions of the MOS transistor of each cell is a sub-bit line B ₁₂ , B ₂₁ , B ₂₂ , B _31, and the other of the source / drain region of the MOS transistor of each cell is a sub-column line C
₁₁ , C ₁₂ , C ₂₁ and C ₂₂ . These sub-bit lines and sub-column lines extend in a direction perpendicular to the word lines W _{1 to} W ₄ as a longitudinal direction. These sub-bit lines and sub-column lines are further shared by MOS transistors adjacent in the word line extension direction. Therefore, the sub bit lines B ₁₂ ,
B _21, B _22, B ₃₁ and auxiliary column line _{C 11, C 12, C 21} , C 22
Are formed alternately in the extending direction of the word line, next to the auxiliary column line C ₁₁ of the sub-bit line B ₁₂ is arranged, the sub-column lines C
_The bit line B ₂₁ is arranged next to ₁₁ , and the sub-column lines and the sub-bit lines are similarly arranged in order.

At one end of the memory cell block 1, each of the sub-bit lines B ₁₂ , B ₂₁ , B ₂₂ and B ₃₁ is alternatively connected to the main bit lines B ₁ , B ₂ and B ₃ . MOS to connect
Transistors T ₁ , T ₂ , T _3, T ₄ are provided. That is, the sub bit line B ₁₂ is connected to the main bit line B ₁ via the MOS transistor T ₁ , and the sub bit line B ₂₁
Are connected via the MOS transistor T ₂ to the main bit line B _2, the sub-bit line B ₂₂ is connected via the MOS transistor T ₃ to the main bit line B _2, the sub-bit line B ₃₁ is MO
Via the S transistor T ₄ is connected to the main bit line B _3. From such a connection relationship, the main bit line is electrically connected to one of the pair of sub-bit lines by the MOS transistors T ₁ , T ₂ , T ₃ , and T ₄ .

Here, the MOS transistors T ₁ and T ₃ are:
The gate electrode of the MOS transistors T ₂ and T ₄ is set to the selection line WBS ′ (“′” indicates negative logic), and the gate electrode of the MOS transistors T ₂ and T ₄ is set to the selection line WBS. Therefore, the selection line WB
S 'and the signal supplied to the selection line WBS have opposite phases to each other. Therefore, when the select line WBS is at a high level, for example, the main bit line B ₂ is connected to the bit line B ₂₁ via the MOS transistor T ₂ , and conversely, when the select line WBS ′ is at a high level, the same main bit line B ₂ is connected. B ₂ is connected to bit line B ₂₂ via the MOS transistor T _3. The same operation is performed for the other sub-bit lines.

At the other end of the memory cell block 1, MOS transistors T ₅ , T ₆ , T ₇ , T ₈ , T ₉ are provided. These MOS transistors T ₅ , T ₆ , T
₇ , T ₈ , T ₉ are the main column lines C ₁ , C ₂ and the sub column lines C
_11, is used as a switch to be selectively electrically connected to the _{C 12, C 21, C 22} . That is, the main column line C ₁ is connected to the sub column line C ₁₁ via the MOS transistor T _6.
Is connected to, it is connected via the MOS transistor T ₇ in the sub-column line C _12. In addition, the main column line C ₂
Are connected to the sub-column line C ₂₁ via the MOS transistor T ₈ and to the sub-column line C ₂₂ via the MOS transistor T ₉ . Further, the same applies to other bit lines. And the MOS transistor T
₅ , T ₆ , T ₇ , T ₈ , T ₉ , MOS transistors T ₆ , T ₈ have their gate electrodes selected as select lines WCS ′,
The gate electrodes of the MOS transistors T ₅ , T ₇ , and T ₉ are used as the selection line WCS. Then, the signal supplied to the selection line WCS ′ and the signal supplied to the selection line WCS have phases opposite to each other. Therefore, when the select line WCS 'is at a high level, the MOS transistors T ₆ and T ₈ are turned on, the main column line C ₁ is electrically connected to the sub column line C ₁₁ , and at the same time, the main column line C ₁₁ is turned on. ₂ is electrically connected to the sub-column line C _21. Conversely, when the select line WCS is at a high level, the MOS transistors T ₇ and T ₉ are turned on,
The main column line C ₁ is electrically connected to the sub column line C ₁₂ ,
At the same time, the main column line C ₂ is electrically connected to the sub-column line C _22.

As described above, the main bit lines B ₁ , B ₂ , B ₃ and the main column which are selectively connected to the respective sub bit lines and the respective sub column lines in accordance with the respective signals supplied to the respective selection lines. Lines C ₁ and C
₂ extends the memory cell block 1 in a direction perpendicular to the direction in which the word lines extend. The load circuit 3 is connected to one end of each of the main bit lines B ₁ , B ₂ , B ₃ and the main column lines C ₁ , C ₂ . This load circuit 3 includes load transistors T ₁₈ , T ₁₉ , T ₂₀ , T ₂₁ , T ₂₂ ,
Specifically, the main bit lines B ₁ to the load transistor T ₁₈ is connected, the main bit line B ₂ load transistor T ₂₀ is connected, the load transistor T ₂₂ is connected to the main bit line B _3, main column lines load C ₁ transistor T ₁₉ is connected, a main column line C ₂ on the load transistor T ₂₁ is connected. These main bit lines B ₁ , B ₂ , B ₃ and main column lines C ₁ ,
C ₂ is the load transistors T ₁₈ , T ₁₉ , T ₂₀ , T ₂₁ ,
Power supply voltage Vcc is applied through the T _22. The gate electrodes of the load transistors T ₁₈ , T ₁₉ , T ₂₀ , T ₂₁ , and T ₂₂ are shared, and a signal Φ ₁ for controlling impedance is supplied.

On the opposite side of the memory cell block 1 in which such a load circuit 3 is provided, a column selection circuit 2 is provided with the memory cell block 1 interposed therebetween. The column selection circuit 2 selects a certain column of the memory cell block 1 in a group unit according to signals Y ₁ and Y ₂ from a column decoder. That is, the main column line to be selected is determined by the signals Y ₁ and Y ₂ , and to which column line the main column line is connected is determined by the MOS transistors T ₅ , T ₆ , T ₇ , T ₈ ,
It is determined by the operation of the T _9. Further, the signals Y ₁ , Y
By _2, a main bit line to be selected (two in this embodiment)
Is determined, and to which column line the main bit line is connected is determined by the MOS transistors T ₁ , T ₂ , T ₃ , T ₄
Is determined by the operation of

In the column selection circuit 2, the main column line is mainly selected by the signals Y ₁ and Y _{2 so} that the main bit lines related to the main column line are simultaneously selected.
_1, Y ₂ by may select a main bit line to the principal. One group includes two sub-column lines and three sub-bit lines. That is, for example, only the signal Y ₁ is a high level, the signal Y has such columns is selected to _1, still MOS transistors _{T 1, T 2, T 3} , T 4 and MOS transistors T _5, T _6, Assuming that T ₇ , T ₈ , and T ₉ do not operate, the only columns that may be selected are the cells on both sides of the sub-column lines C ₁₁ and C ₁₂ , and only the inside of the group can be read. The selection of the alternative sub-bit line and sub-column line within the group is
This is performed by one of the transistors T ₁ , T ₂ , T ₃ , T ₄ and the MOS transistors T ₅ , T ₆ , T ₇ , T ₈ , T ₉ .

Here, a specific configuration of the column selection circuit 2 will be described, that is, the main bit line B ₁
Is one MOS, not shown as MOS transistors T ₁₀
The main bit line B ₂ is connected through MOS transistors T ₁₃ and T ₁₄ , and the main bit line B ₃ is connected to a MOS transistor T ₁₇ and one MOS transistor (not shown). Connected to the data bus line via The main column line C ₁ is connected to the ground line via a MOS transistor T _11, T _12, a main column line C ₂ is connected to the ground line via a MOS transistor T _15, T _16.

The gates of the MOS transistors T ₁₀ and T ₁₁ are connected to the output terminal of the AND circuit 21,
The gates of the S transistors T ₁₂ and T ₁₃ are connected to the AND circuit 22.
Of the MOS transistor T ₁₄ ,
The gate of T ₁₅ is connected to the output terminal of the AND circuit 23, the gate of the MOS transistor T _16, T ₁₇ is A
Connected to the output terminal of ND circuit 24. Each of these AND circuits 21 to 24 has a two-input gate, and one of them receives signals Y ₁ and Y ₂ . The AND circuit 21
Is supplied with the signal Y ₁ and the logical product of the signals of the selection line WBS ′ and the selection line WCS ′. The AND circuit 22 receives the signal Y ₁ and the logical sum of the signals on the selection line WBS and the selection line WCS. The AND circuit 23 receives the signal Y ₂ and the logical product of the signals of the selection line WBS ′ and the selection line WCS ′. AND
The circuit 24 receives the signal Y _{2 and} selects the selection line WB
The logical sum of S and each signal of the selection line WCS is input. Therefore, the outputs of the AND circuits 21 and 23 go high only when the signals on the selection lines WBS 'and WCS' are both high. In other cases, the outputs of the AND circuits 22 and 23 go high. 24 goes high.

Description of Read Operation (FIGS. 1 and 2) Next, the read operation of the read-only memory device having the configuration of FIG. 1 will be described with reference to FIG.

The read-only device, as shown in FIG.
First, the signal Φ ₁ changes from “L” level (low level) to “H”.
Level (high level), the impedance of each load transistor T ₁₈ , T ₁₉ , T ₂₀ , T ₂₁ , T ₂₂ of the load circuit 3 is set to a predetermined value, and the main bit lines B ₁ , B ₂ , B ₃ And the main column lines C ₁ and C ₂ are pulled up to the power supply voltage Vcc side in a non-selected state.

From here, the memory transistors M in the first row
₁ When ~M ₇ will be described operation when sequentially read, rises to "H" level potential of the word line W ₁ from "L" level, this by the word line W ₁ according to the first row is selected become. Further, the potential of the other word lines W ₂ to _W-4, "L" remains level or "L" is shifted to a level, it is unselected. Further, a signal from the column decoder, first only the signal Y ₁ rises to "H" level from the "L" level, the other signal Y ₂ is kept at the "L" level. Therefore, only the AND circuits 21 and 22 to the signal Y ₁ is input becomes operational, other AN
The D circuits 23, 24 and the like are disabled. Then, rising along with the signal Y _1, MOS transistors _{T 1, T 2, T 3} , T 4 and MOS transistors T _5, T _6,
Select line WBS, select line WC for operating T ₇ , T ₈ , T ₉
An S signal is also provided. First, the selection line WBS is set to “L” level, and the selection line WCS is also set to “L” level. Therefore, both the selection line WBS 'and the selection line WCS' are set to the "H" level. As a result, only the AND circuit 21 to which the logical product of the selection line WBS ′ and the selection line WCS ′ is input becomes “H” level, and the other AND circuits 22 to 24
It is kept at the “L” level.

When the AND circuit 21 goes high, the MOS transistors T ₁₀ and T ₁₁ are turned on. MOS driven by other AND circuits 21 to 24
Transistor T ₁₂ ~T ₁₇ remains off. Thus, the MOS transistors T ₁₀ and T ₁₁ are turned on,
The main bit lines B ₁ represents, are electrically connected via the MOS transistor T ₁₀ to the data bus line. At the same time, the main column line C ₁ is connected via the MOS transistor T ₁₁ is electrically connected to the ground line, functions as a virtual ground line. Thus, the electrical connection of the main column line C ₁ to the ground line lowers the potential of the main column line C ₁ .

At the same time, as described above, the selection line WB
Since both S ′ and the select line WCS ′ are at “H” level, the MOS transistors T ₁ and T ₃ are turned on,
The MOS transistors T ₆ and T ₈ are turned on. In addition,
The other MOS transistors T ₂ , T ₄ , T ₅ , T ₇ , T ₉ are:
It remains off. Then, enter the operating state, as described above, the main bit line B ₁ since only main column line C _1, main bit line B ₁ represents, alternatively sub bit through the MOS transistors T ₁ is connected to line B _12, the main column line C ₁ is to be connected alternatively on the sub-column line C ₁₁ via the MOS transistor T _6. In the word line, only the word line W ₁ is in the ON state. Therefore, the memory transistor M ₁ is selected at this stage.

If the selected memory transistor M ₁ has a high threshold voltage by programming by selective ion implantation of impurities, the memory transistor M _1
1 is not turned on, there is no possibility that the potential of the sub-bit line B ₁₂ is lowered. Also, if having a low threshold voltage the memory transistor M _1, made from the potential of the word line W ₁ to the ON state, the potential of the sub-bit line B ₁₂ is lowered. As a result, it decreases the potential of the main bit lines B _1, also lowered the potential of the data bus lines. Thus, the threshold voltage of the memory transistor M _1, will be the potential of the data bus line changes, the data bus line potential changes to amplify is detected by the sense amplifier, the output signal Dout is obtained.

[0029] After the data of such a transistor M ₁ has been read out, the selection line WBS "L" from the level "H"
Change to a level. Then, first, the output of the AND circuit 21 selected by the signal Y ₁ becomes “L” level, and conversely, the output of the AND circuit 22 switches to “H” level.
As a result, MOS transistor T ₁₀ is turned off, the main bit line B ₁ represents, is electrically disconnected from the data bus line. The main column line C ₁ is connected to the MOS transistor T ₁₁
Rather than being connected to the ground line via is electrically connected to the ground line via a MOS transistor T _12. Also, MOS transistor T ₁₃ is turned on, this time the main bit line B ₂ is to be electrically connected to the data bus line through the MOS transistor T _13. Since the selection line WCS is at the “L” level as it is, the main column line C
₁ is connected via the MOS transistor T ₆ in the sub-column line C _11. To select line WBS becomes "H" level from the "L" level, MOS transistor T ₂ is turned on, MOS transistor T ₃ is in the OFF state. Therefore, the main bit line B ₂ is alternatively electrically connected to the sub bit line B ₂₁ via the MOS transistor T ₂ .

As described above, by selecting the sub-bit line B ₂₁ and the sub-column line C ₁₁ , the memory transistor M ₂ in the row related to the same word line W ₁ is selected. Then, according to the same programmed data with the memory transistor M _1, the sub-bit line B ₂₁ is changed, it appears to the data bus line through the main bit line B _2.

In the next cycle, the memory transistor M
_In order to select ₃ , the potential of the selection line WCS transitions from “L” level to “H” level. Then, the AND circuit 2
The output of the 2 remains in "H" level, MOS transistors T ₆ connected to the main bit line C ₁ is changed to the OFF state, MOS transistor T ₇ is changed to the ON state. As a result, the sub column line electrically connected to the main column line C ₁ is switched from the sub column line C ₁₁ to the sub column line C ₁₂ . This results in the memory transistor M ₃ is selected. Then, according to the data programmed in the same manner as the memory transistor M _1, the sub-bit lines B
₂₁ is changed, it appears to the data bus line through the main bit line B _2.

In the next cycle, the potential of the select line WBS falls from "H" level to "L" level. As a result, MOS transistor T ₂ is turned off, MOS
Transistor T ₃ is turned on. Then, the bit line electrically connected to the main bit line B ₂ becomes the sub bit line B
Switch to ₂₂ . Since the main column line C ₁ is already grounded and the main column line C ₁ is electrically connected to the sub column line C ₁₂ via the MOS transistor T ₇ , the sub column line C ₁₂ is connected to the sub column line C _12. so that the memory transistor M ₄ sandwiched between the bit line B ₂₂ is selected. Then, the data is read out to the data bus line through the likewise main bit line B _2.

[0033] After the data of the memory transistor M ₄ is read, as shown in FIG. 2, falling signal Y _1, the rise of the signal Y _2, and selects the next group as a first selection means Will be. Then, the selection lines WBS and W
By setting each of the potentials of CS to “L” level, the potentials of the signal lines WBS ′ and WCS ′ become “H” level, and A
The output of the ND circuit 23 becomes "H" level. At this time, the outputs of the other AND circuits 21, 22, and 24 are at "L" level. Since the output of the AND circuit 23 is at the “H” level, the MOS transistors T ₁₄ and T ₁₅ are turned on. As a result, the main bit line B ₂ and the main column line C ₂ are selected. At the same time, the signal line WB
Since the potential of S ′ is at “H” level, the MOS transistor T ₃ is selected, and the main bit line B ₂ is connected to the MOS transistor T _3.
It is connected via a transistor T ₃ to the sub-bit line B _22. Further, since the potential of the signal line WCS 'is at "H" level, MOS transistor T ₈ is turned on,
Auxiliary column line C ₂₁ are electrically connected to the main column line C _2. As described above, by using the sub column line C ₂₁ and the sub bit line B ₂₂ , the memory transistor M ₅ is selected.

[0034] Hereinafter, while only the signal Y ₂ is at the "H" level, the signal Y ₁ is "H" Similarly select lines WB and when the level
The potentials of S and WCS are sequentially changed, and are sequentially selected as memory transistors M ₆ , M _7, .... After the cycle of the signal Y ₂ is completed, the signal Y _3, Y _4, advances the signal for selecting ... and the group. Now that you have reached the final of the column, lower the potential of the word line W _1, the potential of the word line W ₂ rises. Then, similarly, the memory transistors are sequentially selected, and the data is read out to the data bus line.

Block Dividing Configuration (FIG. 4) The ROM of this embodiment can have a configuration in which a memory cell block is divided as shown in FIG. Although the number of word lines is eight here, it does not have an essential difference from the ROM of FIG.

The ROM shown in FIG. 4 has a cell block MB ₁ divided into n blocks in a direction perpendicular to the word line extending direction.
It has a MB ₂ ··· MBn. Each cell block MB ₁ ,
Each of MB ₂ ... MBn has, as shown in FIG. 1 described above, each line which is alternately arranged and constantly used as a column line and a bit line, and memory transistors arranged in a matrix, _{WBS · X 1 ~WBS · Xn,} WBS '· X 1
'A MOS transistor controlled by · Xn, selection lines _{WCS · X 1 ~WCS · Xn,} WCS' ~WBS · X 1
ＭＯＳWCS ′ · Xn. Thus, by the block division, each cell block MB _1, MB ₂ ··· MB column lines and bit lines (not shown) in the _n is shorter in a direction perpendicular to the extension direction of the word line. Therefore, values such as resistance and parasitic capacitance can be reduced, and high-speed operation can be performed. This is particularly advantageous when the bit lines and the column lines are each formed of a diffusion region, as described later.

Thus, the n cell blocks MB ₁ ,
In MB ₂ ··· MB _n, commonly have main bit lines B ₀ to Bm are provided, the main bit line B ₀ to Bm are formed in the same direction as the forming direction of the bit line. Further, the n-number of cell blocks MB _1, MB ₂ ··· MBn, commonly is also provided a main column lines C ₁ ~Cm, likewise, these main column line C ₁ ~Cm also main bit line in parallel It is provided in.
The main bit lines B _{0 to} Bm and the main column lines C _{1 to} C
m are alternately arranged in the word line extension direction.

[0038] end of an extension direction perpendicular to the direction of the cell blocks MB ₁ word line, the load circuit 30 is provided. This load circuit 30 is supplied with a signal Φ ₁ for controlling the impedance of the MOS transistor constituting the load circuit 30. Thus, each main bit line B ₀
To Bm and the main column lines C _{1 to} Cm are connected to each cell block MB ₁ ,
By commonly using the MB ₂ ... MB _n , the load circuit 30 may be arranged at the end of the entire cell block, and the occupation area can be reduced and high integration can be achieved.

A column selection circuit 20 is provided at an end of the cell block MBn in a direction perpendicular to the word line extending direction. The column selection circuit 20 includes control signals WBS, W
CS is supplied, and at the same time, signals Y _{1 to} Ym for column selection from the column decoder are also supplied. Each of these signals selects one main column line and one main bit line as one group, and performs the above-described read operation. By using this manner in common each main bit lines B ₀ to Bm and the main column line C ₁ ~Cm each cell block _{MB 1, MB 2 ··· MB n} , similarly to the load circuit 30 column selection circuit What is necessary is just to arrange | position 20 at the edge part of the whole cell block, and it becomes possible to achieve high integration from reduction of an occupation area.

Layout when electrode layer is made of single-layer polysilicon (FIG. 5) Next, a layout when the electrode layer is formed of a single-layer polysilicon layer will be described with reference to FIG. The layout shown in FIG. 5 is only partially shown for simplification of the description, and is actually formed continuously in a pattern repeated in the Y and X directions in the figure.

As shown in FIG. 5, a plurality of polysilicon layers are formed on the silicon substrate 41 so as to extend in the X direction indicated by the dotted areas in the figure. In this layout, a pair of contact holes 4 arranged in the Y direction
The area between 2 and 42 is one cell block unit. In this cell block, select lines WBS'.Xn, WB
S · Xn, eight word lines W _{1 to} W _8, and a selection line WC
S'.Xn and WCS.Xn are each formed in a band-like pattern made of a polysilicon layer. These lines are separated by a predetermined interval, and ion implantation for channel stop is performed in a self-aligned manner.

The sub-bit lines B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂ and the sub-column lines C ₀₁ , C ₀₂ , C ₁₁ , C ₁₂ are formed with the Y direction as the longitudinal direction, as indicated by the thick solid lines in the figure. Is done. The patterns of the sub-bit lines B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂ and the sub-column lines C ₀₁ , C ₀₂ , C ₁₁ , C ₁₂ are respectively strip-shaped patterns, and particularly, under the thick oxide film (LOCOS). Is formed from the impurity diffusion region formed in the substrate. Note that the thick oxide film is omitted in the figure. These sub bit lines B ₁₁ ,
B ₁₂ , B ₂₁ , B ₂₂ and sub column lines C ₀₁ , C ₀₂ , C ₁₁ , C
Reference numeral ₁₂ denotes an impurity diffusion region formed below the thick oxide film on the surface of the silicon substrate 41, and thus is used as a source / drain region of each memory transistor. The sub-bit lines B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂ and the sub-column lines C ₀₁ , C ₀₂ , C ₁₁ , C ₁₂ are used to connect a MOS transistor and a memory transistor as second and third selecting means. In order to have the same channel direction, the position of the end in each cell block is characteristic.

That is, the sub-column lines C ₀₁ and C ₁₁ are formed in a range from the lower part of the word line W _{1 to} the lower part of the select line WCS ′ · Xn, and the end 47 extends to the lower part of the select line WCS · Xn. Has not been reached. Therefore, the contact hole 42
Can be extended to a position corresponding to the sub-column lines C ₀₁ and C ₁₁ . Auxiliary column line C _02, C ₁₂ is formed in a range ranging from the lower part of the word line W ₁ at the bottom of the selection line WCS · Xn. The impurity diffusion region extending from the contact hole 42 with the main column lines C ₀ and C ₁ extends in the Y direction on the extension of the bit line, and
, An end portion 48 is provided beyond the selection line WCS ′ · Xn. A mask pattern 43 indicated by a broken line in the figure is provided below the select line WCS'.Xn and in a region 49 between the impurity diffusion region extended from the contact hole 42 and the sub column lines C ₀₂ and C ₁₂ . Impurities are implanted to prevent channel formation by utilizing the same. Therefore, the sub-column lines C ₀₁ and C ₁₁ use the MOS transistors formed on the selection lines WCS ′ · Xn as the selection transistors, and the sub-column lines C ₀₂ and C ₁₂ use the MOS transistors formed on the selection lines WCS · Xn. Is a selection transistor. Each of these selection lines WCS '· Xn, since the MOS transistor formed in WCS · Xn, the channel direction is the same as the channel direction of the memory transistors, as in the portion of the word lines W ₁ to _W-8, Self The channel stopper region can be easily formed by alignment, which is advantageous for reduction of the occupied area and high integration.

Similarly, the bit line is also designed so that the channel direction of the transistor for selection is set in the X direction, and the sub-bit lines B ₁₂ and B ₂₂ are
₈ is formed in the range from the lower part of the selection line WBS.Xn to the lower part of the selection line WBS.
It does not reach the lower part of S ′ · Xn. Therefore, the periphery of the contact hole 42 can be extended on the extension of the sub-bit lines B ₁₂ and B ₂₂ . Also, the sub bit lines B ₁₁ ,
B ₂₁ is the selection line WBS '· Xn from the bottom of the word line W ₈
And the selection line WBS ′ · Xn near the contact hole 42 can be used as the gate of the selection MOS transistor. A region 6 between the sub-bit lines B ₁₁ and B ₂₁ and the impurity diffusion region extending the contact hole 42 connecting the main bit lines B ₁ and B _2.
0 is used as a channel stopper region using the mask pattern 43. The impurity diffusion region has a sub-column line C
_02, as an extension of C ₁₂ extending in the Y direction, the end portion 46
Exists at a position across two select lines WBS'.Xn and WBS.Xn. Therefore, the main bit lines B ₁ and B ₂ are alternatively connected to the sub bit lines, and the main bit lines B ₁ and B ₂ are connected to the sub bit lines B ₁₁ and B ₂₁ by using the selection line WBS ′ · Xn. , And the main bit lines B ₁ ,
B ₂ is connected to the sub-bit line B _12, B _22. As in the case of the sub column line, the channel direction is the word line W ₁
And to _W-8 are the same direction, which is advantageous for miniaturization and the like.

The mask pattern 43 can also serve as a mask 44 for ion implantation of a program which is implanted to prevent channel formation of each memory transistor. Therefore, the process can be simplified, and the TAT
(Turn-around time) is advantageous.

The main bit lines B ₁ and B ₂ are made of an aluminum-based wiring layer extending in the Y direction in the figure. The main column lines C ₀ and C ₁ are also made of an aluminum-based wiring layer extending in the Y direction in the figure. The main bit lines B ₁ , B ₂ and the main column lines C ₀ , C ₁ are in the form of strips parallel to each other, and are connected to an impurity diffusion region formed on the surface of the silicon substrate 41 in the region of the contact hole. . In the read-only memory device of the present embodiment, the contact holes 42 of the main bit lines B ₁ and B ₂ and the main column lines C ₀ and C ₁ are connected to the Y of the cell block.
In the direction, it is divided and formed. For this reason,
The contact holes 42 are not arranged adjacent to each other in the X direction, which is advantageous for integration.

Layout when electrode layer is made of two-layer polysilicon (FIG. 6) Next, a layout when the electrode layer is formed of two polysilicon layers will be described with reference to FIG. The layout shown in FIG. 6 is only a part shown in FIG. 5 for the sake of simplicity of explanation, and is actually continuous in a pattern repeated in the Y direction and the X direction in the drawing. It is formed.

As shown in FIG. 6, the ROM of this embodiment using the two polysilicon layers as the electrode layers has a first polysilicon layer and a second polysilicon layer on a silicon substrate 51. Each of the electrode layers has a band-like pattern extending in the X direction. From the first polysilicon layer, select lines WBS.Xn, WCS.Xn, WCS.X
n + 1 and word lines W ₂ , W ₄ , W ₆ , W ₈ are formed, and select lines WBS ′ · Xn, WC are formed from the second polysilicon layer.
S '· Xn, WCS' · Xn + 1, word lines W _1, W _3, W
₅ , W ₇ is formed. The spacing between the first and second polysilicon layers serving as selection lines on the plane is the spacing between the thin interlayer insulating films only, and is arranged sufficiently close to overlap the ends in the Y direction. Also, the intervals between the word lines W _{1 to} W ₈ are arranged sufficiently reduced in the Y direction, taking advantage of the advantage of the two-layer polysilicon layer. The word lines W _{1 to} W ₈ are subjected to ion implantation for programming using the mask pattern 54. This ion implantation can be performed in a self-aligned manner, which is effective for downsizing. The structure of this word line portion will be described later. Note that the selection line may be formed by arranging a single polysilicon layer without forming a two-layer structure.

One cell block is provided in a region between contact holes 52 in the Y direction. Since the width of the cell block in the Y direction is two as described above, it can be shorter than that of a single layer.

In this cell block, the sub-bit lines B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂ and the column lines are formed in a belt-like pattern parallel to each other with the Y direction in the drawing as the longitudinal direction.
The patterns of the sub-bit lines B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂ and the sub-column lines C ₀₁ , C ₀₂ , C ₁₁ , C ₁₂ are formed particularly in the impurity diffusion region formed under the thick oxide film (LOCOS). Consists of Note that the thick oxide film is omitted in the figure.
The sub bit lines B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂ and the sub column lines C ₀₁ , C ₀₂ , C ₁₁ , C ₁₂ function as source / drain regions of each memory transistor. The sub-bit lines B ₁₁ , B ₁₂ , B ₂₁ , B ₂₂ and the sub-column lines C ₀₁ , C ₀₂ , C ₁₁ , C ₁₂ are used to connect a MOS transistor and a memory transistor as second and third selecting means. In order to have the same channel direction, the length in the Y direction in each cell block is adjusted.

First, the sub-column lines C ₀₁ , C ₀₂ , C ₁₁ , C ₁₂
Has been formed in a pattern that starts from the bottom of the word line W _1, auxiliary column line C _01, C ₁₁ is the end portion 57 is to the bottom of the selection line WCS '· Xn, column lines C _02,
C ₁₂ extends to below the selection line WCS · Xn. Therefore, the impurity diffusion region of the contact hole 52 can be extended to a position corresponding to the line of the column lines C ₀₁ and C ₁₁ . The impurity diffusion region connected to the contact hole 52 extends over the selection line in the Y direction on the extension of the bit line, and since it functions as one of the source / drain regions of the MOS transistor, The lines C ₀₁ and C ₁₁ use the MOS transistors formed on the selection lines WCS ′ · Xn as selection transistors,
For the sub column lines C ₀₂ and C ₁₂ , MOS transistors formed on the selection lines WCS · Xn are used as selection transistors. To form such a select transistor, the region 59
Then, ion implantation for preventing channel formation is performed using the mask pattern 53. This mask pattern can be formed by the same process as the program performed on the lower portion of the second polysilicon layer. Each of these selection lines W
CS · Xn, since the MOS transistor formed in WCS '· Xn, the channel direction is the same as the channel direction of the memory transistor, the word line W ₁ to _W-8
As in the above case, the channel stopper region can be easily formed by self-alignment, which is advantageous for reducing the occupied area and increasing the degree of integration.

The sub bit lines B ₁₁ , B ₁₂ , B ₂₂ , B ₂₁
Pattern is starting respectively from the bottom of the word line W _8, sub bit lines B _12, B _22, the end 55 is selected line W
Up to the lower portion of BS.Xn, the sub-bit lines B ₁₁ and B
₂₁ is formed in a range extending below the selection line WBS ′ · Xn. With such a pattern, the MOS transistors in the channel direction and the X direction are connected to the respective select lines WB
S.Xn and WBS'.Xn. Therefore, it is advantageous for reducing the occupied area. On this bit line side, the region 61 between the sub-bit lines B ₁₂ and B ₂₂ and the impurity diffusion region is
A channel stopper region is formed by using a mask pattern 53 used at the time of programming.

The main bit lines B ₁ , B ₂ and the main column lines C ₀ ,
C ₁ is made of an aluminum-based wiring layer is extended in the Y direction of the drawing. The main bit lines B ₁ , B ₂ and the main column lines C ₀ , C ₁ are in a band-like pattern parallel to each other. Therefore, it is advantageous for miniaturization. In addition, these main bit lines B
₁ , B ₂ and main column lines C ₀ , C ₁ are contact holes 5
The region 2 is connected to an impurity diffusion region formed on the surface of the silicon substrate 41. In the read-only memory device of this embodiment, the contact holes 52 of the main bit lines B ₁ and B ₂ and the main column lines C ₀ and C ₁ are arranged in the Y direction of the cell block.
It is distributed and formed. Therefore, the contact holes 52 are not arranged adjacent to each other in the X direction, which is advantageous for integration.

Cell Structure (FIGS. 7 to 11) Next, the structure of the memory cell portion will be described with reference to FIGS.

FIG. 7 is a plan view of a cell portion of the ROM of this embodiment having a two-layer polysilicon layer structure. In the figure, a hatched area indicates a thick oxide film 102 formed on the surface of a p-type semiconductor substrate 101, and extends in the Y direction in the figure in parallel with each other in a band-like pattern. This thick oxide film 1
The source / drain region 107 is formed below the layer 02 in a consistent manner. Then, in the X direction in the drawing, which is a direction orthogonal to the thick oxide film 102, the first polysilicon layer 103 and the second A second polysilicon layer 104 as an electrode layer is formed. The first polysilicon layer 103 is formed in a strip-shaped pattern parallel to each other, and adjacent patterns have an interval of width l ₁ . The second polysilicon layer 104 is formed so as to cover the region between the first polysilicon layers 103, and a part of each end in the Y direction is a first polysilicon layer. 103 overlaps the end of 103 on a plane. Therefore, in the Y direction, the memory transistors are formed in parallel without leaving a substantial interval, and the read-only memory device can be highly integrated.

The substantially square pattern 105 is a window portion of a program mask formed by ion implantation into the lower portion of the first polysilicon layer 103.
Reference numeral 6 denotes a window portion of a program mask formed by ion implantation below the second polysilicon layer 104. Each of the patterns 105 and 106 is wider than the width of the polysilicon layers 103 and 104 in the Y direction, and has a large opening extending over a pair of thick oxide films 102 and 102 in the X direction. At the time of ion implantation using the pattern 105, a pair of thick oxide films 10
2 and 102 also function as part of the mask. And Y
The portion protruding in the direction is the first polysilicon layer 1.
Since it is scraped off by etching consistent with 03, it is resistant to mask misalignment. In addition, at the time of ion implantation using the pattern 106, a pair of thick oxide films 102, 102 and the first polysilicon layer 1 are formed together with the resist mask.
Since 03 functions as a mask, it is resistant to mask misalignment. Therefore, even if the integration is performed with a high degree of integration, the program can be reliably performed.

FIGS. 8 and 9 are cross sections in the X direction in the drawings. FIG. 8 is a cross section cut at the second-layer polysilicon layer 104. On the surface of the p-type silicon substrate 101, thick oxide films 102, 102 separated on the surface are provided.
Are formed. On the surface of the silicon substrate 101 therebelow, an n ⁺ -type impurity region 107 is formed in a consistent manner. This n ⁺ -type impurity region 107 functions as a source / drain region of the memory transistor. The surface of the substrate in a region sandwiched between the pair of thick oxide films 102, 102 is shaved and deepened, and a groove 109 is formed. On the bottom and side surfaces of the trench 109, a gate oxide film 108 formed thinner than the thick oxide film 102 is formed.

Then, the second polysilicon layer extends from over the gate oxide film 108 to over the thick oxide film 102 and further over the gate oxide film 108 of another memory transistor. 104 are formed continuously on the cross section. The polysilicon layer 104 is formed in contact with the gate oxide film 108 in a region sandwiched between the pair of thick oxide films 102, 102.
02 and 102 are sufficiently separated from the n ⁺ -type impurity region 107.

FIG. 9 is a cross section in the X direction of FIG. 7, but a cross section of the first polysilicon layer 103. In the cross section of FIG. 9, similar to FIG.
A thick oxide film 102 is formed on the silicon substrate 101 at a distance, and the lower portion of the thick oxide film 102
⁺ Type impurity region 107 is formed. This n ⁺ -type impurity region 107 functions as the source / drain region of the memory transistor. However, in the region between the pair of thick oxide films 102, the silicon substrate 101 is not shaved, and only the gate oxide film 108 is formed on the main surface of the substrate. First polysilicon layer 1
Numeral 03 extends from the gate oxide film 108 formed on the main surface of the substrate to the thick oxide film 102 along the cross-sectional direction, and further extends to the gate oxide film 10 of another memory transistor.
8 continuously.

Next, FIGS. 10 and 11 are cross-sectional views in the Y direction of FIG. 7, and FIG. 10 is a cross-sectional view cut at the thick oxide film 102. In this cross section, a linear n ⁺ impurity region 1 is formed on the surface of p-type silicon substrate 101.
A thick oxide film 102 is formed along 07. On this thick oxide film 102, a first polysilicon layer 103 and a second polysilicon layer 104 are formed alternately. An end of the second polysilicon layer 104 overlaps an end of the first polysilicon layer 103 via an interlayer insulating film (not shown).

FIG. 11 is a cross section of a portion corresponding to a channel forming region of each memory transistor. In this cross section, the surface of the silicon substrate 101 in a region corresponding to the second polysilicon layer 104 is shaved and deepened. Then, the second polysilicon layer 104 is formed on the deepened trench 109 via the gate oxide film 108. The first polysilicon layer 103 is formed on the gate oxide film 108 formed on the main surface of the substrate. The memory transistor is formed for each of the polysilicon layers 103 and 104. Therefore, the transistors adjacent to each other in the cross-sectional direction in FIG. 11 have different heights of the main surface of the substrate in the channel formation region. In these channel formation areas,
As shown in FIG. 10, p-type impurities are selectively introduced to form impurity regions 110 and 111. The memory transistor in which the impurity regions 110 and 111 are formed in the channel formation region is not turned on even when the word line is selected due to an increase in the potential, and is an n ⁺ -type pair of source / drain regions. Impurity region 107, 1
There is no conduction during 07. On the other hand, in a memory transistor in which a p-type impurity region is not formed, n ⁺ -type impurity regions 107 and 1 serving as a pair of source / drain regions are formed.
During the period of 07, it becomes conductive at the time of selection. Due to this difference in operation, programmed data can be read.

In the read-only memory device of this embodiment having such a structure, the p-type impurity region 107 serving as the source / drain region is formed below the thick oxide film 102, so that high integration is achieved. It is possible to increase the capacity of the ROM. The structure of the memory cell is N
Because of the OR type, the memory transistors are formed in parallel between a common source and a common drain. Therefore, the driving capability of the memory cell does not change according to the number of transistors, and reliable and high-speed data reading can be performed with sufficient driving capability. Further, in the read-only memory device of this embodiment, the electrode layer is composed of two polysilicon layers 103 and 104, and the second polysilicon layer 104 is replaced with the first polysilicon layer 10.
By forming the memory transistors in parallel with the region between the three, the memory transistors can be arranged tightly along the longitudinal direction of the thick oxide film 102 without any gap. This is advantageous for high integration, and in particular, the first polysilicon layer 103
By providing a step between the lower portion of the polysilicon layer 104 and the lower portion of the second polysilicon layer 104, reliable programming is possible.

Process for Forming Source / Drain Regions (FIGS. 12A to 12C) Next, a p-type impurity region 123 to be a source / drain region is formed in a lower portion of a thick oxide film 124 in a consistent manner. FIG. 12 (a) to FIG.
This will be described with reference to FIG.

First, an oxidation resistant film 121 made of a silicon nitride film is formed on a p-type silicon substrate 120 via a pad oxide film. Then, a resist layer 122 is applied on the oxidation-resistant film 121. Next, the resist layer 12
2 is selectively exposed to a pattern for forming a thick oxide film and developed. This pattern is a pattern that is opened in a band shape parallel to each other in the region of the memory cell array.
Subsequently, the resist layer 122 having such a pattern is formed.
Patterning of the oxidation-resistant film 121 using RIE, for example.
It is performed using a method or the like.

Next, as shown in FIG. 12A, using the resist layer 122 and the oxidation-resistant film 121 as a mask, n
Type impurities, for example, arsenic ions are implanted at a high concentration by ion implantation. This ion implantation allows the silicon substrate 12
On the 0 surface, n-type impurity regions 123 are formed in a band-like pattern parallel to each other. This n-type impurity region 1
23 can be formed in the same manner as the formation of a channel stopper region formed below a normal field oxide film.

Next, the resist layer 122 is removed by ashing or the like, and the whole is oxidized. As a result of this oxidation, the surface of the region where the oxidation-resistant film 121 is not formed, that is, the region where the n-type impurity region 123 is formed is formed as shown in FIG.
As shown in (b), a thick oxide film (LOCOS) 124
Is formed. By forming the thick oxide film 124 using the oxidation-resistant film 121 as a mask in this manner, a thick oxide film 124 that is consistently overlapped with the n-type impurity region 123 is obtained.

Subsequently, the oxidation resistant film 121 is removed, and the region where the oxidation resistant film 121 has been formed is oxidized to obtain a region shown in FIG.
As shown in (c), a gate oxide film 125 is formed.
The gate oxide film 125 has a smaller thickness than the thick oxide film 124. Then, implantation of impurities for forming a program, formation of an electrode layer, and the like are performed.

Program and Electrode Formation Process (Thirteenth
(FIG. 13 (a) to FIG. 13 (c)) Next, FIG. 13 (a) to FIG.
With reference to FIG. 3 (c), the process of selectively implanting the impurities of these programs and the process of forming the electrode layer will be described.

First, as shown in FIG. 13A, impurities are selectively ion-implanted below the gate oxide film 131 of the silicon substrate 130. For this ion implantation, a required mask 132 is used.
At 34, the impurities are implanted on the surface of the substrate through which the impurities have passed. The impurity to be implanted is, for example, a p-type impurity such as boron, and the opening portion 134 of the mask 132 can be made wider than a region to be a channel forming region of a memory transistor. This is because the thick oxide film functions as a part of the mask, and as described below, the substrate surface in a region protruding from the first polysilicon layer is etched away, so that a large area is formed. No problem occurs even if ion implantation is performed. Note that the mask 132
For example, it is composed of a resist layer or the like. The region 133 into which the impurity is implanted serves as a channel formation region of the transistor whose threshold voltage is set to a high voltage.

Next, the mask 132 is removed, and the first polysilicon layer 135 is formed on the entire surface of the gate oxide film 131.
To form This first polysilicon layer 135 is
The thick oxide film is patterned in a band shape in a pattern parallel to each other in a direction perpendicular to an in-plane direction of a cross-sectional view which is a longitudinal direction of the thick oxide film. After the patterning of the first polysilicon layer 135, the gate oxide film 131 in a region between the first polysilicon layers 135 is removed, and the exposed silicon substrate 130 is etched from the surface. To form a groove 136 in alignment with the first polysilicon layer 135. At the time of this etching, the end portion of the impurity region 133 formed wider is shaved. Impurity region 13
Since the end of the third layer is etched away, only the lower portion of the first polysilicon layer 135 is surely programmed.

As described above, the first polysilicon layer 13
After the grooves 136 are formed in alignment with the openings 5, as shown in FIG. 13B, the openings 13 for selectively implanting impurities are formed.
A mask 137 having 8 is formed. This opening 138
The window is selectively formed in a region where the second polysilicon layer is to be formed, and the size of the opening 138 is actually smaller than the channel below the second polysilicon layer 136. The area is larger than the area to be the area. This is the first polysilicon layer 13 already formed.
This is because the oxide film as thick as 5 functions as a part of the mask.
Sufficient data can be written even when high integration is achieved. Then, a p-type impurity, for example, boron is ion-implanted using the mask 137, and the trench 136 is selectively formed.
Is implanted into the region according to. The region 139 into which impurities are implanted in this manner is also used as a channel formation region of a transistor having a high threshold voltage, similarly to the region 133.

Next, the mask 137 is removed, and an interlayer oxide film and a gate oxide film 140 are formed by thermal oxidation or the like. The interlayer oxide film covers the surface of the first polysilicon layer 135. Further, the gate oxide film 140 is formed in the groove 136.
Is formed by oxidizing the side walls and bottom surface of the substrate. After forming the interlayer oxide film and the gate oxide film 140 in this manner, a second-layer polysilicon layer 141 is formed on the entire surface by, for example, a CVD method. This second polysilicon layer 141 is
It is formed along the side wall and bottom surface of the groove 136. After the second-layer polysilicon layer 141 is formed on the entire surface in this way, the second-layer polysilicon layer 141 is patterned. The patterning is performed so that the second-layer polysilicon layer 141 has a band-like pattern parallel to each other. The second-layer polysilicon layer 141 is formed between the first-layer polysilicon layers 135. Groove 136 formed in
Is formed so that a part of the end in the cross-sectional direction covers the end of the first-layer polysilicon layer 135 via the interlayer oxide film. Second polysilicon layer 141
Is formed, a silicon oxide film (for example, PSG) 142 is further formed as an interlayer insulating film, and an aluminum-based wiring layer 143 is formed on the silicon oxide film 142.
Are formed in a required pattern. The aluminum-based wiring layer 143 functions as a main bit line or a main column line connected to the n ⁺ -type impurity region below the thick oxide film. Hereinafter, a passivation film is formed according to a normal process to complete a read-only memory device.

In the above-described method for manufacturing a read-only memory device, since the impurity region 123 serving as the source / drain region is formed below the thick oxide film 124, the impurity for programming is consistent with the polysilicon layer. Does not affect the source / drain regions. Also, 2
In order to form a polysilicon layer and further form a groove 136 in alignment with the first polysilicon layer 135,
Mask 132 for introducing impurities for programming, 1
The openings 134 and 138 of the 37 may have a wide pattern,
It becomes strong against misalignment of the mask. Also, the first polysilicon layer 135 and the second polysilicon layer 1
The structure in which the memory cells 41 are arranged in parallel and sufficiently close to each other with only a thin interlayer oxide film therebetween enables high-density memory cells to be arranged.

In the above description, the groove 136 is formed below the second polysilicon layer. However, the groove may not necessarily be formed if the problem of program mask alignment can be solved. Further, the electrode layer is not limited to the polysilicon layer, and may be a refractory metal silicide, a polycide structure, a refractory metal layer, or the like. Further, the material of the insulating film is not limited to the oxide film, and a structure in which a nitride film or the like is combined may be employed.

Layout of Column Select Circuit (FIG. 17) FIG. 17 shows a layout of a part of the column select circuit. In the drawing, a region with a dotted line is a polysilicon layer, and a signal line 71 to which signals Y _{0 to} Y ₆ are supplied from a column decoder.
It has become. Each of these signal lines extends in a band shape in the Y direction, and is arranged at a fixed interval l _{2 in} the X direction. Since the main bit line and the main column line are each divided into two sub-bit lines and sub-column lines as described above, the interval l ₂ corresponds to an interval twice the memory cell pitch.

In the figure, in the Y direction, the main column lines C ₁ ,
C _2, C ₃ and main bit lines B ₁ , B ₂ , B ₃ are alternately formed in a band-like pattern, as shown by the hatched area in the figure. These main column lines C ₁ , C ₂ , C ₃ and main bit lines B ₁ ,
B ₂ and B ₃ are each made of an aluminum-based wiring layer.

On the silicon substrate 70, a ground line 72 formed of a diffusion region is formed. The ground line 72 extends in the Y direction below the main bit lines B ₁ , B ₂ , and B ₃ , and the extended region 73 becomes one of the source / drain regions of the select transistor Tc. That is, the gate electrode of the select transistor Tc is formed of the signal line 71, and the other source / drain region is the region 74.
This region 74 is connected to each main column line C ₁ , C ₂ , C ₃ via a contact hole 75 formed on the surface. Therefore, the potential of the signal line 71, region 74 and region 73 are rendered conductive, the potential of the main column lines C _1, C _2, C ₃ is selectively grounded potential. One extended area 73
Are common sources and drains of the two select transistors Tc. The region 74 below one contact hole 75 also serves as a common source / drain of the two select transistors Tc. Therefore, the degree of integration is high.

Data bus lines 76 made of an aluminum-based wiring layer are formed in a pattern extending in the X direction in the figure. This data bus line 76 is connected to a contact hole 77
Is electrically connected to the diffusion region 78 via The diffusion region 78 faces the diffusion region 79 with the signal line 71 interposed therebetween. These diffusion regions 78 and 79, functions as a source-drain region of the select transistor T _B, the signal line 7
1 becomes the gate electrode. Each diffusion region 79 is electrically connected to main bit lines B ₁ , B ₂ , and B ₃ via contact holes 80. Therefore, the main bit lines B ₁ , B _2, B ₃
Is electrically connected to the data bus line 76 only in the column of the selected signal line 71, and is amplified and output via the sense amplifier.

Second Embodiment This embodiment is a modification of the ROM of the first embodiment.
In particular, this is an example in which the circuit configuration of the column selection circuit is different. Since the other parts of the circuit have the same configuration, only the part of the column selection circuit will be described with reference to FIG. 14 to simplify the description.

The column selection circuit 2a is connected to the memory cell block 1
A circuit for electrically connecting the main bit line B _1, B _2, B ₃ and the main column lines C _1, selectively ground line and the data bus line C ₂ of the signal Y _1, Y ₂ It is controlled based on.

In the column selection circuit 2a of this embodiment, the main column lines C ₁ and C ₂ are controlled directly based on the signals Y ₁ and Y ₂ . That is, the main column line C ₁ is connected to the MOS transistor T
Is connected to the ground line via a _35, the gate of the MOS transistor T ₃₅ is the signal Y ₁ is supplied. The main column line C ₂ is connected to the ground line via a MOS transistor T _38, the gate of the MOS transistor T ₃₈ is the signal Y ₂
Is supplied.

[0082] Next, the main bit lines B _1, B _2, B _3, the signal Y _1, is controlled by Y _2, further main bit lines according to the bit lines selected within the same group B ₁ , B ₂ and B ₃ need to be selected, the selection lines WBS, WCS, WB
A MOS transistor operated by each signal of S ′ and WCS ′ is provided. That is, the main bit line B ₁ is electrically connected to the data bus line via the MOS transistors T ₃₄ and T ₃₀ connected in series. The main bit line B ₂ is electrically connected to the data bus line via the MOS transistors T ₃₆ and T ₃₂ connected in series, and electrically connected via the MOS transistors T ₃₇ and T ₃₁ connected in series. The data bus line is connected to the data bus line through two paths, ie, the data bus line. The main bit line B ₃ is electrically connected to the data bus line through the MOS transistor T _33, T _39, which are connected in series. Note that the main bit lines B ₁ and B ₃ are also 2
Although it may have one path, its illustration is omitted for simplicity. MOS transistors T ₃₀ and T ₃₁ are turned on by the logical product of the signals of select lines WBS ′ and WCS ′, and MOS transistors T ₃₂ and T ₃₃ are connected to select line WB.
It is turned on by the logical sum of the S and WCS signals.
Therefore, the MOS transistors T ₃₀ and T ₃₂ are not simultaneously turned on, and the MOS transistors T ₃₁ and T ₃₃ are not simultaneously turned on. Therefore, the signals Y ₁ ,
Even when a certain group is selected by Y ₂ , the main bit lines B ₁ , B ₂ , and B ₃ are alternatively selected, and further, the operation of selecting one sub-cell line and sub-column line is performed with one cell. The data can be read.

In the column selection circuit 2a according to the present embodiment, the number of transistors is significantly reduced as compared with the column selection circuit 2 according to the first embodiment. Therefore, the column selection circuit 2a
This makes it easy to reduce the occupied area.

Third Embodiment This embodiment is a modification of the ROM of the first embodiment.
In particular, in order to perform high-speed reading by precharging the main bit line and the main column line, the circuit configuration of the load circuit and the column selection circuit are different. Since other parts of the circuit have the same configuration, only different circuit parts will be described with reference to FIGS. 15 and 16 for simplification of the description.

The ROM of the third embodiment is similar to the ROM of FIG.
As shown in FIG. 7, a memory cell block 1 similar to that of the first embodiment is provided. The memory cell block 1 has main bit lines B ₁ , B ₂ , B ₃ and main column lines C ₁ , C ₂ extending in a direction perpendicular to the word line extending direction. From each of these main bit lines and main column lines, two sub-bit lines and two sub-column lines are provided separately, as in the first embodiment.

At the end of the bit line of the memory cell block 1 in the extending direction, a load circuit 3a is provided. Other having the load circuit 3a main bit lines B _1, B _2, B ₃ and MOS transistors _{T 40, T 42, T 44} , T 46, T 48 to provide the required impedance to the main column line C _1, C ₂ Have MOS transistors T ₄₁ , T ₄₃ , T ₄₅ , T ₄₇ , and T ₄₉ for performing precharge. One of the sources of the MOS transistors T ₄₀ , T ₄₂ , T ₄₄ , T ₄₆ , T ₄₈
The drain region is connected to a power supply line, and the other source / drain region is connected to a main bit line or a main column line. These MOS transistors T ₄₀ , T ₄₂ , T ₄₄ ,
The signal Φ ₂ ′ is commonly supplied to the gates of T ₄₆ and T ₄₈ . Also, MOS transistors T ₄₁ , T ₄₃ , T ₄₅ ,
While the source and drain regions of the T _47, T ₄₉ is also connected to the main bit line or main column line, also other source-drain region is likewise connected to the power supply line. The signal φ ₁ ′ is commonly supplied to the gates of the MOS transistors T ₄₁ , T ₄₃ , T ₄₅ , T ₄₇ , and T ₄₉ . This signal Φ ₂ ′ becomes “H” level when the selected memory transistor is switched as described below. When this signal Φ ₂ becomes “H” level, precharge is performed.

At the other end of the memory cell block 1 in the direction in which the bit lines extend, a column selection circuit 2b is provided. The column selection circuit 2b has the same structure as the column selection circuit 2 of the first embodiment, but the MOS transistor T
MOS transistors T ₅₀ , T ₅₁ , T ₅₂ , and T ₅₃ functioning as switches are formed between ₁₁ , ₁₁ , T ₁₂ , T ₁₅ , and T ₁₆ and the ground line. These MOS transistors T ₅₀ ,
The signal Φ ₂ is supplied to the gates of T ₅₁ , T ₅₂ , and T ₅₃ , and is turned on when the signal Φ ₂ is at the “H” level.
The signal is turned off when the signal Φ ₂ is at the “L” level. MOS
With the transistors T ₅₀ , T ₅₁ , T ₅₂ , T ₅₃ turned off, the main column lines C ₁ , C ₂ are disconnected from the ground level, thus enabling effective precharge.

Next, the operation of the ROM according to the third embodiment will be briefly described with reference to FIG. Since the operation of the present embodiment is obtained by adding the precharge operation to the operation of the first embodiment, the precharge operation will be described for simplicity.

At the beginning of a certain cycle, the signal Φ ₂ ′ rises from the “L” level to the “H” level, and as a result, the MOS transistors T ₄₁ , T ₄₃ , T _{43 of the} load circuit 3a.
₄₅ , T ₄₇ and T ₄₉ are turned on. Further, since the signal [Phi ₂ falls, MOS transistors T ₅₀ of the column selection circuit _{2b, T 51, T 52,} T 53 are turned off. As a result, the potentials of the main column lines C ₁ and C ₂ and the main bit lines B ₁ , B ₂ and B ₃ are raised to the power supply voltage Vcc.

After the precharge is performed and before the driving of the memory transistor of the memory cell block 1 is started, the signal Φ ₂ ′ is set to the “L” level again, and the signal Φ ₂ is set to the “H” level. Be leveled. This turns off the MOS transistors T ₄₁ , T ₄₃ , T ₄₅ , T ₄₇ , and T ₄₉ ,
The MOS transistors T ₅₀ , T ₅₁ , T ₅₂ and T ₅₃ are turned on. Now you can read data,
Hereinafter, the read operation is performed in the same manner as in the first embodiment.

In the ROM according to the third embodiment, since the main bit lines and the main column lines are precharged, data can be read at high speed.

In the above embodiment, two bit lines and two column lines correspond to one main bit line and one main column line. However, the present invention is not limited to this. is not.

[0093]

According to the read-only memory device and the method of manufacturing the read-only memory device according to the present invention, since the impurity region is formed below the thick oxide film, high integration is possible, and the size of the ROM can be increased. The capacity can be increased.
Further, the second electrode layer is parallel to the first electrode layer,
The memory transistor is selectively formed on the semiconductor substrate corresponding to the etched region sandwiched between the first and second electrode layers so as to have a portion overlapping the first electrode layer. Can be arranged without opening, which is advantageous for high integration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a main part of an example of a read-only memory device according to the present invention.

FIG. 2 is a timing chart showing an example of the operation of the read-only memory device.

FIG. 3 is a diagram showing an overall block configuration of the read-only memory device.

FIG. 4 is a block diagram showing a configuration when the read-only memory device is divided into blocks.

FIG. 5 is a layout in the case where the electrode layer of the read-only memory device is formed of a single polysilicon layer.

FIG. 6 is a layout in the case where the electrode layer of the read-only memory device is formed of two-layer polysilicon.

FIG. 7 is a layout of a memory cell of the read-only memory device.

FIG. 8 is a sectional view taken along the line VIII-VIII of FIG. 7;

FIG. 9 is a sectional view taken along the line IX-IX of FIG. 7;

10 is a cross-sectional view of the memory cell of FIG. 7 taken along line XX.

FIG. 11 is a sectional view taken along line XI-XI of the memory cell of FIG. 7;

FIG. 12 is a cross-sectional view for explaining a step of forming source / drain regions of a memory transistor of the read-only memory device.

FIGS. 13A and 13B are cross-sectional views illustrating a process of forming a memory transistor and an electrode layer of the read-only memory device.

FIG. 14 is a circuit diagram of a main part of another example of the read-only memory device.

FIG. 15 is a main part circuit diagram of still another example of the read-only memory device.

FIG. 16 is a timing chart for explaining an operation of the example of the read-only memory device shown in FIG. 15;

FIG. 17 is a layout of a column selection circuit of another example of the read-only memory device shown in FIG. 1;

FIG. 18 is a main part circuit diagram of an example of a conventional read-only memory device.

FIG. 19 is a layout of an example of the read-only memory device.

[Explanation of symbols]

M ₁ ~M ₇ memory _{transistor, T 1 ~T 4 T 11 ~T} 22
MOS transistor, B _{1 to} B ₃ main bit line, C ₁
C ₂ main column _{lines, B 12 B 21 B 22 B} 31 sub-bit _{line, C 11 C 12 C 21 C} 22 auxiliary column lines, one memory cell block, 22a 2b column select circuit, 3 3a
Load circuit, 21 to 24 AND circuit

Claims (5)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type, a thick oxide film formed in a band shape in parallel with a surface of the semiconductor substrate of the first conductivity type, and a thin oxide film in contact with a bottom of the thick oxide film. A source / drain region of a second conductivity type having a conductivity type opposite to the first conductivity type formed on the semiconductor substrate; and a first electrode layer formed in a strip shape substantially orthogonal to the thick oxide film. A second electrode layer formed in a strip shape on the semiconductor substrate, which is parallel to the first electrode layer, and has a portion overlapping with the first electrode layer on the semiconductor substrate sandwiched between the first electrode layers; Between the thick oxide film, a gate oxide film formed thinner than the thick oxide film on the surface of the semiconductor substrate under the first electrode layer, and between the thick oxide film, A thickness greater than that of the thick oxide film on the surface of the semiconductor substrate under the second electrode layer; A read-only memory device comprising: a gate oxide film formed thin. 2. A groove formed between the thick oxide films in the semiconductor substrate region below the second electrode layer in a self-aligned manner with respect to the first electrode layer and the thick oxide film. 2. The read-only memory device according to claim 1, wherein said gate insulating film is formed on a surface of said semiconductor substrate in a region. 3. The semiconductor device according to claim 1, wherein the first conductivity type is a p-type, and the second conductivity type is an n-type.
A read-only memory device according to any of the preceding claims. 4. A first step of forming an oxidation-resistant film on a surface of a semiconductor substrate of a first conductivity type; a second step of forming a strip-shaped resist layer in parallel on the oxidation-resistant film; A third step of etching the oxidation-resistant film using the resist layer as a mask, and using the stacked film of the resist layer and the oxidation-resistant film as a mask, the first conductivity type and the conductivity type are reversed on the semiconductor substrate. A fourth step of introducing a certain second conductivity type impurity, a fifth step of removing the resist layer, and a step of forming a thick oxide film by oxidizing the semiconductor surface using the oxidation resistant film as a mask. A sixth step of removing the oxidation-resistant film; an eighth step of forming a gate oxide film thinner than the thick oxide film on the surface of the semiconductor substrate between the thick oxide films; Selectively in the region where the gate oxide film is formed A ninth step of introducing an impurity of the first conductivity type; a tenth step of forming a strip-shaped first electrode layer in a direction substantially orthogonal to a longitudinal direction of the thick oxide film; An eleventh step of etching the gate oxide film and the semiconductor substrate using the electrode layer as a mask, and a twelfth step of selectively introducing a first conductivity type impurity into the semiconductor substrate corresponding to the etched region. A thirteenth step of forming a gate oxide film thinner than the thick oxide film on the semiconductor substrate corresponding to the etched region and the first electrode layer; Forming a second electrode layer selectively on the semiconductor substrate corresponding to the etched region sandwiched between the first electrode layers, the second electrode layer having a portion overlapping the first electrode layer; Read only Of manufacturing a memory device for a semiconductor device. 5. The semiconductor device according to claim 1, wherein the first conductivity type is a p-type, and the second conductivity type is an n-type.
A manufacturing method of the read-only memory device according to the above.