JPH11186528A - Nonvolatile semiconductor storing device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the workability of bit lines by arranging the positioning pattern of a source impurity region and contact, to reduce the area of a cell array by reducing area other than effective cells in a NAND string, and to improve the accuracy of readout. SOLUTION: A drain impurities region 6b and a source impurities region 20 are formed in a semiconductor layer 4. Selected transistors S11, S12 and the like and memory transistors M11-M14 are connected in series in the row direction between the drain impurity region 6b and the source impurity region 20 to form a transistor row. The source impurities region 20 is separated from the source impurities region in another transistor row which is adjacent in the direction of the columns and is disposed in a line with other impurity regions 6a and 6b in the transistor row. A bit contact BC and a source contact SC are alternately disposed between the transistor rows which are adjacent in the column direction. A common source potential layer 22 which connects the source impurities regions 20 are disposed, for example in a planar form to shield a bit line BL 1 or the like of an upper layer in a direction vertical to the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called NAND
The present invention relates to a nonvolatile semiconductor memory device of the type. Specifically, according to the present invention, the pattern shape of the source impurity diffusion layer electrically connected in common between the transistor columns (NAND columns), which are the repetition units of the memory cell array, and the arrangement pattern of the bit contacts are changed. The present invention relates to a nonvolatile semiconductor memory device having a configuration suitable for area reduction.

[0002]

2. Description of the Related Art In recent years, non-volatile semiconductor memory devices (flash memories) of a batch erasing type have been used for storing file data. The flash memory for storing file data or the mask ROM is required to have a low unit cost. However, among various memory cell systems, the cell size is the smallest and the unit cost can be reduced. A NAND type is known as a cell system to be satisfied. A NAND type nonvolatile memory device is configured by connecting a plurality of memory transistors in series and
A memory block called an ND column is formed, and two NAs
By sharing one bit contact and source line in the ND column, it is possible to reduce the effective cell area per bit.

FIG. 12 is a circuit diagram showing a basic configuration of a memory cell array of a conventional NAND type nonvolatile memory device. FIG. 13 is a plan view of a basic structural unit portion of the memory cell array corresponding to FIG. 12, and FIG. 14 is a cross-sectional view taken along line AA 'of FIG. Here, a case where the memory transistor is an FG (Floating Gate) type is exemplified.

In FIGS. 12 and 13, reference numeral 100 denotes a memory cell array, M11 to M34 denote memory transistors, S11 to S32 (and S11a to S31a and S12b to S32b of the basic configuration adjacent in the column direction) denote selection transistors, and BL1 to BL32. BL3 is a bit line, WL1 to WL4
Is a word line, SL is a source line, SG1 and SG2 (and SG1a and SG2b of the basic configuration adjacent in the column direction) are select gate lines, and BC is a bit contact. A repeating unit called a string includes two selection transistors (selection gates) connected to a bit line or a source line, and n pieces (n is, for example, 8, 16, 3) between both selection transistors.
A number such as 2 and FIG. 12 illustrates n = 4 for simplification)
And a NAND string in which the memory transistors are connected in series. Select transistors S11-S31 and S11a-S31 connected to bit lines
a is controlled by the selection gate line SG1 or SG1a, and is connected to the selection transistors S12 to S12 connected to the source line.
32 and S12b to S32b are controlled by the selection gate line SG2 or SG2b. Further, the memory transistors M11 to M31, M12 to M32, M13 to M33,
M14 to M34 are word lines WL1, WL2,
It is controlled by WL3 and WL4.

[0005] In the plan view of FIG. 13, element isolation regions 5 are arranged in a parallel stripe shape elongated in the column direction, and the transistor columns are formed in the active regions in the separated spaces. In each transistor row, a word line and a selection gate line are arranged in a direction orthogonal to the element isolation region 5, and various impurity regions 6 a to 6 c are arranged in a space separated from each other.

In FIG. 14, reference numeral 2 denotes, for example, an n-type semiconductor substrate, 4 denotes, for example, a p-type well (p-well),
Denotes an interlayer insulating film, and 12a denotes a bit contact hole formed in the interlayer insulating film. The bit contact hole 12a forms the bit contact BC together with the connection plug 14 embedded therein. Each memory transistor M11
M14 to M14 are formed by stacking a tunnel insulating film 8, a floating gate FG, an inter-gate insulating film 10, and a control gate CG on the p-well 4. Control gates CG of the respective memory transistors constitute word lines WL11 to WL14, respectively.

Each of the select transistors (eg, SG11) has basically the same gate lamination structure as that of the memory transistor. In these select transistors, the layer that becomes the floating gate FG and the layer that becomes the control gate CG in the memory transistor have the same gate. It is short-circuited via a connection hole provided in the inter-insulating film 10. As a result, the gate electrode layers on the gate insulating film are all at the same potential as in the case of a normal single-layer gate, and thus each select gate line (SG11, etc.) is formed.

In the surface region of the p-well 4 located in the space region between the gate electrodes thus arranged, source / drain impurity regions 6a are formed between the memory transistors and between the memory transistor and the select transistor. . On the other hand, select transistors S11 and S11a
In the intervening p-well surface region, a common drain impurity region 6b is formed between the two strings in the bit direction. On the other hand, in the p-well surface region between the select transistors S12 and S12b, the source impurity region 6c common to other strings adjacent to the other side in the column direction is formed. As shown in FIG. 13, the source impurity region 6c is shared between the strings in the row direction, and is formed of, for example, an upper Al wiring layer or the like for every 32 strings via the source contact SC shown in FIG. Source line SL
It is connected to the.

In the NAND type memory cell array having such a configuration, the limit resolution F of photolithography is applied in both the row direction and the column direction, and the area of the cell array is minimized. That is, as shown in FIG. 13, the L / S (line width and space width) of the element isolation region 5 (for example, trench) in the row direction and the L / S of the polysilicon electrode layer (word line and select gate line) in the column direction. / S is the limit resolution F
It is formed with. Therefore, a cell area of 4F ² is realized, and the effective cell area and the two select transistor regions and the bit contact region (drain impurity and bit contact BC) and the source contact region (source impurity region and source contact SC) are combined. The cell area per bit is determined by the sum of the contact cell area converted per hit.

[0010]

However, such a conventional NAND type memory cell array configuration has the following problems.

First, the source impurity region 6c is formed by introducing impurities into the substrate and diffusing the same. There is a limit in reducing the resistance. For example, the source impurity region 6c is formed of a low-resistance source made of Al or the like for every 32 strings. Since it is connected to the line SL, the source resistance is large. For this reason, at the time of reading the cell data, the source potential increases due to the current flowing through the string, and it becomes impossible to read the cell threshold value correctly. This is because the source resistance value varies between the string in the middle of the source contact SC and the string near the source contact, and this becomes a noise component of the cell threshold value, which tends to cause a decrease in readout accuracy or erroneous readout. Particularly, in a multi-valued memory in which a plurality of bits of data are stored in one memory cell, writing and reading with a narrow threshold distribution are required. Usually, after writing, the threshold is verified and the correct threshold is driven. Therefore, not only is the possibility of erroneous reading high, but it is difficult to write to the correct threshold value only due to the decrease in reading accuracy.
On the other hand, if the width of the source impurity region 6c is widened in order to alleviate this problem, that is, to lower the resistance value of the source impurity region 6c even slightly, each string becomes longer in the column direction due to the increase in the source contact region described above. As a result, the cell area per bit increases.

Second, as shown in FIG. 13, the source impurity region 6c is bent at 90 degrees on the mask pattern at a place where the strings are connected to each other, and this place is processed according to the pattern by the lithography processing technique. Because
The corners are rounded in the actual finished pattern. If the gate electrode of the selection transistor overlaps this curved portion, it causes a variation in the effective gate width of the selection transistor.
Between the connection portion of the source impurity region 6c and the select gate line. Therefore, in the conventional pattern, the string becomes longer in the column direction.

Third, since the planar shape of the source impurity region 6c is not a simple line and space, an ultra-high resolution lithography technique for forming a pattern smaller than the limit resolution F using a phase shift method, modified illumination, or the like is used. It was difficult to apply.

Fourthly, the bit lines need to be formed at least somewhat wide in order to provide a margin for alignment in the bit contact BC portion. In the conventional pattern, however, the bit contact BC is formed in a row as shown in FIG. Since they are arranged in the same direction, there is a problem that it is difficult to perform Al processing in a wide portion of the bit line. For this reason, the limit resolution F is applied to the interval between the wide portions of the bit lines. As a result, the interval between the element isolation regions 5 cannot be formed at the limit resolution F, and the cell array area increases in the row direction. Was the result. As shown in FIG. 15, a bit contact B
There is an example in which C is alternately shifted up and down. However, in this case, the bit contact region becomes longer in the column direction (about twice), and in this case, the cell array area cannot be avoided.

The present invention has been made in view of such circumstances, and by devising the arrangement pattern of the source impurity region and the contact, the workability of the bit line is good and the area other than the effective cell portion in the NAND string is reduced. Accordingly, it is an object of the present invention to provide a nonvolatile semiconductor memory device which can achieve a reduction in cell array area and has high readout accuracy, and a method for manufacturing the same.

[0016]

Means for Solving the Problems The first of the prior arts described above.
In order to solve the third to third problems, the nonvolatile semiconductor memory device according to the present invention is arranged such that a selection transistor and a memory transistor are connected in series in a column direction between a drain impurity region and a source impurity region formed in a semiconductor layer. A nonvolatile semiconductor memory device in which a memory array is configured by arranging a plurality of connected transistor columns in a matrix, wherein the source impurity region is a source impurity region in another transistor column adjacent in a row direction. And arranged in a line with other impurity regions in the transistor row. In addition, the source impurity regions are commonly connected at least between the transistor columns in a row direction by an upper common source potential layer via source contacts. The common source potential layer is preferably formed of a word line for driving the memory transistor and a conductive layer above a selection signal line for driving the selection transistor, and is formed wider than at least the word line and the selection signal line. Have been.

In the nonvolatile semiconductor memory device having such a configuration, the source impurity region is formed in a line shape by being separated for each string. There is no need to take a margin, and it is easy to apply an ultra-high resolution lithography technique such as a phase shift method or modified illumination. In addition, since each source impurity region is connected to a common source potential layer (for example, a source line), the source resistance value is small and there is almost no variation in resistance value between strings.

In order to solve the fourth problem of the prior art described above, in the nonvolatile semiconductor memory device of the present invention, a drain impurity region formed in a semiconductor layer is connected to an upper bit wiring layer via a bit contact. A first select transistor connected to the first select transistor, a second select transistor having a source impurity region formed in the semiconductor layer connected to an upper common source potential layer via a source contact,
A non-volatile semiconductor memory device in which a memory array is formed by arranging a plurality of transistor columns each including a plurality of memory transistors connected in series in a column direction between second selection transistors in a matrix, Contacts and source contacts are alternately arranged at both ends of the transistor column between transistor columns adjacent in the row direction.

In this configuration, the source contacts and the bit contacts are alternately formed in the row direction, so that the distance between the bit wiring layers is greatly reduced. Along with this, it is necessary to devise the shape of the source wiring layer (common source potential layer) which has conventionally been constituted by the upper Al wiring. In the present invention, the common source potential layer has an opening or detour shape at least at the bit contact portion,
It is formed of a conductive layer above the word line for driving the memory transistor and the select signal line for driving the first and second select transistors and below the bit wiring layer. The common source potential layer may have a configuration in which, for example, a wide line in which a bit contact portion is opened or a meandering line that bypasses a bit contact is arranged in a row direction, for example, but is preferably opened in at least the bit contact portion. The source impurity regions are arranged in a planar shape (for example, a plate shape, a mesh shape, or the like) covering substantially the entire surface of the transistor column, and commonly connect the source impurity regions between the transistor columns adjacent in the row direction and the column direction. . In this configuration, the common source potential layer shields an upper bit line to which a relatively low voltage cell signal is transmitted at the time of reading from a lower word line or the like to which a relatively high voltage is applied.

Preferably, a bit line selecting means for selecting the bit lines into even columns and odd columns is connected to the bit lines. For example, in a write operation of a NAND flash memory, write and verification (read) may be repeated as described above. However, in a read operation, a read current usually flows through another cell in the NAND string. In order to improve the reading accuracy at this time, writing is performed sequentially from the cell on the source line side. In such a case, in the configuration in which the source side and the drain side are alternately switched, it is necessary to perform writing and reading separately in even columns and odd columns every other column. The provision of the bit line selection means enables control of every other column.

Preferably, the apparatus further comprises a shield potential line, and shield column selecting means connected to the bit line and connecting the unselected bit line to the shield potential line when the bit line is not selected. . The above common source potential layer shields the bit line in the vertical direction of the substrate,
Further, by providing the shield selecting means, the non-selected bit lines adjacent to both sides of the bit line at the time of reading are held at the shield voltage. The unselected bit lines more effectively shield the bit lines in the horizontal direction of the substrate.

According to a method of manufacturing a nonvolatile semiconductor memory device of the present invention, a semiconductor layer includes a first and a second selection transistor and a plurality of serially connected columns between the first and the second selection transistor in a column direction. A transistor row composed of memory transistors is divided into the first selection transistor and the second selection transistor.
Forming a first interlayer insulating film over the entire surface, and forming an opening on a source impurity region located at a transistor column end of the second transistor. Forming a source contact hole to be formed in the first interlayer insulating film, and opening the source contact hole at least above a drain impurity region located at an end of a transistor column of the first select transistor through the source contact hole; Forming, on the first interlayer insulating film, a common source potential layer interconnecting the source impurity regions between adjacent transistor columns in the row direction and the column direction; And forming a bit contact hole in the first and second interlayer insulating films that is opened on the first impurity region through an open portion of the common source potential layer. With that a step, and forming a bit line layer over the bit contact hole connecting to the drain impurity region on said second interlayer insulating film.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention is applied to a NAND type nonvolatile semiconductor memory device, and its storage element is a normal FG (F
loating Gate) type and MNOS (Metal-Nitride-Oxi
de Semiconductor), MONOS (Metal-Oxide-Nitride)
-Oxide Semiconductor), and also applicable to nanocrystal type and the like. Hereinafter, an embodiment of a nonvolatile semiconductor memory device and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings, taking a NAND nonvolatile memory device having an FG type memory element as an example.

First Embodiment FIG. 1 is a circuit diagram showing a circuit configuration of a memory cell array of a NAND type memory device according to this embodiment.

In FIG. 1, each bit line BL1 to BL3
A transistor row (string) is connected between the transistor line and the source line SL. The connection relationship between each bit line BL1 to BL3 of this string and the source line is the same as the conventional one (FIG.
Since it is the same as 2), the description here is omitted.

In the memory cell array 1 according to the present embodiment, the arrangement direction of the strings in the column direction is alternately switched between the even columns and the odd columns. That is,
In FIG. 1, the strings in the first column connected to the bit line BL1 and the strings in the third column connected to the bit line BL3 have the select transistors S11 and S31 of the bit lines in the same direction (upward in the figure). Although arranged, the strings in the second column are opposite to the bit line selection transistors S21.
The side is arranged downward in the figure. Therefore, the bit contacts BC1 in the first column and the source contacts S in the second column
C2 and bit contacts BC3 in the third column are arranged side by side in the row direction. Further, the first column of source contacts SC1, the second column of bit contacts BC2, and the third
The column source contacts SC3 are arranged in the row direction.

Select transistors S11, S22 and S3
1 is controlled by the select gate line SG1, and the select transistors S12, S21, and S32 are all controlled by the select gate line SG2. The memory transistors M11, M24 and M31 are controlled by the word line WL1. Similarly, memory transistors M12,
M23 and M32 are controlled by word line WL2, memory transistors M13, M22 and M33 are controlled by word line WL3, and memory transistors M14, M21 and M34 are controlled by word line WL4.

In the memory cell array 1 of this embodiment, the bit line selection means 3 is connected to the bit lines BL1 to BL3. The bit line selection means 3 is a means for selecting the bit lines of the odd column and the even column for separate control. This is because, as described above, in the case where verification (read operation after writing) is involved in the write operation of the NAND flash memory, in order to improve the read accuracy and, consequently, the write accuracy, the cells on the source line side need to be improved. This is because writing must be performed in order. If it is not necessary, the bit line selecting means 3 may be omitted.
Specifically, the bit line selection means 3 in the present embodiment
It comprises third selection transistors S13, S23 and S33 connected in series for each bit line, and bit selection lines BS1 and BS2 for controlling the same in an even column and an odd column.

Further, although not particularly shown, shield selecting means having substantially the same configuration can be provided. The shield selection means includes, for example, a selection transistor and a selection line (in this case, referred to as a shield selection line) having substantially the same configuration as the bit line selection means 3, and further connects / disconnects to / from the bit line via each selection transistor. Are controlled to be switched, and a shield line maintained at a predetermined shield voltage can be adopted. In the shield selecting means, bit lines are selected every other column by the bit line selecting means 3, and non-selected bit lines arranged on both sides of each selected bit line are held at a shield voltage. This is, for example, when reading
For selected bit lines to which low-amplitude cell signals are transmitted,
This is because shielding is performed on both sides in the plane direction parallel to the substrate so as to be less susceptible to noise and to prevent malfunction. The unselected bit line at the time of reading is, for example, a ground potential or the like,
In such a case where noise countermeasures are sufficient, the shield selecting means may be omitted.

FIG. 2 is a plan view showing an example of the arrangement of the memory cell array portion having the circuit configuration of FIG. FIG. 3 is FIG.
FIG. 4 is a sectional structural view in the column direction along the line BB ′ of FIG.
FIG. 4 is a cross-sectional structural view in the row direction along the line CC ′ of FIG. FIG.
As shown in the cross-sectional view of FIG. 3, for example, a p-type well (p-well 4) is formed on the surface side in the n-type semiconductor substrate 2, and a transistor row is arranged on the surface side of the p-well. ing. The p-well can be formed in a p-type semiconductor substrate. In that case, an n-type well (n-well) is interposed between the p-well and the substrate region. The element isolation region 5 may be LOCOS or the like.
As shown in the figure, an insulator is buried in the etching groove (trench T).

In the memory transistors M11 to M14, as shown in FIG. 3, a tunnel insulating film 8, a floating gate FG, an inter-gate insulating film 1
0, control electrodes (word lines WL1 to WL4) are stacked. The floating gate FG is made of a first-layer polysilicon film, and the word lines WL1 to WL4 are made of a second-layer polysilicon film. The word line is formed by further stacking a high-melting metal silicide layer on the polysilicon film. Other configurations are also possible. Select transistors S11, S11a, S12, S1
2b is a gate laminated structure similar to a memory transistor, similar to the conventional one, and is a normal MOSF having a short-circuit between gates.
It has an ET structure. Select transistors S11, S1
The gate electrode layers 1a, S12, and S12b form select gate lines SG1, SG1a, SG2, and SG2b, respectively.

On the surface side in the p-well 4 between the gates of the memory transistor, n-type impurities are introduced at a high concentration to form source / drain impurity regions 6a, as in the prior art. On one side, a drain impurity region 6b common to another adjacent string is formed.

In this embodiment, on the other side in the bit direction,
Although a common source impurity region is provided between adjacent strings as in the related art, the source impurity region 20 of the present example has a string shape in the row direction as shown in FIG. As shown in FIG. 5, a pattern is extracted and is arranged in a line with other impurity regions 6a and 6b of the transistor row. In addition, as shown in FIG.
SC3 (contact hole 12a formed in the first interlayer insulating film in the cross section of FIG. 3) is provided. Then, the common source potential layer 22 (the source line S on the circuit) connected to the source impurity region 20 through the contact hole 12a.
L) is formed on the first interlayer insulating film 12. 2 to 4, the common source potential layer 22 has a plate shape that covers substantially the entire surface of the transistor row, and has an opening 22a above the drain impurity region 6b for passing a bit contact described later. Having. FIG. 6 shows an extracted pattern of the common source potential layer 22. In addition, as another mode of the common source potential layer 22,
A wide row-direction wiring layer having an opening 22a, or a row-direction wiring layer, for example, meandering so as to bypass a bit contact portion, may be provided entirely between the transistor columns in the column direction. Further, the shape may be a mesh shape instead of the plate shape.

As shown in FIGS. 3 and 4, a second interlayer insulating film 13 is formed on the entire surface of the common source potential layer 22. A contact hole 12a that is opened on impurity region 6b is formed. In the contact hole 12a, for example, Ti / T
A metal plug 14 such as W is embedded with an adhesion layer such as iN interposed therebetween. The metal plug 14 is
a together with the bit contact BC1. The bit line BL1 is wired on the second interlayer insulating layer 13 so as to be connected to the transistor column by the bit contact BC1. The bit line BL1 may have a three-layer structure in which, for example, a single-layer film of Al or the like or a main wiring layer of Al or the like is sandwiched between an antireflection layer (or a protective layer) and a barrier metal.

In the NAND-type nonvolatile memory device having such a configuration, as is apparent from FIG. 4, bit contacts are provided every other column in the row direction, so that a thick Al
And other difficulties in processing the wiring layer. That is, in the example of FIG. 4, the bit lines BL1 and BL3 on both sides are
Has bit contacts BC1 and BC3 at this portion, but no bit contact is provided at this portion on the central bit line BL2. Assuming that the limit resolution of the photolithography is F and the margin of alignment between the bit contact and the bit line is P, the bit lines B on both sides are
The minimum line width of L1 and BL3 is (F + 2P) which is the same as the conventional one, but the minimum line width of the central bit line BL is changed to the conventional (F + 2P).
2P) to F. Therefore, the workability of the bit line is improved by that much, and if the workability is the same, the width of the element isolation region 5 can be narrowed by that much, and the effective cell area can be reduced.

As is apparent from FIG. 5, the source impurity region 20 has a simple line shape together with the other impurity regions 6a and 6b, and does not have a portion bent at a right angle unlike the conventional case. The corners are rounded due to receding or the like, and it is not necessary to estimate in advance the margin for matching with the gate electrode of the selection transistor. The source impurity region 20 can be shortened in the column direction. Since the source impurity regions 20 and the like are formed by self-alignment, the pattern shape is determined in the row direction when the element isolation region 5 is formed. That is, the pattern of the element isolation region 5 has a simple line-and-space shape, and it is easy to apply, for example, a phase shift method or a modified illumination technique during this formation. In general, these ultra-high resolution lithography techniques can be easily applied to a simple repetition pattern such as an island pattern or a parallel stripe pattern. Therefore, in the present embodiment, the narrow parallel stripe-shaped element isolation region 5 having a smaller than the limit resolution F and the narrow parallel stripe-shaped active region having a smaller than the limit resolution F (the impurity diffusion region and the channel formation region).
Is obtained, and the size can be reduced twice in the row direction.

Further, source contacts SC1 to SC3 are provided for each source impurity region 20. At these portions, the paths through which the current flows in the impurity diffusion regions are small and are uniform for each string, so that the source resistance value is low. Almost no variation between strings. For this reason, the accuracy at the time of reading is improved, and when performing verification for each bit, the writing accuracy is also improved.

Further, as shown in FIGS. 2 to 4, in the present embodiment, the common source potential layer 22 is provided using an intermediate wiring layer between a word line and a bit line, and It has a plate shape that almost covers the rows.
Therefore, an upper bit line, to which a cell signal having a relatively low amplitude is transmitted at the time of reading, is connected to a lower word line or the like to which a relatively high voltage is applied by the common source potential layer 22 (usually the ground potential). Can be shielded in the vertical direction of the substrate. This shielding effect can also be obtained when the common source potential layer 22 is formed in a mesh shape.
Further, as described above, by providing the shield selecting means, it is possible to achieve the shield between the bit lines in the horizontal direction of the substrate by the non-selected bit lines.

Next, the manufacturing method of this embodiment will be described. 7 to 9 are cross-sectional views illustrating the steps of manufacturing the nonvolatile memory device having the above-described configuration. 7 is a sectional view taken along line EE ′ of FIG. 2, and FIGS. 8 and 9 are sectional views of FIG.
It is sectional drawing which followed the -B 'line.

In FIG. 7, a semiconductor substrate 2 such as an n-type silicon wafer is prepared, and a predetermined p
A mold well 4 is formed, and an element isolation region 5 is formed. First, in FIG. 7A, a tunnel insulating film 8 is formed on the p-well 4 by, for example, about 8 nm to 10 nm by a thermal oxidation method, and then a Doped-Poly Si film serving as a floating gate FG is formed.
CV is applied to the laminated film of SiO ₂ film to be used as an etching mask.
A film is formed by a D (Chemical Vapor Deposition) method or the like. A resist pattern RP is formed on the laminated film after film formation, and the laminated film is etched in a column line using the resist pattern RP as a mask. As a result, a stacked film of the layer 9 serving as the floating gate FG and the etching mask 24 is formed so as to be separated in the width direction of the string.

In FIG. 7B, a trench is formed. First, a layer 9 serving as a column line floating gate FG
Is removed to expose the surface of the p-well 4 and the p-well 4 is etched to a predetermined depth to form a trench T. In FIG. 7C, after the inner wall of the trench T is thinly thermally oxidized, a SiO ₂ -based insulator is deposited in the trench T by, for example, an LP (Low pressure) -CVD method. The SiO ₂ -based insulator is dug down by an etch-back method or the like. The amount of etchback of this SiO ₂ based insulator is
The overlapping area between the floating gate FG and a control gate (word line) formed later is determined. The overlapping area of the two gates determines the capacitance ratio between the control gate and the floating gate FG or the silicon layers 2 and 4. Therefore, the amount by which the SiO ₂ -based insulator is etched back is an important parameter that determines the charge injection amount and the charge extraction amount of the floating gate FG. It is desirable that this digging be performed up to, for example, about 0.3 μm from the surface of the floating gate FG. Thereby, the element isolation region 5 is formed.

In FIG. 8, for example, an ONO (Oxide-Nitride-Oxide) film is formed on the entire surface as an inter-gate insulating film, and for example, Doped-Poly Si or polycide (Polycide).
A layer serving as a control electrode (word line) is deposited on the entire surface. On the layer to be a word line, a photoresist pattern (not shown) is formed in a linear shape long in a direction orthogonal to the layer 9 to be a floating gate FG. Dry etching is performed using this resist pattern as a mask to process and form word lines. During this dry etching, the underlying ONO film and the layer 9 serving as the floating gate FG are also cut at the same time. As a result, the floating gate F 9 is separated for each memory transistor.
G is formed, and the stack gate shown in FIG. 8 is completed.
Next, source / drain impurity regions 6a, drain impurity regions 6b, and source impurity regions 20 are formed in the arrangement pattern shown in FIG. .

In the step shown in FIG. 9, a first interlayer insulating film 12 of, for example, silicon oxide is formed on the entire surface, and is planarized as necessary. Thereafter, for the first interlayer insulating film 12, contact holes 12b (source contacts SC1 to SC3) opened on the source impurity region 20 are formed for each source impurity region 20 by a normal photolithography processing technique. . A conductive layer (for example, Doped-Poly) serving as a common source potential layer 22 is formed on the first interlayer insulating film 12.
An Si layer is formed on the entire surface so as to completely bury the inside of the contact hole 12b, and this is etched using a resist pattern (not shown) as a mask. This allows
At least a common source potential layer 22 having an opening 22a having a position and a size that does not hinder the formation of the bit contact, including variations, is formed.

Thereafter, as shown in FIG. 3, a second interlayer insulating film 13 is deposited and, if necessary, planarized.
And the underlying first interlayer insulating film 12,
The non-volatile memory is completed by opening the bit contact hole 12a, embedding the connection plug 14 in a conventional manner, and wiring the bit line BL1.

Next, in the NAND type nonvolatile memory device having such a configuration, the bit line selection control operation by the bit line selecting means in FIG. 1 will be briefly described in reading from the NAND type nonvolatile memory device. The present invention can be applied to a case where this memory transistor stores multi-valued information in addition to binary information. Here, a case where binary information is read is exemplified. In the case of multi-valued information, the word line voltage or the like at the time of programming or reading is stepwise changed.
For example, since the shift is performed in the forward direction, the basic operation is the same.

First, when reading data in a string in an odd-numbered column, the selection transistor S1 for selecting a bit line is used.
3 or a voltage for conducting S33 is applied to the bit selection line BS1. At this time, the selection transistors S2 in the other even columns
3 and S43 remain off, whereby the bit lines in the odd-numbered columns are selectively read out by a read-related circuit (for example,
Data latch circuit). In a read operation,
A word line (selected word line) to which a cell to be read (selected cell) is connected and a well are connected to a predetermined read potential (for example, 2
(A threshold distribution intermediate value of the value information), and a voltage at which all the selected transistors and all the memory transistors connected to the word lines other than the selected word line (non-selected word lines) conduct. Apply to all selected signal lines and unselected word lines. This voltage is large enough that writing and erasing are not performed on the memory transistor only by the potential difference from the well. In this state, if, for example, a positive voltage is applied only to the odd-numbered bit lines (selected bit lines) to which the selected cell is connected, all the memory transistors other than the cell from which information is to be read are in a conductive state. According to the threshold value of the transistor, whether or not a current flows in the selected bit line in the odd-numbered column is determined. The presence or absence of this current is detected by the selected readout circuit, and the logical state “1” or “0” of the stored data is determined.

In the reading of the even-numbered column, the control of the bit control line is performed in the same manner as in the case of exciting BS2. At this time, when the shield selecting means is provided, it is preferable to perform the shield between bit lines by connecting only the unselected bit lines to a shield voltage line (not shown).

Second Embodiment This embodiment is different from the first embodiment in that the direction of the strings is reversed and the bit contacts and the source contacts are not alternately arranged. 1 shows an embodiment for implementing the present invention. FIG. 10 is a plan view of the memory cell array, and FIG. 11 is a cross-sectional configuration diagram along the line DD ′ in FIG. In the present embodiment, the same components as those in the first embodiment and the manufacturing method thereof are denoted by the same reference numerals, and description thereof is omitted.

The conventional circuit diagram shown in FIG. 12 is applied to the memory cell array 30 of the present embodiment except for the connection portion of the source line (common source potential layer in this example). Therefore,
As shown in FIG. 10, on one side of a string, bit contacts BC between adjacent strings in the row direction are arranged in the row direction. On the other hand, on the other side of the string, as shown in FIG.
Source impurity region 20 having the same arrangement pattern as the embodiment
And source contact SC for each source impurity region 20
1 to SC3 are provided.

The common source potential layer 32 in the present embodiment
Is formed of a conductive layer (for example, a polysilicon layer) in a middle layer between a word line and a bit line as in the first embodiment, so that it can be formed wide without reducing the string size in the column direction. It is not always necessary to extend to the bit contact BC portion. This is because the alternate arrangement of the bit contacts and the source contacts is not adopted. If the wiring width of the common source potential layer 32 overlaps the source contact SC including the variation, the source resistance value can be sufficiently reduced and the variation suppressing effect can be obtained as compared with the related art. In the examples shown in FIGS. 10 and 11, the common source potential layer 32 is wired in the row direction so as to have a width enough to cover above the select transistors on both sides. However, in the case where it is desired that the common source potential layer 32 also has the same shielding effect in the vertical direction of the substrate as in the first embodiment, the common source potential layer 32 may be formed in a plate shape or a mesh shape up to the vicinity of the bit contact BC or over the entire surface. .

In the nonvolatile memory device according to the present embodiment, while the writing / reading operation can be performed in word line units, the effect of improving the accuracy is obtained by reducing the source resistance value and its variation. Further, as in the first embodiment, the source impurity region is arranged in a line with other impurity regions in a line shape and has a simple line arrangement shape, so that it is possible to save space in the memory cell array in both the row direction and the column direction.

The present embodiment can be suitably applied not only to an EEPROM such as a flash memory but also to a NAND type mask ROM. In the NAND string of the mask ROM, the selection transistor on the source side is usually omitted, and when the direction of the string is reversed every other row as in the first embodiment, the selection transistor is always turned on every other row. Requires the process of
Since only the occupied area of the select transistor is required, according to the present invention, when there is a size reduction effect exceeding the area increase by the select transistor, for example,
The application of the first embodiment is also possible.

[0053]

According to the nonvolatile semiconductor memory device and the method of manufacturing the same according to the present invention, all the impurity regions of the source and the drain in the transistor column constituting the NAND type memory cell array can be formed as simple lines. The space in the direction (line of the element isolation region) can be made into a simple line shape, so that there is no need for margin for matching with the selection transistor, which was required in the past, and the application of ultra-high resolution lithography technology is facilitated. And the area of the memory cell array in both the column direction can be reduced. Further, since the source impurity regions separated for each transistor column are connected by using, for example, a wiring layer (common source potential layer) intermediate between a bit line and a word line, the source resistance value and its variation are small, and the reading accuracy is small. improves. By arranging the common source potential layer so as to cover, for example, the upper part of the transistor row, a shielding effect in the direction perpendicular to the substrate is obtained, and the reading accuracy is further improved.

In the configuration in which the source contacts and the bit contacts are alternately arranged, the bit line can be easily processed,
In addition, the restriction that the width of the element isolation region cannot be reduced in order to ensure the workability of the bit line as in the related art is reduced.
In addition, the bit line selection means makes it possible to operate every other column. In this operation, non-selected bit lines having no potential change are always arranged on both sides of the selected bit line through which the read cell current flows, so that the shield in the horizontal direction of the substrate is used. Effective and suitable for high-precision reading. By means of shield selection,
If a shield potential is applied to this non-selected bit line, the reading accuracy is further improved.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a memory cell array and a peripheral portion thereof in a NAND nonvolatile memory device according to a first embodiment of the present invention.

FIG. 2 is a plan view of the memory cell array of FIG. 1;

FIG. 3 is a cross-sectional structural view in a column direction along line BB ′ of FIG. 2;

FIG. 4 is a cross-sectional structural view in the row direction along line CC ′ of FIG. 2;

FIG. 5 is a layout pattern diagram of impurity regions forming a source and a drain of a transistor row, extracted from the plan view of FIG. 2;

FIG. 6 is a pattern diagram of a common source potential layer extracted from the plan view of FIG. 2;

FIGS. 7A and 7B are cross-sectional views illustrating the steps of manufacturing the NAND-type nonvolatile memory device according to the first embodiment of the present invention, and show steps up to the formation of an element isolation region.

FIG. 8 is a sectional view following FIG. 7, showing up to the formation of a transistor row;

FIG. 9 is a sectional view following FIG. 8, showing the steps up to the formation of a common source potential layer;

FIG. 10 is a plan view of a memory cell array of a NAND nonvolatile memory device according to a second embodiment of the present invention.

FIG. 11 is a sectional structural view taken along line DD ′ of FIG. 10;

FIG. 12 is a circuit diagram showing a configuration of a memory cell array of a conventional NAND type nonvolatile memory device.

FIG. 13 is a plan view of the memory cell array of FIG.

14 is a cross-sectional structural view in the column direction along the line AA ′ in FIG.

FIG. 15 is a partial plan view of a memory cell array showing an example of arrangement of bit contacts for improving workability of a bit line in the related art.

[Explanation of symbols]

1, 30 memory cell array, 2 semiconductor substrate, 3 bit line selecting means, 4 p well, 5 element isolation region, 6
a: source / drain impurity region, 6b: drain impurity region, 8: tunnel insulating film, 9: layer to be a floating gate, 10: inter-gate insulating film, 12: first interlayer insulating film, 12a: bit contact hole, 12b: source contact hole, 13: second interlayer insulating film, 14: metal plug, 20: source impurity region, 22, 32: common source potential layer, 22a: opening, 24: etching mask layer, FG: floating gate , BC1, etc. bit contact, SC1 etc. source contact, M11 etc. memory transistor, S11, S12 etc. selection transistor, S13 etc. bit selection transistor, BL1 etc. bit line, WL1 etc. word line, SL ... source line , SG1
1, SG12: select gate line, BS1, etc .: bit select line, RP: resist pattern.

Claims (13)

[Claims] 1. A memory array comprising a plurality of transistor columns each having a selection transistor and a memory transistor connected in series in a column direction between a drain impurity region and a source impurity region formed in a semiconductor layer. Wherein the source impurity region is separated from a source impurity region in another transistor column adjacent in a row direction so as to form a line with the other impurity region in the transistor column. Nonvolatile semiconductor memory device arranged in the semiconductor device. 2. The semiconductor device according to claim 1, wherein said source impurity regions are respectively formed by a common source potential layer on an upper layer through source contacts.
The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is commonly connected at least between the transistor columns in a row direction. 3. The drain impurity region is connected via a bit contact to a bit wiring layer further above the common source potential layer, wherein the common source potential layer includes a word line for driving the memory transistor and the word line. A transistor which is formed from a conductive layer above the selection signal line for driving the selection transistor and below the bit wiring layer, has an opening or detour shape at least at the bit contact portion, and is adjacent in the row direction and the column direction. 3. The nonvolatile semiconductor memory device according to claim 2, wherein said source impurity region is commonly connected between columns. 4. The nonvolatile semiconductor memory device according to claim 3, wherein said common source line is opened at said bit contact portion and is arranged in a plane shape covering substantially the entire surface of said transistor row. 5. A first select transistor having a drain impurity region formed in a semiconductor layer connected to an upper bit wiring layer via a bit contact, and a source impurity region formed in the semiconductor layer having a source impurity region. A transistor column including a second selection transistor connected to an upper common source potential layer via a contact and a plurality of memory transistors serially connected in a column direction between the first and second selection transistors is arranged in a matrix. A nonvolatile semiconductor memory device in which a memory array is configured by arranging a plurality of bit contacts and source contacts, wherein the bit contacts and the source contacts are alternately arranged at both ends of the transistor columns between adjacent transistor columns in a row direction. Nonvolatile semiconductor memory device. 6. The source impurity region is separated from a source impurity region in another transistor column adjacent in a row direction and arranged in a line with another impurity region in the transistor column. 6. The non-volatile semiconductor memory device according to claim 5, wherein said source contact is provided. 7. The common source potential layer has an opening or detour at least at the bit contact portion,
7. The non-volatile memory according to claim 6, wherein said non-volatile memory is constituted by a conductive layer which is higher than a word line for driving said memory transistor and a selection signal line for driving said first and second selection transistors and lower than said bit wiring layer. Semiconductor storage device. 8. The non-volatile semiconductor memory device according to claim 7, wherein said common source potential layer is opened at least in said bit contact portion, and is arranged in a plane shape covering substantially the entire surface of said transistor row. 9. The non-volatile semiconductor memory device according to claim 5, wherein a bit line selecting means for selecting the bit lines into even columns and odd columns is connected to said bit lines. 10. The bit line selection means includes a plurality of bit line selection transistors connected in series to each bit line, wherein the plurality of bit line selection transistors are an even column bit line selection transistor and an odd column bit line. 10. The nonvolatile semiconductor memory device according to claim 9, wherein control electrodes are commonly connected to bit selection lines different from the line selection transistors. 11. A semiconductor device according to claim 9, further comprising: a shield potential line; and a shield column selecting means connected to said bit line and connecting said unselected bit line to said shield potential line when said bit line is not selected. 3. The nonvolatile semiconductor memory device according to 1. 12. The shield column selection means includes a plurality of shield selection transistors connected in series to each bit line, wherein the plurality of shield selection transistors include an even column shield selection transistor and an odd column shield selection transistor. 12. The nonvolatile semiconductor memory device according to claim 11, wherein the control electrodes are commonly connected by different shield selection lines. 13. A transistor array comprising a first and a second select transistor and a plurality of memory transistors connected in series in a column direction between the first and the second select transistor in the semiconductor layer. Forming a first select transistor and a second select transistor so as to be alternately adjacent to each other in a row direction; forming a first interlayer insulating film on the entire surface; and positioning the first interlayer insulating film at a transistor column end of the second transistor. Forming a source contact hole opened in the source impurity region in the first interlayer insulating film; and forming at least the first contact hole through the source contact hole.
A common source potential layer, which is opened above the drain impurity region located at the transistor column end of the select transistor and interconnects the source impurity regions between adjacent transistor columns in the row and column directions, Forming a second interlayer insulating film on the entire surface, and forming a bit contact hole opened on the first impurity region through an opening portion of the common source potential layer. Forming the first and second interlayer insulating films; and forming a bit wiring layer connected to the drain impurity region through the bit contact holes on the second interlayer insulating film. A method for manufacturing a nonvolatile semiconductor memory device.