JPH02177456A - Gate array basic cell - Google Patents

Abstract

PURPOSE:To constitute a high speed RAM cell by a small number of basic cells without producing an idle transistor and constitute a high speed random logic without degradation of packaging density by a method wherein a plurality of pairs of first P-MOS's and first N-MOS's and a pair of a second P-MOS and a second N-MOS are provided and by another method. CONSTITUTION:A plurality of pairs of first P-type channel MOS transistors (P-MOS's) 51 and 52 and first N-type channel MOS transistors (N-MOS's) 61 and 62 which have large channel widths and a pair of a second P-MOS 53 and a second N-MOS 63 having independent diffused regions 58 and 68 and small channel widths are provided. For instance, the second P-MOS 53 and the second N-MOS 63 are arranged sideways with the first P-MOS's 51 and 52 and the first N-MOS's 61 and 62 between an electric source potential line VCC and a ground potential line VSS which are arranged approximately in parallel with each other. Further, diffused regions 59 and 69 for P-type well and N-type well electric sources are formed nearly on the same line with the outside diffused regions of the second P-MOS 53 and the second N-MOS 63.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a basic cell of a gate array for constructing a unique random gate circuit by freely combining logic gates.

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 60-4
Publication No. 7441 (hereinafter referred to as Document 1), and JP-A-6
There was one described in Publication No. 0-65546 (hereinafter referred to as Document 2).

FIG. 2 is a schematic pattern diagram of the conventional gate array described in Document 1.

In this gate array, a pad 2 region and a bulk pattern region for input/output cells 3 are formed on the periphery of a master chip 1, and basic cells are arranged in the lateral direction (
Basic cell rows 4-1.4-2.
..., 4-n are arranged in the vertical direction (Y direction) at predetermined intervals (wiring area).

3 is a pattern diagram of the basic cell in FIG. 2, and FIG. 4 is an equivalent circuit diagram of FIG. 3.

This basic cell consists of two pairs of transistors (2-p
This is called an air of transistors configuration, and consists of two pairs of P-channel MOS transistors (
11-1, 11-2 (hereinafter referred to as PMO3) and an N-channel MOS transistor (hereinafter referred to as NMOS)
2-1.12-2, each PIVIO8II-1
, 11-2 and NMOS 12-1゜12-2 form a gate electrode 13-1 made of polysilicon (polycrystalline silicon).
．． 13-2 and are commonly connected to each other. PIVIO
The dimensions of 8II-1 and 11-2 (expressed as W/L, where the channel length and width are W, and are used as an index of the gain of the transistor) are equal, and NM
The dimensions of OS 12-1 and OS 12-2 are also the same. P
The P-type impurity diffusion region 14 constituting the source region or drain region of the MOs 811-1 and 11-2 is shared by both the PMOs 3II-1 and 11-2. Similarly, the N-type impurity diffusion region 15 constituting the source region or drain region of the NMOSs 12-1 and 12-2 is shared by both the NMOSs 812-1 and 12-2.

Note that an N-type substrate contact pattern 16 and a P-type substrate contact pattern 17 are formed outside the diffusion regions 14 and 15, respectively.

This type of basic cell is wired according to the following procedure to realize a user-specific large-scale integrated circuit (LSI), for example.

That is, basic circuits (hereinafter referred to as IJ block) such as NAND gates and flip-flop circuits (hereinafter referred to as FF circuits) are constructed using basic cells on the required side. Next, according to the user's design, the placement of each functional block on the chip and the wiring between each functional block are calculated and determined by an automatic placement and routing system that uses computer-based logic simulation techniques and the like.

However, the basic cell having such a configuration has the following drawbacks.

(a) Two PMO8II-1, 11-2 and two N
Because IVIO812-1 and 12-2 each share the diffusion area, PMOs connected in parallel
It is difficult to construct a single transfer gate consisting of 8 and NMOS, that is, one transfer gate.

Therefore, when configuring RAM (Random Access Memory), a large number of basic cells (third
In the example shown, 4 basic cells are required for 1 bit)
Otherwise, unconnected and useless so-called idle transistors occur in the basic cells used. Therefore, RAM1'
The degree of integration of the 9th generation, etc. is extremely low.

(b) Generally, in order to obtain high-speed random logic, the dimension of a transistor is increased, but a transistor that drives a small load capacitance inside a functional block may have a small dimension. However, in the basic cell shown in Fig. 3, PMO8II
Since the dimensions of -1 and 11-2 and the NMOSs 12-1 and 12-2 are uniform, some transistors in the circuit have excessive dimensions. Therefore, when trying to increase speed, it is not possible to obtain a sufficient degree of integration even in random logic.

In order to eliminate such drawbacks, the technology of Document 1 uses large-dimensional transistors (hereinafter referred to as A basic cell is composed of a transistor with a small dimension (hereinafter referred to as a small transistor) and a transistor with a small dimension (hereinafter referred to as a small transistor).

That is, this basic cell includes a first PMO8 region 21A, a second PMO3 region 21B outside it, and a first NMO3 region 21A.
S region 22A and second NMOS region 22A outside it
It has The first PMO3 region 2LA has two large transistors (7) PMO321-LL, 2l.
-2L, the second PMO8 region 21B has two PMOS21-33, 21-43 consisting of small transistors, and the first
The second NMO8 region 22A has two NMO82s 22-LL and 22-2L made of large transistors, and the second NMO8 region 22B has two NMO82s made of small transistors.
2-38 and 22-48 are formed, respectively. PM
O821-LL and 2l-2L are each composed of independent P-type impurity diffusion regions 23-1 and 23-2, gate electrodes 24-1 and 24-2 made of polysilicon, and N-type substrate contact region 25. ing. PMO821-
38, 21-48 is a shared P-type impurity diffusion region 23-
3, a gate electrode 24-3, 24-4, and an N-type substrate contact region 25, respectively. N.M.O.
322-IL, 22-2L are independent N-type impurity diffusion regions 26-1, 26-2, and gate electrodes 27-1, 27-
2, and a P-type substrate contact region 28, and furthermore, the NMOs 822-33 and 22-48 have a common N-type impurity diffusion region 26-3, a gate electrode 27-3.
27-4, and a P-type substrate contact region 28, respectively.

When constructing a random logic, for example, a two-man NAND gate, using the above-mentioned basic cells, as shown in FIG.
-LL, 2l-2L and NMO822-LL, 22-2
Use L. Contact region 25 and pH/l0321-
The diffusion regions 23-1 and 23-2 of LL and 2l-2L are connected to the power supply potential Vcc line, and the contact region 28 and the NMOS 2
The diffusion region 26-2 of 2-2L is connected to the ground potential Vss line,
The gate electrode 23-1.27-1 is connected to the input signal ■N1, the gate electrode 24-2.27-2 is connected to the input signal IN2, and the diffusion region 23-1.23-2.26-1 is connected to the output signal OUT. Connected. Small transistor second PMO8
The region 21B and the NMO3 region 22B are used as wiring regions. Note that NA indicated by a white circle is a contact portion between the first layer Aρ wiring and the semiconductor substrate.

Further, a RAM cell using the basic cell shown in FIG. 5 is configured as shown in FIGS. 7 and 8, for example.

FIG. 7 is a pattern diagram of a RAM cell. In FIG. 7, LA shown by a solid line is the Ap wiring of the first layer, LB shown by a broken line is the Aj wiring of the second layer, and NA shown by a white circle is the contact between the A1 wiring LA of the first layer and the semiconductor substrate. The portion NB indicated by a double circle is the AfI wiring LA in the first layer and A, l! in the second layer. Contact part with wiring LB, Di is input data signal, Qi is inverted input data signal, Qo is inverted output data signal, WRD is read word line, WW is write word line, 2l-ILl, 2l-2L1.2l-3SL ,2
1-481 is the first basic cell layered in another basic cell column. Second PMO8 area 2LA-1, 21B-1
This is PMO8.

FIG. 8 is an equivalent circuit diagram of FIG. 7, and shows the inverter 23.
24 is PMO321-331, 2l-4S1 and NMO
822-38, 22-48.

This RAM cell is constructed using half of the adjacent basic cells. and each N which is a large transistor
MO322-IL, 22-21 and PMO821-IL
Since I, 2l-2LL do not share a diffusion region with each other, it is easy to configure a single transfer gate or a tallied inverter. Furthermore, small transistors Nrvros22-3g, 22-48 and PMO3
By configuring inverters 23 and 24 for data retention using 21-381 and 21-431, no idle transistors are created, and a static RAM cell for 1 bit is realized with the area of 1 basic cell. can. Therefore, the degree of integration when configuring the RAM is greatly improved.

(Problems to be Solved by the Invention) However, when using the basic cell with the above configuration to configure random logic or RAM, a technically satisfactory result could not be obtained due to the following reasons.

(i> In conventional basic cells, it is difficult to use small transistors in random logic, and the degree of integration in random logic configurations has not yet been resolved.

For example, if you try to configure a random logic functional block with a mixture of large and small transistors using the basic cell shown in FIG.
38,21-48 and NMO822-38,22-48
The gate and drain of the large transistor PMO821
-IL, 212L and NMO322-IL, 22-2L
It must be connected across the large transistor, and crosses the power supply potential Vcc line and the ground potential Vss line that run on the large transistor. Therefore, when wiring the functional blocks,
In addition to first-layer metal wiring, second-layer metal wiring must also be used extensively, and automatic placement and routing systems can perform global wiring (
wiring between each functional block). It is also possible to configure such a functional block by using small transistors from one of the adjacent basic cells, but even in such a case, the basic cells that use small transistors , the burden on the automatic placement and routing system increases, such as only being able to place functional blocks using only large transistors. Furthermore, in either case, the power supply potential Vcc line running on the large transistor and the ground potential Vs
A lead line is required to supply power from the s-line to the small transistor, making wiring even more difficult.

(ii) In conventional basic cells, the transfer gate is composed of mostly large transistors, so
There is also the problem that high-speed RAM is difficult to obtain.

For example, in the RAM shown in Figure 8, a large transistor is assigned to the transfer gate NMO822-L connected to the read bit line, but in such a circuit, the dimensions of the transfer gate NMO822-L are increased. At the same time, the inverted output data signal T50
The capacitance of the bit line and word line WRD also increases, making it impossible to increase the speed. More preferably, the transfer gate NMO 322-IL should be a small transistor, and this small transistor should be driven by a large transistor, but such a configuration is difficult with the basic cell shown in FIG.

(iii) Regarding the problem in (i) that it is difficult to use small transistors in random logic, the following solution is provided in Document 2.

FIG. 9 is a pattern diagram of the basic cell described in Document 2, and FIG. 10 is its equivalent circuit diagram.

In the technique of Document 2, the first basic cell 30 has a two-pair-of-transistor configuration consisting of a large transistor, and the first basic cell 30 has a two-pair-of-transistor configuration consisting of a small transistor arranged in parallel.
A gate array is configured with the second basic cell 40 having an OFF-transistor configuration. The first basic cell 30 includes PMO831-1, 31-2 and NMO83
2-1 and 32-2, and these are the gate electrode 33.
．． 34 and source/drain regions 35 and 36. The second basic cell 40 is PMO841-1,4
1-2 and NMO842-1°42-2, which form the gate electrode 4344 and the source/drain region 4.
It is formed by 5.46. Unused areas 47 and 48 exist at both ends of the second basic cell 40.

Reference 2 does not mention the power supply potential Vcc line and the ground potential Vss line, but assuming that they run through the center of the large transistor perpendicularly to the gate electrodes 33 and 34, the small transistor will suddenly reach the power supply potential Vcc line. and the ground potential Vss line. Therefore, even if random logic is configured by combining large and small transistors, it can be expected that the wiring will not be too crowded.

However, in such a configuration, wasteful unused areas 47 and 48 remain outside the second basic cell 40, which is disadvantageous in terms of area and is not very practical. Further, as is clear from the explanation in the above-mentioned document 1, with such a configuration, a RAM cell cannot be efficiently configured without generating idle transistors.

The present invention addresses the problems that the prior art had and that it is difficult to configure a high-speed RAM cell with a small number of basic cells without creating idle transistors.
The present invention provides a basic cell of a gate array that solves the difficulty of configuring high-speed random logic without impeding global wiring without reducing the degree of integration.

(Means for Solving the Problems) In order to solve the above problems, it is necessary to provide enough space between transistors to provide diffusion regions for P-well electrodes and N-well electrodes, and to avoid sharing the diffusion regions with other transistors. Focusing on the fact that the width (length in the vertical direction to the gate) of a single transistor is almost equal, in the invention of claim 1, the basic cell is formed by at least a plurality of pairs of first PMO3 and first N
It is composed of MO8, a pair of second PMO8 and second NMO3. Here, the second PMO 8 and the second NMO 8 are patterned so as not to share a diffusion region with other first PMO 8 and first NMO 8 .

In the invention of claim 2, the first PMO8 and the first NMO
8 alongside the first PMO3 and the first NMO8,
Moreover, it is arranged substantially inside the power supply potential line and the ground potential line.

In the invention of claim 3, the diffusion region for the P/N well electrode is arranged outside the second PMO 3 and the second NMO 8 and substantially in line with the second PMO 8 and the second NMO 8. are doing.

(Function) According to the invention of claims 1 to 3, since the basic cell is configured as described above, the second PMO 8 and the second NMO 8
Since most of the wiring can be performed inside the power supply potential line and the ground potential line, a highly integrated configuration is possible without interfering with global wiring. In addition, the first PMO8 and the first N
Since the second PMO3, the second NMO8, and the diffusion region for the P/N well electrode are laid out tightly between the MO8 and the MO8, a wasted area remains as in the conventional case shown in FIG. 9. Therefore, the degree of integration can be improved. Therefore,
The above problem can be solved.

(Example) Figure 1 (a>, (b) shows an example of the present invention,
FIG. 5(a) is a pattern diagram of a basic cell, and FIG. 2(b) is an equivalent circuit diagram thereof.

This basic cell 50 includes two PMOs 351 and 52 made of large transistors formed on an N-type semiconductor substrate, one PMO 353 made of a small transistor, and a large transistor formed in a P well region 6o in the semiconductor substrate. The NMO 863 consists of two NMOs 361 and 62 consisting of a small transistor, and one NMO 863 consisting of a small transistor.

The two (7) PMOs 851, 52 have gate electrodes 54. made of polysilicon or the like extending parallel to the vertical direction (Y direction).
55 and a source/drain P type diffusion region 57 located below it.

The sources or trains of PMOs 851 and 52 are shared and electrically connected to each other. Gate electrode 54
．． In the lateral direction (X direction) substantially perpendicular to 55, a power supply potential Vcc line is formed by the first layer metal wiring. PM
O353 is located substantially inside the power supply potential Vcc line (i.e.
The gate electrode 56 is arranged side by side in the vicinity of the PMOs 851 and 52 (lower side in the Y direction), and is composed of a gate electrode 56 extending in the Y direction, and P type diffusion regions 58 for source and drain located below it. has been done. This PMO 853 is formed independently and apart from the other (7) PMOs 851 and 52. On the outside of the PMO 853 in the Y direction (that is, on the upper side in the Y direction), an N + type diffusion region 59 for an N well electrode is formed almost on the same line as the PMO 853 .

NMO861, 62, 63 is PMO851°52.5
The large transistors NMOs 861 and 62 have gate electrodes 64 and 65 extending parallel to the Y direction, and N-type diffusion regions 67 for source and drain located below. , is formed.

The sources or trains of NMOs 861 and 62 are shared and electrically connected to each other. Gate electrode 64
．． In the X direction substantially perpendicular to 65, a ground potential Vss line is formed by the first layer metal wiring. The NMO 863 is arranged side by side substantially inside the ground potential Vss line (that is, above the Y direction) and near the NMOs 361 and 62, and has a gate electrode 66 extending in the Y direction and a gate electrode 66 located below it. Source/drain N type diffusion region 68
It is made up of. This NMO863 is similar to other NM
It is formed independently and apart from O861°62. N.M.
On the outside of O363 in the Y direction (that is, on the lower side of the Y direction),
A P type diffusion region 69 for a P well electrode is formed almost on the same line as this.

The basic cell 50 of this embodiment has the following advantages.

(a) PMO853 and N consisting of small transistors
MO863 has a structure in which its gate electrode 56.66 and diffusion region 58.68 are independent and are not commonly connected or shared with other transistors, so this PMO853
A transfer gate can be easily constructed using NMO363 and NMO363.

(b) PMO853 and N consisting of small transistors
MO863 is provided between the power supply potential Vcc line and the ground potential Vss line, and on the outside thereof, an N type diffusion region 59 for the N well electrode and a P type diffusion region 69 for the P well electrode are provided almost in a line. Therefore, the increase in area can be reduced compared to the conventional basic cell having a two-pair-of-transistor configuration shown in FIG. In other words, although it varies depending on the design rules, in the design of the present inventors, it is 8% lower than the conventional design.
On the other hand, the number of transistors is 1.
Since it is 5 times as large, if all the transistors of the basic cell are used, the degree of integration will be approximately 1.4 times.

Next, configuration examples of random logic using the basic cell 50 of the above embodiment are shown in FIGS. 11 to 13.

Fig. 11 is a pattern diagram of functional blocks used in random logic, Fig. 12 is its equivalent circuit diagram, and Fig. 13 is a pattern diagram of functional blocks used in random logic.
The figure is its logic circuit diagram.

As shown in FIG. 11, by forming a plurality of first-layer metal interconnections 70 and connecting each transistor through contacts 71 indicated by circles in the figure, Inverter 72 consisting of PMO853 and NMO363, PMO851, 52 and NMO86
A two-man power NAND gate 73 consisting of 1.62 is configured. In FIG. 11, the contact 71 marked with a circle and the sides of the rectangle indicating the power supply potential Vcc line and the ground potential Vss line are connected to the power supply potential Vcc.
A contact 71 is provided directly under the pattern of the power supply potential Vcc line or the ground potential Vss line.
This shows that the s-line and a transistor etc. are directly connected. This circuit, as shown in FIGS. 12 and 13,
The input signal I2 is inverted by an inverter 72, the NAND of the inverted signal and the input signal 11 is obtained by a NAND gate 73, and the output signal O is outputted from the NAND gate 73.

In this circuit, PMO853 consisting of small transistors,
A power supply potential Vcc line and a ground potential Vss line are arranged to run between the P/N well electrode diffusion regions 59 and 63 and the P/N well electrode diffusion regions 59 and 69, respectively. In other words, the power supply potential Vcc line and the ground potential Vss
The line pattern is PMO853,63(7) diffusion region 5
8.68 edge and diffusion region 59 for P/N well electrode
．． It was arranged so that it overlapped both the end sides of 69. Therefore,
There is no need to provide lead lines for supplying power to small transistors as in the past, making wiring easier. In addition, since the PMO85B and NMO863 are arranged inside the power supply potential Vcc line and the ground potential Vss line, even if a circuit is configured with a mixture of large and small transistors, the majority of the wiring is connected to the power supply potential Vcc line and the ground potential Vss line. It can be done inside.

Therefore, it does not significantly impede global wiring.

On the other hand, regarding the degree of integration, the conventional basic cell with two pair-of-transistor configuration shown in FIG. 3 requires two basic cells to configure the circuit shown in FIG. In contrast to the @ idle transistor, this embodiment can be configured using only one basic cell, and the degree of integration is doubled.

Moreover, the output stage is a large transistor PMO352 and N
By configuring the MO 861 and 62, high speed can also be achieved. Therefore, in this embodiment, high-speed random logic can be constructed without reducing the degree of integration.

Next, examples of the configuration of a RAM cell using the basic cell shown in FIG. 1 are shown in FIGS. 14 to 16.

FIG. 14 is a pattern diagram of the RAM cell, FIG. 15 is its equivalent circuit diagram, and FIG. 16 is its logic circuit diagram.

As shown in FIG. 14, this RAM cell consists of two basic cells 50 shown in FIG. 1 (50-1, 50-2>) to form a 1-bit cell. -1.
50-2, like the basic cell 50 in FIG.
51-1~53-1゜51-2~53-2 and NMO3
61-1 to 63-1, and 61-2 to 63-2, respectively. Write address line φwa indicated by a solid line
``■, 8 and read address line φra'' ``ra is the first
The write bit line WD and the read bit line RD, which are formed by layer metal wiring and are shown by broken lines, are formed by second layer metal wiring, and these wirings are connected to contacts 71 shown by circles or by double circles. It is connected to each transistor via the through hole 74 shown. The connections between the patterns of the power supply potential Vcc line and the ground potential Vss line and the contacts 71 are shown in the same manner as in FIG. Note that in FIG. 14, some of the wiring lines are drawn avoiding the contact 71 and the gate electrode to make the drawing easier to see.

As shown in FIGS. 15 and 16, this RAM cell consists of small transistors PMO853-1 and NMO863.
-1, an inverter 81 consisting of large transistors PMO852-2 and NMO362-2, and a second transistor PMO351-1,
52-1, a clocked inverter 82 consisting of NMOs 861-1 and 62-1, and a large transistor PMO 85.
1-2, NMO861-2 and small transistor (7)P
The clocked inverter 83 includes an MO853-2 and an NMO363-2. As is clear from the figure, there are no idle transistors in each of the basic cells 50-1 and 50-2, allowing efficient RAM cell construction.

The advantages of the RAM cell of this embodiment are compared to the conventional ones in FIGS. 7 and 8.
This will be explained below in comparison with the RAM cell shown in the figure.

0 Circuit Advantages In the basic cell 50 (50-1, 50-2>) of this embodiment, the small transistors PMO853-1 and NMO863
-1 is a pattern in which the transfer gate 80 can be easily constructed. Therefore, as shown in Figures 14 to 16,
Clocked inverter 8 that drives read bit line RD
3, small transistors PMO853-2 and NMO36 are used as transistors connected to the bit line πn.
3-2, it is possible to easily realize a configuration in which these small transistors are driven by large transistors PMO 351-2 and NMO 861-2. Therefore, depending on the circuit,
The read speed can be increased by about 20%. Further, the transfer gate 80 connected to the write bit line WD is also made up of small transistors PMO853-1 and NMO36B.
-1, so the write address line φwa' ”
High-speed writing is possible by reducing the capacity of wa.

■Advantages in Placement and Routing Regarding placement and routing, the unit of placement is not shifted to half of the basic cell when configuring random logic, unlike conventional methods, and it can be handled simply as a functional block consisting of multiple basic cells, so it is automatic. Less burden on the placement and routing system. Regarding wiring, although there are more second-layer metal wirings than in the past, there is not much difference when considered per basic cell. On the other hand, regarding the global wiring in the X direction in Figure 14, the conventional method is completely impossible between small transistors, and cannot be used between large transistors when configuring random logic, so it is wasteful to secure a large wiring area. bawl. On the other hand, in this embodiment, the area used for global wiring in the X direction is outside the basic cell 50-1. Then, all you need to do is secure the necessary wiring area according to the number of gates on the chip.
There is no significant waste caused by the component circuitry.

(2) Advantages in terms of degree of integration Conventionally, a 1-bit RAM cell could be constructed with one basic cell, but in this embodiment, two are required. However, since the areas of the basic cells themselves differ greatly as shown below, there is no large difference in the degree of integration.

That is, since a total of four small transistors are conventionally provided on both sides of a large transistor, the length in the Y direction in FIG. 14 is much larger than that of this embodiment. For example, although it varies depending on the design rules, the inventors of the present invention found that it was about 1.7 times as large. On the other hand, regarding the length in the X direction, as described above, the basic cell 50-
1.50-2 is not much different from the conventional two-pair-of-transistor configuration, and is rather larger because the conventional pattern is such that two large transistors do not share a diffusion region. Therefore, the area occupied by a 1-bit RAM cell in this embodiment is slightly larger (approximately 20%) than the conventional one. In addition, compared to the two-pair-of-transistor configuration,
The area it occupies is 1/2, and the degree of integration is sufficiently improved.

(2) Summary of the above (2) to (2) In this embodiment, when the RAMtjR is constructed, the degree of integration is greatly improved compared to the conventional two-pair-of-transistor configuration. Also, compared to the conventional one in Figure 7,
Although it is slightly inferior in terms of integration, it is superior in terms of operating speed and burden on automatic placement and routing systems.

The basic cell 50 shown in FIG. 1 can be modified into other patterns, or can be applied to various circuits such as random logic and RAM having configurations other than those shown.

(Effects of the Invention) As described above in detail, in the invention of claim 1, the basic cell is at least composed of a plurality of pairs of first PMQS and first NMO 8, and a pair of second PMQS and second N M
Since it is configured with an OS, a high-speed operating RAM cell can be configured with a small number of basic cells without creating idle transistors. Furthermore, high-speed random logic can be easily and accurately configured without reducing the degree of integration and without interfering with global wiring.

In the invention of claim 2, the second PMQS and the second NMO
8 is placed inside the power supply potential line and the ground potential line, a high-speed operation random logic can be constructed with a degree of integration that is, for example, about 1.4 times that of the conventional one, without interfering with global wiring.

In the third aspect of the invention, since the diffusion region for the P/N well electrode, the second PMQS, and the second NMO 8 are arranged substantially in the same row, no wasteful unused region remains. Therefore, in addition to the effect of the invention of claim 2, when the RAM 1 is formed, the degree of integration is greatly improved compared to the conventional two-pair-of-transistor configuration. Some of the other improved basic cells are about 20% better in terms of integration, but they are better than any other in terms of higher speed and less burden on automatic placement and routing systems. It is possible to obtain a gate array that is better than that of the conventional one.

Therefore, the gate array based on the basic cells of the invention according to claims 1 to 3 can be used in various control circuits including random logic and RAM such as high-speed and small-scale register files.
Particularly effective.

[Brief explanation of the drawing]

FIG. 1 (a>, (b) shows an embodiment of the present invention,
Figure 1(a) is a pattern diagram of a basic cell, Figure 1(b) is its equivalent circuit diagram, Figure 2 is a schematic plan view of a conventional gate array, and Figure 3 is a diagram of the basic cell in Figure 2. Pattern diagram, 4th
The figure is an equivalent circuit diagram of Figure 3, Figure 5 is a pattern diagram of a conventional basic cell, Figure 6 is an equivalent circuit diagram of Figure 5, and Figure 7 is an equivalent circuit diagram of Figure 5.
Figure 8 is an equivalent circuit diagram of Figure 7, Figure 9 is a pattern diagram of a conventional basic cell, Figure 10 is an equivalent circuit diagram of Figure 9, and Figure 11 is an equivalent circuit diagram of Figure 9. A random logic pattern diagram using Figure 1, Figure 12 is an equivalent circuit diagram of Figure 11, Figure 13 is a logic circuit diagram of Figure 11, and Figure 12 is an equivalent circuit diagram of Figure 11.
4 is a pattern diagram of a RAIVI cell using FIG. 1, FIG. 15 is an equivalent circuit diagram of FIG. 14, and FIG. 16 is a logic circuit diagram of FIG. 14. 50.50-1.50-2...Basic cell, 51
゜51-1.51-2.52.52-1.52-2...
...First PMO8, 53, 53-1, 53-2・
...Second PMO8, 61, 61-1, 61-2
゜62.62-1.62-2--・--・-first NMo
5.63.63-1.63-2...Second NM
o3.54.55.56.64.65.66...
・Gate electrode, 57.58, 59, 67.68.69・
...Diffusion area.

Claims (1)

[Claims] 1. Plural pairs of first P-channel type M with large channel widths
An OS transistor and a first N-channel MOS transistor, a pair of second P-channel MOS transistors with small channel widths each having an independently formed diffusion region, and a second N-channel MOS transistor.
A basic cell of a gate array characterized by comprising a channel type MOS transistor. 2. In the basic cell of the gate array according to claim 1, the second P-channel MOS transistor and the second
A basic cell of a gate array, in which an N-channel transistor is arranged side by side with the first P-channel MOS transistor and the first N-channel MOS transistor. 3. In the basic cell of the gate array according to claim 2, diffusion regions for P-well and N-well power supplies are provided on substantially the same line as those outside the second P-channel MOS transistor and the second N-channel transistor. The basic cell of the gate array.