JPH0498876A - Cmos master slice - Google Patents

Abstract

PURPOSE:To enable a CMOS master slice to be remarkably lessened in area by a method wherein a body contact is provided to the vertical center of each side of a basic cell, and the body contacts of the adjacent basic cells are formed into an integral structure. CONSTITUTION:The gate width W2 of an additional MOS transistor is so set as to satisfy a formula, W2<=(W1-alpha)/2, where W1 denotes the gate width of a basic MOS transistor and alpha is the vertical length of body contacts 24-27. Therefore, the body contacts 24-27 are provided to the vertical centers of the lateral sides of the basic MOS transistors, whereby additional MOS transistors can be provided on both the vertical sides of a body contact within a range of a gate width W1.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a master slice used in a gate array type LSI, and in particular, to a master slice used in a gate array type LSI. The invention relates to a CMOS master slice in which the basic cells are arranged regularly.

[Conventional technology]

FIG. 2 is a plan view showing a portion of a conventional CMOS master slice. In this example, the conductivity type of the substrate is n-type,
A p-type well region 4 is partially formed. Three elementary cells 1.2.3 are shown here, between which body contacts 5 and 6 are provided.

In each basic cell 1 to 3, the upper half has two
p-channel MOS transistors are formed,
In the lower half, two n-channel MOs are placed on the p-type well region 4.
3I-transistors are formed. It should be noted that the portion shown with a matte finish is the gate electrode of each MO5I-transistor.

Body contact portions 5 and 6 are connection portions with power supply wiring provided to set the substrate and well region 4 to power supply voltage Vdd and GND, respectively. The substrate and well region 4 are connected to power supply voltages Vdd and GN, respectively.
The reason for setting it to D is to prevent the latch-up phenomenon.

[Problem to be solved by the invention]

By the way, in order to effectively prevent the latch-up phenomenon in the conventional CMOS master slice as described above,
It was necessary to secure a dedicated area for the body contact portion every several basic cells (every three basic cells in FIG. 2).

However, the existence of such a region solely for the body contact portion reduces the number of basic cells per unit area, causing a deterioration in integration efficiency.

[Means to solve the problem]

In order to solve the above problems, the CMOS master slice of the present invention has a basic MOS transistor with a gate width of Wl, and a basic MOS transistor with a gate width of Wl for each of the p-channel MOS transistor region and n-channel MO3I-transistor region of each basic cell. A body contact part is placed at the center of the gate width direction (vertical direction) on both sides of the gate length direction (left and right direction) and has a length α in the vertical direction, and a body contact part is placed on one or both of the top and bottom of this body contact part and has a gate width W ( Here, it is provided with an additional MOS transistor of W2≦(Wl-α)/2).

[Effect]

Since the body contact portion is provided for each basic cell, there is no need to provide a region just for the body contact portion separately from the basic cell as in the conventional case.

Furthermore, since the body contact portions are provided on both left and right sides of each basic cell and at the center in the vertical direction, the body contact portions of left and right adjacent basic cells can be integrated with each other. If adjacent body contact portions are integrated to double the area per unit, it is possible that the area ratio of the body contact portions in the basic cell can be further reduced.

〔Example〕

FIG. 1 is a plan view showing a basic cell of a CMOS master slice according to an embodiment of the present invention.

Basic cell 10 includes six n-channel MOS transistors indicated by gate electrodes 12 to 17, and gate electrodes 18 to 17.
It has six p-channel MOS transistors indicated by 23. These n-channel MO3 transistors and p-channel MO8I-transistors are each arranged mirror-symmetrically in the gate width direction (vertical direction of the drawing) as shown. Between gate electrodes 14 and 16, gate electrode 1
5 and 17, between gate electrodes 20 and 22, and between gate electrodes 21 and 23, body contact portions 24 are provided, respectively.
．． 25, 26, and 27 are formed.

The body contact portions 24 and 25 include the p-well region 1.
1 is connected to the power supply wiring for making the potential of the power supply voltage GND on the low potential side power supply voltage GND, and the body contact portions 26 and 27 are connected to
Wiring for setting the substrate potential to the high potential side power supply voltage Vdd is connected.

The four MOS transistors indicated by the gate electrodes 12, 13, 18 and 19 are located at the center of the basic cell 10 in the gate length direction (horizontal direction in the drawing), so they are referred to as basic MOS transistors here. west,
Gate electrodes 14 to 17 with short gate widths on both sides thereof.
The eight MOS transistors 20 to 23 will be referred to as additional MOS transistors. That is, eight MOS transistors placed on the two outer wiring tracks 31 and 35 among the wiring tracks 31 to 35 are added to the additional MOS transistors, and eight MOS transistors are placed on the inner wiring tracks 32 and 34. There are 4 MOs
The S transistor will be called a basic MOS transistor.

The gate width W2 of the additional MOS l-transistor is the basic MO
When the gate width of the S transistor is Wl, and the length of the body contact portions 24 to 27 in the vertical direction in the drawing is α, the value satisfies W2≦(W, −α)/2. Therefore, by arranging the body contact parts 24 to 27 at the center in the gate width direction (vertical direction) on the left and right sides of the basic MOS transistor as shown in the figure, it is possible to An additional MOS transistor can be placed in the.

Further, the body contact portions 24 to 27 are integrated with the body contact portions of the basic cells 36 and 37 adjacent to each other on the left and right. In other words, the body contact portion 24.2
6 extend to the left beyond the area of the basic cell 10 and are also used as body contact portions of the basic cell 36, and similarly, body contact portions 25 and 27 each extend to the right and contact the body of the basic cell 37. Also used as a contact part. In this way, when the body contact part is shared by mutually adjacent basic cells,
The area of each body contact portion can be increased. From another perspective, if the minimum area required for each body contact part is determined and the area of the body contact part is governed by this condition, then by integrating the body The area of the contact portion can be halved.

In all basic cells, in order to make the body contact parts of adjacent basic cells common to each other (unification), it is necessary that the body contact parts are arranged symmetrically, but in this example, This is satisfied because all the body contact portions are located at the center in the gate width direction with respect to the basic MOS transistor.

In this embodiment, additional MOS transistors are provided on both upper and lower sides of each of the body contact parts 24 to 27, but they may be provided on either the upper or lower side.

〔Effect of the invention〕

As explained above, according to the CMOS master slice of the present invention, the body contact portion is formed for each basic cell, so there is no need to provide a dedicated area for the body contact portion separately from the basic cell. . Therefore, the area can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a basic cell of a CMOS master slice according to an embodiment of the present invention, and FIG. 2 is a plan view showing a basic cell of a conventional CMOS master slice. 10.36.37... Basic cell, 11... P-type well region, 12.13... Gate of n-channel basic MOS transistor, 14-17... N-channel additional MO
S transistor, 18.19...p channel basic MO
3 gates of transistors, 20-23... p-channel addition MO5I-transistors, 24-27... body contact portions. Figure 1 of Example

Claims (1)

[Claims] Plural p-channel MOS transistors and n-channel MOS
In a CMOS master slice in which a basic cell is constituted by S transistors and a large number of the basic cells are regularly arranged, the basic cell has a gate width of a p-channel MOS transistor region and an n-channel MOS transistor region, respectively. A basic MOS transistor W_1, a body contact part located at the center in the gate width direction (vertical direction) on both sides of the gate length direction (horizontal direction) of this basic MOS transistor and having a length α in the vertical direction; Gate width is W
Addition M of _2 (where W_2≦(W_1-α)/2)
A commercial characterized by being equipped with an OS transistor.
OS master slice.