JPH04151870A - Cmos gate array - Google Patents

Abstract

PURPOSE:To realize high speed operation and prevent the decrease of level of integration, by arranging a plurality of four kinds of transistors of different gate length so as to be adjacent to each other, and isolating transistor rows of different gate length, for a well whose conductivity type is different from a substrate. CONSTITUTION:Rows of P-channel transistors(Tr) 51a-51e, 81a-81e and raws of N-channel Tr's 61a-61e, 71a-71e of different gate length are arranged so as to be adjacent to each other. As to wells 54, 58 whose conductivity type is different from a substrate, Tr rows of different gate length are isolated. Further, a part of the rows of Tr's 51a-51e, 61a-61e of longer gate length is so constituted that it can be used as a wiring region for connecting macrocells. Thereby only the voltage of a power supply to be supplied to a transistor whose drain is connected with an output terminal of the macrocell can be increased, so that high speed operation can be realized and the decrease of level of integration is avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type gate array having complementary logic functional elements.

[Conventional technology]

In recent years, with the realization of higher integration and higher speed of logic integrated circuits, the transistors (hereinafter referred to as Tr) that make up the circuit have also been changed to transistors (hereinafter referred to as Tr) with gate lengths of 0.8 to 0.9 μm (hereinafter referred to as 5ub-
μm T r ) to 0.5 to 0.6 μm T
r (hereinafter referred to as half-μmTr). Here, C using half-μmTr is described below.
A configuration example in the case of a MOS gate array will be described.

FIG. 4 shows the layout of transistors in a conventional CMOS gate array constructed on a P-substrate as disclosed in, for example, Japanese Patent Laid-Open No. 57-176756, which is commonly called a mask for the logic circuit to be realized.

In the figure, (71a) to (71e) are half-μ
m N channel Tr (hereinafter referred to as N chTr), (
81a) to (81e) are half-μm P channel T
r (hereinafter referred to as P chT r), (72a) to (7
2e) are half −1, t m N chT, respectively.
Gate electrodes of r (71a) to (71e), (73a)
~(73f) are each half-μm N chT
r (71a) to (71e) source or train electrodes, (82a) to (82e) are each half-μm
The gate electrodes of P chTr (8]a) to (81e), (83a) to (83f) are half-μ, respectively.
This is the source or drain electrode of m P chTr (81a) to (81e). Also, (84) is half-
These are the well regions of μm P chTr (81a) to (81e).

In a spread type gate array, P chTr and N chTr with the same gate length are spread all over the inside of the gate array, and some adjacent P
A logic circuit of a macro cell is formed by a pair of columns of chTr and NchTr. The other transistors are not operated at all, and their regions are used as wiring channels for connecting macro cells.

Now, according to the conventional technology, the gate length of the Tr constituting the logic circuit is the same for each of P chTr and N chTr, and the well regions thereof are not necessarily separated from each other. Only one pair of power supply voltages can be used.

Next, a logic circuit constructed on the transistor shown in FIG. 4 will be explained.

FIG. 5 is a circuit diagram of a conventional logic circuit that functions, for example, as a half adder. In the figure, (11) to (17) are haI
f-μm P chTr , (21) to (27) are half-μrn N chTr , (1) is VDDl
, (2) is VSSI, VDDI (1) and VSSI (2
) is 3.3v.

Also, (31) and (32) are input terminals, (33),
(34) is an output terminal.

Next, the operation will be explained. Input terminals (31) and (3
2) When a “low” or “high” signal is input,
haIf-μm P chTr (II) ~ (15)
and halflt m N chTr (21) ~(
25), the inverted logic of the desired logic is determined, and further half-μm P chTr (16) (17) and half-μm N chTr (26), (27
), the desired logic is output to the output terminals (33), (34)
is output to.

Several inputs of the next-stage macrocells are connected to these output terminals (33) and (34), but especially in gate arrays, in order to automatically arrange and route the macrocells, the inputs of the next-stage macrocells are connected. The wiring may become long,
A large parasitic capacitance (43) (44) connects the output terminal (33) (
34). Therefore T r (16
), (17), (26), and (27) are different from other Tr (11) to (15), (2+) to (25) when large parasitic capacitances (43) and (44) are connected. However, a large current drive is required to enable sufficient charging and discharging.

On the other hand, according to the prior art, when using a half-μm Tr, (7) VDD I (1) VSSI
(2) (7)? The tt potential difference must be set to 3.3V from the viewpoint of reliability, and the potential difference between VDD and VSS is set to 5.3V using a conventional 5ub-μm Tr. Compared to the case where the circuit is configured with Ov, even if the gate length is reduced and the drain current is increased, the potential difference between VDD and vSS is 5. Since the voltage decreases from Ov to 3.3V, as a result, the drain current value of the transistor does not increase in the circuit. This will be explained with reference to the characteristic diagram in FIG.

Figure 6 shows, for example, two cases where the gate width is the same but only the gate length is different.
This figure shows the train current characteristics of different types of Tr. (a
) The figure is half-μm P chTr, (b) the figure is 5
This is the case for ub-μmPchTr. According to this characteristic diagram, half-μm P chTr is 5ub-μm
Since the gate length is smaller than P chT r, each gate
Is the drain current value increasing with respect to the source voltage?
Since the power supply voltage of the circuit using half-μmP chTr is 3.3V, half-μmP chTr is used in the circuit.
The maximum value of the drain current that can be passed through chTr is the value to the point shown in FIG. 4(a), and this is the value of the 5ub-μm P chT shown in FIG. 4(b).
In a circuit using r, Subμm P chT r
is smaller than the maximum value (point B) of the drain current that can flow. For this reason, when charging and discharging a large capacity using a transistor, the hal
f-μm P chTr The charging and discharging time is longer. This also applies to the case of N chT r.

From the above, if a gate array is constructed using only half-μmTrs, since the gate width is common, the charging/discharging time of the Tr connected to the output terminal or most of the delay of the macro cell will be taken up, so there is a problem that the speed cannot be increased. is born.

[Invention or problem to be solved]

The conventional CMOS gate array configured with a half-μm Tr was configured as shown below, so even if the potential difference between VDD and VSS is as low as 3.3V, the current drive of the Tr connected to the output terminal is still possible. To prevent power from decreasing, set Tr to 2.
It is necessary to connect them in parallel or three in parallel, which increases the macrocell area and has the problem of reducing the degree of integration of the CMOS gate array.

This invention was made to solve the above-mentioned problems, and it can achieve higher speed than the conventional half-μm Tr circuit.
It is an object of the present invention to obtain a CMOS gate array that does not require a significant reduction in the degree of integration compared to a gate array constructed only of mTrs.

[Means to solve the problem]

In the CMOS gate array according to the present invention, PchTr, Nc
For each hTr, a plurality of four types of transistors with different gate lengths are arranged in adjacent rows, and for wells of a conductivity type different from the substrate, they are separated into rows of transistors with different gate lengths. It can be used as a wiring channel that connects the -[- macrocells of the longer transistor rows to each other.

[Effect]

In this invention, the pair of transistors with a longer gate length is supplied with a second pair of power supplies higher in voltage value than the voltage value of the pair of power supplies supplied to the pair of transistors with a narrower gate length, so that the drain current value is increased. This shortens the charging and discharging time of the capacitor added to the output terminal.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a layout of transistors in a CMOS gate array constructed on a P-substrate according to an embodiment of the present invention.

In the figure, (51a) to (51e) are 5ub-μm
P chTr, its gate electrode is (52a) ~ (
52e), the source or drain electrode is (53a)
~(53f), (61a) ~(61e) are 5ub-μm
NchTr, its gate electrode is (62a) ~ (
62e), the source or drain electrode is (63a) ~
(63f), (71a) to (71e) are half-μm
NchTr, its gate electrode is (72a) ~ (
72e), the source or drain electrodes are (73a) to (
73f), (8Ia) to (81e) are halfumPc
The gate electrodes of hTr are (82a) to (82e),
The source or train electrodes are (83a) to (83f).

As shown in the figure, in this embodiment, the master
When transistors with two types of gate lengths, μm Tr and half-μm Tr, are arranged in different columns, and a P-substrate is used, a 5ub-μm PchTr well (54
) and half-μm P chTr wells (84)
and the source or drain electrodes (53a) to (53f) and (63a) of the 5ub-μm Tr.
A part of .about.(63f) is used as a wiring region connecting macro cells.

Next, the case where a logic circuit is realized on the mask shown in FIG. 1 will be explained.

FIG. 3 is a circuit diagram of a half adder according to an embodiment of the present invention, in which (11) to (15) are half adders.
m P chTr , (21) to (25) are hal
f-μm NchTr.

(116) (117) is 5ub-um P chT
r, (126) (127) is 5ub-μm Nch
It is T r. Also, (1) is VDD I, (2) +;
tVss 1, (+01) is VDD2, (102)
At VSS2, the potential difference between VDDI (1) and VSSI (2) is 3.3V, and V D D 2 (101) and V
The potential difference between S S 2 (+02) is 5. It is Ov.

In this embodiment, considering the case where the circuit is configured on a P-substrate, VSSI and VSS2 are assumed to be at the same potential Ov. In addition, (31) and (32) are input terminals, (33) and (34
) is the output terminal.

In FIG. 3, the V supplied to P chTr (116) (117) connected to the output terminals (33) (34)
D D 2 (+01) is T r (11) to (15)
, 3.3v VDD supplied to (21) to (25)
Higher than I(])5. While applying a voltage of Ov,
．． T r (L12) where the voltage of OV is applied, (117)
, (126) and (127) are 5 to ensure reliability.
The configuration uses a ub-μm Tr.

Next, the operation will be explained. Input terminal (31), (3
2) When a “low” or “high” signal is input,
half-μm P chTr (+1) ~ (+5
) and half-1-1mN chTr (2+) ~
(25) determines the inverted logic of the desired logic. At this time T r (111) ~ (15), (21) ~ (25
) or the charging/discharging capacity is at most 4 to the input capacitance of the own Tr.
It is as small as about 6 times, and the time required for charging and discharging is a small change compared to the current driving force of the Tr.

On the other hand, the determined inversion logic is 5ub-μm P chT
r(116)(117n and 5ub-μm N ch
T r (+26)(+27)l is thereby inverted and outputted to the output terminals (33) (34) as desired logic. These output terminals (33) and (34) have T r(1
1) to (15), (21) to (25), or parasitic capacitances (43) and (44) larger than the charging/discharging capacity are added. However, the sources of T r (116) and (+17) have a potential difference higher than VDDI (1) of 3.3V. Since VDD 2 (+01) of Ov is applied, the train current of T r (116) (117) becomes T r (11) to ( +5), (21) to (25)
The parasitic capacitance (43) (
44) can be charged faster than before. As a result, the load capacitance dependence of the macrocell can be improved, and the speed inside the gate array can be increased.

Next, a case where the half adder described in FIG. 3 is realized on the mask described in FIG. 1 will be described.

FIG. 2 is a layout of a half adder of a CMOS gate I array according to the present invention. In the figure, (3) is a contact hole, (4) is a peer hole, and (5) is a half adder.

(105) is the first layer wiring, (6) is the second layer wiring, (10
1) is VDD2, (10
2) is VSS2 composed of the first layer wiring (5), (2)
VSSI is made up of the first layer wiring (5), and (1) is VDD I made up of the first layer wiring (5). Also,
(52a) ~ (52g), (62a) ~ (62g),
(72a) ~ (72g), (82a) ~ (82g)
are 5ub-μrn P chTr and 5u, respectively.
b-μmN chTr, half-μmN ch
T r, half-μm P ch T r gate electrode, (53a) to (53h), (63a) to (63
h), (73a) to (73h), (83a) to (83
h) are 5ub-μrn P cllTr and 5u, respectively.
b-μmNchTr, half-μmNchTr,
This is the source or drain electrode of half μm P chT r, and is the same as in FIG. Also, (11) ~ (
+5), (21)~(25), (+16)~(1
17), (+26) to (127) are hal
f-μm P chTr, half-μm N c
hTr, 5ub-, cz mPchTr, 5u
The b-μm NchTr corresponds to the Tr shown in FIG.

According to this embodiment, the output terminal (33) in FIG.
5ub-μm T r (I]6) connected to (34)
~(117).

(+26) ~ (+27) only half-μm T r
By arranging (11) to (15) and (2+) to (25) in different columns, Subμm and PchTr wells [Figure 1 (54)] and half-μmPchTr
Since the wells [Fig. 1 (84)] can be completely separated,
Not only is it possible to use VDDI (1) and VDD2 (+01) with different voltages at the same time, but also 5ub-
μm T r (116) ~ (+17), (126)
The number of first layer wirings (105) connected to ~(127) is ha
lf -1t m T r (11) - (15) (21)
Since the number is much smaller than the number of first layer wirings (5) connected to ~(25), the 5ub-μm Tr source or drain electrodes (53a) ~(53h), (63a) ~(6
It is possible to use most of the area 3h) not as a wiring area inside the macrocell but as a wiring channel for wiring between macrocells.

Generally, in a macro cell, a transistor whose output terminal and drain are connected often constitutes an inverter circuit. Therefore, if this example is used, 5ub-μmT
As a result of being able to utilize some of the r area for interconnect channels, VDDI and VSSL can be
half- using two power supplies: and VDD2-VSS2
It is possible to obtain a gate array that can constitute a faster circuit than the conventional one, which is composed of two types of transistors, .mu.m Tr and 5 ub-.mu.m.

In addition, in the above embodiment, the source or drain electrodes (53a) to (53h), (63a
) ~(63h) as the source or train electrode of half-μmTr (73a) ~(73h), (83a) ~
A case where the shape is different from (83b) is shown, or the same shape may be used. A part of the 5 ub-μm Tr can be used for the wiring channel.

In addition, the above embodiments show the case of a P-substrate, or the case of an n-substrate.
The substrate may be a thin film transistor using an insulator as the substrate, and in particular, in the case of an n-substrate, 5ub-μm N
chTr well and half-μm NahTr
A layout that separates the wells is fine.

In addition, in the above embodiment, the half-μmTr of the 3V power supply
and 5) The case of a 5 ub-μm Tr system power supply is shown, or if the voltage value with which the amplitude operation is guaranteed is different, and if a Tr with a different gate length is used, other gate lengths may be used.
For example, 2v system 0.2~0.3μmTr and 3v system 0.5~
Even when using 0.6 μm Tr, the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the transistor rows arranged inside the CMOS gate array include a row of P-channel transistors and a row of N-channel transistors having different gate lengths, and are arranged next to each other, and are of a conductivity type different from that of the substrate. The well is separated into transistor rows with different gate lengths, and a part of the transistor row with the longer gate length can be used as a wiring area between macro cells, so that the output terminals of the macro cells can be connected to each other. It is possible to increase only the voltage of the power supply supplied to the transistor whose drain and drain are connected, making it possible to obtain a CMOS gate array that is faster than conventional ones and does not have a large degree of integration compared to conventional ones. effective.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a layout of transistors in a CMOS gate array according to an embodiment of the present invention, and FIG. 2 is a plan view showing a layout when a half adder is configured on a CMOS gate array according to an embodiment of the present invention. Figure, 3rd
FIG. 4 is a circuit diagram of a half adder according to an embodiment of the present invention.
The figure is a plan view showing the layout of transistors in a conventional CMOS gate array, Figure 5 is a circuit diagram of a conventional half adder, and Figures 6 (a) and (b) are characteristic diagrams showing the train characteristics of transistors. . In the figure, (1) is VDDI, (2) is VSSI, (
+01) is VDD2, (+02) is VSS2, (3) is contact hole, (4) is peer hole, (5) (+0
5) is the first layer wiring, 6 is the second layer wiring, (51a) to (5
1e). (116), (117) are 5ub-μm P chT
r, (61a) to (61e). (126) (127) is 5 ub-μm N chTr
, (71a) to (71e) (2]) to (25) are half-μmNchTr, (81a) to (81e
). (11) to (15) are half-μm P chT
Indicates r. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] a semiconductor substrate of a first conductivity type; a first semiconductor region of a second conductivity type formed in a part of the semiconductor substrate; and a first semiconductor region formed in a part of the semiconductor substrate and separated from the first semiconductor region. a second semiconductor region of a second conductivity type; a first transistor of a first conductivity type formed in the first semiconductor region; and a second transistor of a second conductivity type formed in a portion of the semiconductor substrate. a transistor formed in the second semiconductor region and a first transistor formed in the second semiconductor region;
The third transistor of the first conductivity type has a longer channel length than the transistor of
a fourth transistor of a second conductivity type formed in a part of the semiconductor substrate and having a longer channel length than the second transistor; a first high potential side power supply and a low potential side power supply; a second high-potential power source and a low-potential power source that are set to a higher potential difference than the potential difference between the high-potential power source and the low-potential power source; A plurality of transistors No. 4 and No. 4 and a third transistor are arranged in a row next to each other, and a required number of pairs among the plurality of pairs are used to constitute a cell having a logic function. Further, a CMOS gate array characterized in that a part of the third and fourth transistors is used as a wiring channel region for interconnecting the cells having the logic function.