JPS59127424A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the noise tolerance of an integrated circuit device which uses a CMOS transistor (TR) and to reduce the switching speed difference by reducing the diffeence in the threshold voltage between the input terminal of a basic gate circuit and a corresponding composite gate circuit. CONSTITUTION:A series-connected TR groups of P or N channel MOSTRs and a series-connected TR group of the same number of TRs of the same kind are connected together in parallel; the gates are connected in crossing direction each other between the TR groups to constitute the base circuit and composite gate circuit as a load or driving element. Consequently, the difference in the circuit threshold value between the upper and lower stages is canceled, so the noise tolerance is improved.

Description

[Detailed description of the invention] The present invention relates to a semiconductor device.

In recent years, integrated circuit devices (
ICs) are now on the market and are rapidly growing in the consumer equipment market. In addition, as the market expands, use in personal portable electronic devices is increasing, so driving with a single low power source and high reliability are required conditions.

Accurate operation at low power supply and noise tolerance are emphasized.

In 0MO8, the DC shoe noise margin guaranteed value is generally 30 degrees of the electrolysis voltage, and the margin is high (.), but the relative margin against noise outside the IC decreases as the power source becomes lower.

NOR in the logic circuit of 0MO8.

A basic gate such as NAND has a configuration as shown in Fig. 1.3.5 and has a transfer characteristic as shown in Fig. 2.4.6.

(The numbers on the characteristic curves in Figure 2.4.6 correspond to the terminal numbers in Figure 1.3.5.) From these transfer characteristics, it can be determined that there is a difference in threshold voltage between the input terminals of the circuit. , It can also be seen that as the number of inputs increases, the difference in the maximum and minimum circuit threshold voltages increases.Due to the difference in the threshold voltages of the circuits, there is also a difference in switching speed, and in terms of circuit design, There is a problem in estimating the timing of the signal.From the above, it can be understood that using a series-connected gate group for the load element and drive element has a difficult point in IC design.

In gate arrays using the CMOS master slice switching method, the logic is constructed by connecting basic cells, each consisting of a pair of P-type and N-type transistors with uniform channel width, channel length, and threshold voltage. Compared to dedicated semiconductor integrated circuits, the maximum number of basic gate circuits and the number of inputs are more limited.

The object of the present invention is to provide a threshold voltage of a circuit between input terminals in a basic gate circuit and a similar composite gate circuit when using P-type and N-type MOS transistors connected in series with a load element and a drive element. By reducing the difference between
The object of the present invention is to simplify the design of a semiconductor integrated circuit by improving noise tolerance and reducing the difference in switching speed between input terminals.

A feature of the present invention is that a transistor group 1 consisting of a plurality of P-channel MOS transistors or N-channel MOS transistors connected in series and a transistor group 2 consisting of the same type and number of series connections are connected in parallel. The semiconductor device uses a circuit system in which the respective gates are connected in the opposite direction between transistor groups to form a basic gate circuit and a composite gate circuit as a load element or a driving element. It is desirable that this semiconductor device be designed using a master slice method.

An embodiment of the present invention will be described below with reference to the drawings.

Let us take as an example a basic CMOS gate circuit that often uses series connections of transistors (MOS). In the case of a NAND type circuit, the eighth
Like the two-man NAND shown in the figure, N-channel type MO8)
Two transistor groups, each consisting of two transistors connected in series for the number of inputs, are connected in parallel between the output terminal and GND, each gate is connected in the opposite direction between the transistor groups, and connected in parallel between the power supply and the output. By connecting to the gate of the P-channel type MO transistor (8), the slight difference in circuit threshold between the upper and lower stages of the N-channel type transistor is canceled out. In the case of a NOR type circuit, the two-person NOR circuit shown in Figure 7
Connect two transistor groups in parallel between the power supply and the output, each consisting of two P-channel transistors connected in series for the number of inputs, and connect the gates of each transistor in the opposite direction between the transistor groups. It is connected to the gate of the N-channel type MO8 transistor connected between the car GND and cancels out the threshold value of the circuit for the inputs of the upper and lower stages of the P-channel transistors. Figure 9 shows the case of a three-person powered NOR circuit. Three P-channel M08 transistors connected in series and the same transistor group are connected in parallel between the power supply outputs, and the gates are connected in the opposite direction between the two transistor groups, as in the case of a two-power NOR circuit. , output car GND
It is connected to an N-channel MOS transistor connected in parallel between them.

In the two sets in which the gates of the P-channel type MO8) transistors in the top and bottom stages are connected, the threshold voltages of the circuits cancel each other out, but in the case of the gate connections in the middle stage and the middle stage, they do not cancel out. For this reason, in the case of a three-person powered NOH, a circuit threshold (・value occurs) for the two input terminals.

FIG. 10 shows the case of a three-person powered NAND circuit. Three series-connected N-channel type MO8) transistors and the same transistor group are connected in parallel between the output and GND, and the gates are connected in the opposite direction between the two transistor groups as in a two-man NAND circuit. P connected in parallel between power supply and output
Connect to channel type MOS transistor. In this case as well, similar to the three-power NOR circuit described above, a circuit threshold voltage is generated for two input terminals. In the case of a basic gate with an odd number of inputs, (n+1)72 circuit threshold voltages are generated. Figure 11 shows the case of a four-person NOR circuit. In this case, there are two circuit thresholds.

FIG. 12 shows the case of a four-person powered NAND circuit. this place
It has two circuit thresholds like the four-man power NOR circuit. In the case of an even number of inputs, there are n 72 circuit thresholds. In a normal CMOS master slice gate array, the first
As shown in Figure 4, the basic cell is often configured as a pair of a two-gate P-channel type MO8) transistor and an N-channel type MOS transistor.

P channel type MO8) Channel length of transistor is 3.0
The length of the transistor is 2.5 μm, and the channel width of the P-channel and N-channel MOS transistors is 54 μm.

P channel type MO8) transistor threshold (・value voltage -
1, IV, Nf Jarnel type MO8) transistor threshold (・
5-person power NAND circuit when the value voltage is 0.75V,
The layout of the 5-input NOR circuit on the aforementioned general basic cell is shown in FIGS. 15 and 16, respectively, and its transfer characteristics are shown in FIGS. 19 and 21, respectively. Figure 19, 2nd
From Figure 1, the maximum and minimum differences in the threshold voltages of the circuits are 0.4V for the 5-input NAND circuit and 0.2V for the 5-input NOR circuit.

Also, power supply based on AC simulation5. OV time 17)
The difference between the maximum and minimum itching speed is 52 manual NAN
The rise time of the D circuit is 1.6 NS, the fall time is 0.5 NS, and the rise time of the 5-input NOR circuit is 2.8 NS, and the fall time is 0.5 NS.

Layout examples for implementing the present invention using a master slice type CMOS gate array are shown in Figures 17 and 18. FIG. 17 shows a five-input NAND circuit, and FIG. 18 shows a five-input NOR circuit. Among the Y transistor parameters mentioned above, only the channel length of the P-channel type and N-channel type MO8) transistor is configured to H, which is 27 μm, and the transfer characteristics when this layout example FIGS. 17 and 18 are realized are shown in FIG. 22.

The difference between the maximum and minimum threshold voltage of the circuit is 5 manual NAND
0.07V in the circuit, 0.03 in the case of a 5-input NOR circuit
It becomes V. Also, power supply voltage based on Ae simulation 5.
The difference between the maximum and minimum switching speed for Ov is 5
In the case of a human-powered NAND circuit, the rise time is 0.2NS,
The fall time is 0.2NS, and in the case of a 5-input NOR circuit, the rise time is 0.4NS and the fall time is 0.2NS.
It is greatly improved to 2NS.

In addition to CMO8, it can also be applied to NAND circuits in which MOS transistors are connected in series. As an application example, the 23rd
The figure shows a two-person NAND circuit with an enhanced depletion configuration of N-channel MOS transistors.

If the present invention is applied to a semiconductor integrated circuit, its effects will be obvious and effective.

[Brief explanation of drawings]

Figure 1 is a conventional 0MO8 two-man NAND circuit diagram, Figure 2
The figure shows the general transfer characteristics of the 0MO8 2-input NAND circuit shown in Fig. 1, Fig. 3 shows the conventional 0MO8 2-input NOR circuit diagram, and Fig. 4 shows the general transfer characteristic of the 0MO8 2-input NOR circuit shown in Fig. 3. Characteristics, Figure 5 shows the conventional 0MO8 4-person NAND
Circuit diagram, FIG. 6 shows the general transfer characteristics of the 0MO8 four-power NAND circuit shown in FIG. 5, and FIG. 7 shows the 0MO8 according to the embodiment of the present invention.
2-input NOR circuit, FIG. 8 shows a C-MO according to an embodiment of the present invention.
2/VINAND circuit of 8, FIG. 9 is 0 of the embodiment of the present invention.
MO8 3-input NOR. Circuit, Figure 10 is a three-man power NA of 0MO8 of the embodiment of the present invention.
ND circuit, Fig. 11 shows a 0MO8 4-input NOR circuit according to an embodiment of the present invention, Fig. 12 shows a 0MO8 4-manpower NAND circuit according to an embodiment of the invention, and Fig. 13 shows a 0MO8 5-manpower NAND circuit according to an embodiment of the invention. Figure 14 is a partial plan view of a general CMOS basic cell used in a master slice type gate array, and Figure 15 is a partial plan view of a conventional general CMOS master slice basic cell. The figure shows a 5-input NOR circuit layout using a conventional general CMOS master slice basic cell, and Figure 17 shows a 5-input NAND circuit layout using a CMOS master slice basic cell configured to realize the present invention. Figure 18 shows the layout of a 5-input NOR circuit using a CMOS master slice basic cell configured to realize the present invention, (patent example) Figure 19 shows the 5-manpower NAN shown in Figure 15.
The transfer characteristics of the D circuit, Figure 20 is the 5-man power NAN of Figure 17.
The transfer characteristics of the D circuit, Figure 21 is the 5-input NOR shown in Figure 16.
FIG. 22 shows the transfer characteristics of the 5-input NOR circuit shown in FIG. 18, and FIG. 23 shows the two-man power NAND circuit of the N-channel type MO8, E/D configuration according to the embodiment of the present invention. In addition, in the figure (1... power supply aluminum wiring, 2... P-type diffusion layer, 3... N-type diffusion layer, 4... GND aluminum wiring, 5...
. . . Contact portion, 6 . . . Gate polysilicon. VDD Fig. 1 Fig. 2 Fig. 3 Fig. 4 No. 7 Fig. ■ Fig. 2 Fig. 1/Fig. 79 Fig. 72 Fig. 6 Fig. 77 Fig. 18 V] Vin (V) Figure 27

Claims (1)

[Claims] A first transistor group consisting of a series connection of a plurality of transistors and a second transistor group consisting of a series connection of a plurality of transistors are connected in parallel, and each gate is connected between the transistor groups. A semiconductor device characterized in that the semiconductor device is connected in opposite directions to form a basic gate circuit and a composite gate circuit as a load element or a driving element.