JPH023279A - Standard cell of complementary mis master slice lsi - Google Patents

Abstract

PURPOSE:To enable the stray capacitance of wiring to be made small and realize high speed operation of a gate by arranging the P-type diffusion area and the N-type diffusion area of a P-type MIS transistor in the transverse direction, and arranging the N-type diffusion area and the P-type diffusion area of an N-type MIS transistor in the lateral direction at the positions pointwise symmetrical with respect to the central position of a fundamental cell. CONSTITUTION:The array of an N-type diffusion area (i) which forms an electrode to apply voltage to an N-well and a P-type diffusion area (f) which forms a P-type MIS transistor, and at the positions pointwise symmetrical with respect to the central position of a fundamental cell, the array of a P-type diffusion area (j) which forms an electrode to apply voltage to a P-substrate and an N-type diffusion area (g) which forms an N-type MIS transistor are arranged, respectively, as shown in the figure. If the two-input NAND gate is constituted, the diffusion areas of a P-type MIS transistor and an N-type MIS transistor connected to an output terminal 3 are on the same wiring pitch, and the metallic wirings become straight, whereby the wiring length can be shortened, and the stray capacitance can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention has high functionality, high integration, and design.

The present invention relates to a complementary MTS master slice LSI that has a short manufacturing TAT (turnaround time).

[Conventional technology]

The basic cell (Ba5) of a channelless master slice chip constructed using conventional complementary MIS transistors
ic Ce1l) will be explained as an example. FIG. 1 is a schematic diagram of a channelless master slice LSI to which the present invention and a conventional basic cell are applied.

In the figure, a is a basic cell, b is a peripheral circuit, C is a basic cell array area, and d is a peripheral circuit array area.

The basic cell array area C inside the chip is an area where the basic cells a are laid out in a matrix without gaps, and the peripheral circuit array area d is an area that accommodates pads and peripheral circuits including 110 circuits.

Conventionally, examples of the configuration of the basic cell a arranged in the basic cell array area C include those shown in the diagrams of the conventional first to fourth basic cells shown in FIGS. 2 to 5. In the figure, P is an F type MIS transistor, N is an N type MIS transistor, C is a gate electrode, i is an N type diffusion region, " is a P type diffusion region, j is a P type diffusion region, and g is an N type diffusion region. , h is the outer frame of the basic cell.The N-type diffusion region i is for the electrode that applies voltage to the N-well, and the P-type diffusion region f is for the source electrode and drain electrode of the P-type MIS transistor. Form.

Further, the P type diffusion region j is for an electrode for applying a voltage to the P substrate, and the N type diffusion region g forms the source and drain electrodes of the N type MIS transistor. In the first to fourth basic cells shown in the figure, two-person and four-person coverage formats are used.

In the configuration examples shown in FIGS. 2 and 3, the gate electrode of the P type M I S transistor constituting the basic cell and the gate electrode of the N type M I S transistor
In this method, the gate electrodes of the transistors are separated from each other in advance, and the two are connected by metal wiring in order to realize the function when requested by the user.

[Problem to be solved by the invention]

However, when attempting to incorporate complex functions such as functional macrocells while achieving both speed, power consumption performance, and integration, gates with different drive capacities are required depending on load conditions such as fan-out number, just like in a fully custom LSI. Flexibility in design that can be selectively configured is desired. In the case of Figures 2 and 5, the P-type MIS transistor or N-type MTS transistor that constitutes the basic cell a is configured with one type of channel width (W), so if you want to increase the driving capacity, the configuration gate It is difficult to finely adjust the channel width (W). Therefore, as shown in the configuration diagram of a power gate using the first basic cell in FIG. By connecting them in parallel, a NAND gate (power gate) with twice the driving capacity was realized. FIG. 7 is an equivalent circuit diagram of the power gate of FIG. 6. Since such a method doubles the occupied area, its applicable area is limited.

In order to compensate for this drawback, as a conventional example, as shown in the diagram of the conventional fifth basic cell in FIG. 8 and the diagram of the conventional sixth basic cell in FIG. type fM
I S Transistor U and N with small channel width (W)
There is a configuration in which a conventional large channel width (W) and a small channel width (w) are combined using a type MIS transistor V. However, in this configuration, transistors with large channel widths (W) and small channel widths (V
The ratio of the number of transistors configured in V) is fixed, and depending on the functional macro to be configured, the number of unused transistors increases, which causes a reduction in the overall degree of integration. Another drawback is that the channel width of the transistor prepared in advance is fixed.

[Means to solve the problem]

The vertical direction is the channel width direction, and the horizontal direction is the channel length direction, with P-type MIS transistors in half and N-type M in the other half.
In a channelless master slice LSI consisting of a basic cell composed of complementary MIS transistors in which IS transistors are arranged, a P-type diffusion region forming the source electrode and drain electrode of the P-type M■S transistor;
N-type diffusion regions forming electrodes for applying a voltage to the well are arranged horizontally, gate electrodes are provided on the upper surface of the P-type diffusion region to form half of a basic cell, and the center is centered at the center position of the basic cell. N-type diffusion regions forming the source electrode and drain electrode of the N-type MIS transistor and P-type diffusion regions forming an electrode for applying voltage to the P substrate are arranged laterally at positions symmetrical to the point, A gate electrode was provided on top of the N-type diffusion region to form the other half of the basic cell.

〔Example〕

FIG. 10 is a diagram of the seventh basic cell of the present invention, and FIG. 11 is a diagram of the eighth basic cell of the present invention. In this example, an N-type diffusion region i and a P
P type diffusion region f for forming type MIS transistor
and a P-type diffusion region j for forming an electrode for applying a voltage to the Pi board and an N-type diffusion region for forming an N-type MIS transistor at points symmetrical positions with respect to the center position of the basic cell. The array of region g was arranged as shown in the figure.

Figure 12 shows a two-person NAN configured using the 7th basic cell.
D gate, Figure 13 shows 3 constructed using the 8th basic cell.
14 is an equivalent circuit diagram of FIG. 12, and FIG. 15 is an equivalent circuit diagram of FIG. 13.

The diffusion regions of the P-type MIS transistor and the N-type MIS transistor connected to each output terminal 3.7 are on the same wiring pitch (arrows shown in the figure), and the metal wiring is routed straight and the wiring length is It can be seen that there is a tendency to reduce stray capacitance by shortening the length.

Figure 16 is a configuration diagram using the conventional third basic cell;
The figure shows a configuration diagram using a conventional fourth basic cell, with two
A human powered NAND gate and a three human powered NAND gate are shown. The diffusion regions of the P-type MIS transistor and the N-type MIS transistor connected to each output terminal 3.7 are on the same wiring pitch (arrows shown in the figure) (the metal wiring is not on the same straight line but straight). Since the wiring is not wired, the wiring length becomes long and the stray capacitance also increases.Also, the through hole shown by 5 in Fig. 17 has dense wiring, so it can only be placed at a pitch of 0.5, which is an integer multiple of 1 pitch. This is because even if the polysilicon that forms the gate electrode is expanded as shown by the hatch in the figure, the flexibility of the wiring will not necessarily be improved. The flexibility of wiring is inferior to the embodiments of the present invention shown in FIGS. 10 and 11.

FIG. 18 is a configuration diagram showing the superiority of the basic cell of the present invention. - Metal wiring 50.51.52. shown as an example in the figure.
By performing steps 53 and 54, it is possible to connect the necessary portions of the polysilicon of the gate electrode to obtain the required channel width, and to connect other metal interconnections 55.
56, 57, and 58, and can be routed horizontally.

FIG. 19 is a diagram of the ninth basic cell of the present invention.

This is an embodiment of the ninth basic cell that applies claim 1.2.3 at the same time.
The type diffusion region and the N type diffusion region are divided into two in the channel width direction to create two MIS transistors with small channel widths.

Additionally, in order to use the divided MIS transistors in parallel, six polysilicon wirings for connecting gate electrodes were provided.

The polysilicon wiring 2 is vacant for an adjacent basic cell.

Figure 20 shows a two-person NAN using the ninth basic cell of the present invention.
It is a block diagram of D gate. By connecting the two divided transistors in parallel with metal wiring in this configuration example,
Combine the small channel widths and equivalently channel width (W)
is expanding. Polysilicon wiring y is input electrode 1.
It is also effectively used because the wiring connected to VOO1GND intersects with the power supply wiring VOO1GND.

Figure 21 shows a two-person NOR using the ninth basic cell of the present invention.
It is a block diagram of a gate.

Figure 22 shows a two-person NAN using the ninth basic cell of the present invention.
This is another configuration diagram of the D gate, but since it is constructed using divided transistors with a small channel width (W), both the occupied area and the driving capacity are small.

Figure 23 shows a two-person NOR using the ninth basic cell of the present invention.
FIG. 3 is another configuration diagram of the gate.

Next, an example of a functional macro constructed using the basic cell a of the present invention will be shown. Figure 24 is a circuit diagram of the selector circuit,
FIG. 25 is a block diagram of the selector circuit of FIG. 24 using the ninth basic cell of the present invention.

In this configuration example, all component transistors use divided transistors, and the unused transistor area is
It is used as a wiring area for selector control signals to increase the efficiency of occupied area.

FIG. 26 is a circuit diagram of a decoder circuit, and FIG. 27 is a block diagram of a decoder circuit using the ninth basic cell of the present invention. Inverter IVI and inverter IV2 have a fanout of 1 and have a light load, so they are configured with a small channel width (W), and the ANDOR gate AD is configured with a large channel width (W) assuming a case where the load is large. As in this configuration example, gates having different channel widths can be configured relatively freely as necessary.

The above explanation is based on the complementarity of semiconductors, and the N type of the basic cell is changed to P.
This also holds true even if the P type is replaced with the N type.

〔Effect of the invention〕

NAN which is the basic cell of claim 1 and is the basic unit of CMO3
When configuring D gates and NOR gates, P-type MIS
Since the metal wiring connecting between the source electrode and the drain electrode of the N-type MIS can be short and straight, the stray capacitance of the wiring can be reduced, and as shown in Figures 12 and 13.
The operating speed of the gate configured as shown in the figure can be increased. Furthermore, adjacent gate electrodes can be connected to each other by metal wiring while ensuring a region for metal wiring to connect between the source electrode and drain electrode of the P-type MIS and the N-type MIS.

By connecting the source electrodes, drain electrodes, or gate electrodes of the divided MIS transistors of the complementary MIS master slice LSI of claim 2 with metal wiring or not connecting them, the channel width (W) of the constituent gates can be changed.
Therefore, when configuring a functional macro, it is possible to optimize the driving ability of the constituent gates, thereby increasing the speed of the functional macro cell and reducing the occupied area.

Claim 4 provides that when claim 2 is realized, if polysilicon wiring is placed in advance to connect between the divided gate electrodes, metal wiring and metal wiring can be formed as shown in FIGS. Gate electrodes can be wired freely while crossing each other.

In this way, if the basic cell of the present invention is used and a channelless master slice LSI is used, logic circuits can be configured efficiently by combining gates with different channel widths (W) as necessary, so that functional macros can be configured more efficiently. This makes it possible to design flexible circuits according to load conditions such as fan-out number, and is expected to improve speed and integration.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a channelless master slice LSI to which the present invention and a conventional basic cell are applied; FIG. 2 is a diagram of a conventional first basic cell; FIG. 3 is a diagram of a conventional second basic cell; Fig. 4 is a diagram of a conventional third basic cell, Fig. 5 is a diagram of a conventional fourth basic cell, Fig. 6 is a configuration diagram of a power gate using the first basic cell, and Fig. 7 is a diagram of a conventional fourth basic cell. 8 is a diagram of the conventional fifth basic cell, FIG. 9 is a diagram of the conventional sixth basic cell, FIG. 10 is a diagram of the seventh basic cell of the present invention, and FIG. The figure is a diagram of the eighth basic cell of the present invention, No.
Figure 2 shows a two-man power N constructed using the seventh basic cell of the present invention.
FIG. 13 is a configuration diagram of an OR gate; FIG. 13 is a configuration diagram of a three-man power NOR gate constructed using the eighth basic cell of the present invention;
The figure is an equivalent circuit diagram of Figure 12, Figure 15 is an equivalent circuit diagram of Figure 13, Figure 46 is a configuration diagram using the conventional third basic cell, and Figure 17 is a configuration diagram using the conventional fourth basic cell. Configuration diagram, 1st
Figure 8 is a configuration diagram showing the superiority of the seventh basic cell of the present invention.
Figure 19 is a diagram of the ninth basic cell of the present invention, Figure 20 is a configuration diagram of a two-man NAND gate using the ninth basic cell of the present invention, and Figure 21 is a diagram of the ninth basic cell of the present invention. 2 person power N
The configuration diagram of the OR gate, Figure 22 is the configuration diagram of the two-man powered NAND gate using the 9th basic cell, and Figure 23 shows the two-man powered NO gate.
The configuration diagram of the R gate, Figure 24 is the circuit diagram of the selector circuit,
25 is a block diagram of the selector circuit of FIG. 24 using the ninth basic cell of the present invention, FIG. 26 is a circuit diagram of the decoder circuit, and FIG. 27 is a block diagram of the selector circuit of FIG. 24 using the ninth basic cell of the present invention. FIG. 2 is a configuration diagram of a decoder circuit. a is a basic cell, b is a peripheral circuit, C is a basic cell array area,
d is a peripheral circuit array area, P is a P-type MIS transistor,
N is an N-type MIS transistor, e is a gate electrode, and i is N
type diffusion region, f is P type diffusion region, j is P type diffusion region, g
is the N-type diffusion region, 11 is the outer frame of the basic cell, m is the contact hole, k is the first layer metal wiring, t is the through hole,
U is a P-type MIS transistor with a small channel width, ■ is an N-type MIS transistor with a small channel width, (W) is a small channel width, (W) is a large channel width, and y is for connection between separated gates. polysilicon wiring,
2 is a polysilicon wiring for connecting adjacent separated gates. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (4)

[Claims] (1) Channelless type consisting of a basic cell consisting of complementary MIS transistors, with the vertical direction being the channel width direction and the horizontal direction being the channel length direction, with a P-type MIS transistor in one half and an N-type MIS transistor in the other half. In a master slice LSI, a P-type diffusion region forming the source electrode and drain electrode of the P-type MIS transistor and an N-type diffusion region forming an electrode for applying a voltage to the N-well are arranged laterally, and the gate electrode are provided on the upper surface of the P-type diffusion region to constitute half of the basic cell, and the source electrode and drain electrode of the N-type MIS transistor are formed at positions symmetrical about the center position of the basic cell. A P-type diffusion region and a P-type diffusion region forming an electrode for applying a voltage to the P substrate were arranged laterally, and a gate electrode was provided on the upper surface of the N-type diffusion region to constitute the other half of the basic cell. A basic cell of a complementary MIS master slice LSI characterized by the following. (2) The P-type diffusion region and the N-type diffusion region that form the source electrode and the drain electrode are divided in the channel width direction to form an MIS transistor with a small channel width, and the MIS transistors are connected in parallel to form a large MIS transistor. Width MI
Complementary MIS according to claim 1, forming an S transistor.
Basic cell of master slice LSI. (3) The complementary type M according to claim 1 and claim 2, wherein the N type of the basic cell is replaced with a P type, and the P type is replaced with an N type.
Basic cell of IS master slice LSI. (4) Complementary MI according to claim 2, comprising polysilicon wiring for connecting divided MIS transistor gate electrodes.
Basic cell of S master slice LSI.