JPS6017930A - Basic cell in master slice system - Google Patents

Abstract

PURPOSE:To reduce the occupying area by composing not only a logic circuit such as an NAND or an NOR but also an RAM, a transmission gate circuit with less number of basic cells, thereby eliminating the production of excess transistors. CONSTITUTION:Two further p-channel transistors QP3, QP4 are aligned in parallel outside a p-channel region having two p-channel transistors QP1, QP2, and two further n-channel transistors QN3, QN4 are aligned in parallel outside an n- channel region having two n-channel transistors QN1, QN2. Therefore, when a 2- input NAND or 2-input NOR is composed, the same wirings as those using the conventional basic cell are formed, and when a transmission gate circuit or a clocked gate circuit is composed, newly added four transistors are used. Thus, when compared with the case that the conventional basic cell is used, the circuit may be formed in an area of 1/2-1/3.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to improvements in basic cells for configuring large-scale integrated circuit devices (LSI) manufactured through a mask-slicing method.

Conventional technology and problems In the mask slicing method, a large number of basic cells consisting of multiple transistors and resistors are manufactured in advance in one semiconductor chip, wiring masks are created according to the required product, and the wiring masks are By using this method, processing is performed to connect transistors and resistors to complete an LSI that performs the desired operation.

Conventionally, the basic cell described with reference to FIGS. 1 and 2 is known as a basic cell applied when implementing the mask slice method.

FIG. 1 is an equivalent circuit diagram of a main part of a conventional basic cell.

In the figure, QPI and QP2 are n-channel transistors, and QNI and QN2 are n-channel transistors, respectively.

As shown in the figure, transistors 1 to QPI and QP2 or QNI and QN2 of the same channel share either one of their sources or 1 to transistors, for example QPI and QNI, or QP2 and QN2, each share a gate.

FIG. 2 is a plan view of a main part showing a so-called bulk pattern that embodies the circuit configuration of the basic cell shown in FIG. 1, and the same parts as those explained in connection with FIG. .

In the figure, 1 is a p-type impurity diffusion region, 2 is an n-type impurity diffusion region 11, 301 and 3G2 are polycrystalline silicon 1-full poles, 4CN is an n-type substrate contact 1-pattern, 4CP indicate p-type substrate contact patterns, respectively. Note that the n-type impurity diffusion region 1 is the source region of the n-channel transistors QPI and QP2.
The n-type impurity diffusion region 2 constitutes the drain region, and the n-channel transistors QNI and Q
This constitutes the source region of N2 or the 1.times.rain region.

Normal LSI 74. , I:, In the aluminum V-body chip, δ basic cell rows in the form of vertically arranged basic cells as shown in Fig. 2 are arranged at 11) intervals, and the circuit is made of aluminum It is formed by applying a wiring consisting of /!7.

Logic section 1 of the basic cell explained with reference to FIGS. 1 and 2 (such as two-man NAND or two-man NOR)
This is effective when creating a /3 jib, but RAM (
random access mem.

ry), l-transmission gate circuit, clocked (clockcd) data 1-circuit (C2MO3 circuit)
When forming a circuit such as the above, there are disadvantages in that a large number of transistors are required and surplus transistors are generated.

For example, to form a RAM cell, four basic cells are required, and six unused transistors are required.
Individuals also arise. Furthermore, when forming a transmission gate circuit, only two can be manufactured using one basic cell. Furthermore, in the case of forming a clocked gate circuit, 2111i1 of the basic cells are required, and half of the transistors included therein are used (2) and become redundant.

OBJECTS OF THE INVENTION The present invention improves the configuration of basic cells for configuring LSIs manufactured by applying the mask slicing method as described above, and converts NAND, which was previously possible, to NOR? In addition to the production of logic circuits such as - It is intended to prevent the formation of transistors and to reduce the occupied area compared to the case of the prior art.

Structure of the Invention The basic cell of the present invention consists of two n-channel transistors sharing a source or drain region.
It has an n-channel 1-transistor region consisting of two n-channel transistors sharing a channel transistor region and a source region or a drain region, and has a p-channel transistor of the above 2 (flit p-channel transistor and
The n-channel transistors are individually associated with each other, and the gates of the n-channel transistors are
In a basic cell in which gates 1 to 1 of transistors are commonly connected, two further n-channel regions are formed outside the n-channel region.
By adopting a configuration in which channel (or n-channel) L-transistors are arranged in parallel and two further n-channel (or n-channel) transistors are arranged in parallel on the outside of the n-channel transistor region, NAND or N which can be effectively formed with conventional basic cells
Not only logic circuits such as OH, but also RAM, transmission gate circuits, clocked gate circuits, etc. can be realized with a small number of basic cells, and also with no surplus transistors, and therefore with a small footprint. obtain.

Embodiment fAS diagram of the invention This is an equivalent circuit diagram of the main part of the invention-embodiment, and is the same 141X minute ε as the part explained with regard to FIGS. 1 and 2.
:1 same symbol is 11↑small j/.

Looking at the figure, (:l I) :i and Q P 4 !
;l Newly added n-channel 1 ~ transistor, QN
3 and QN4, and 1 newly added n-channel I.
Each transistor is shown. In addition, the position number of the l-transistor to be added, n channel, 1-transistor and n
The channel transistors may be reversed from what is shown.

FIG. 4 is a plan view of the main parts showing the iW bulk pattern, which embodies the circuit configuration of the basic cell shown in FIG. 3, and the same parts as those explained in connection with FIG. It is.

In the figure, 5 and 6 are n-type impurity diffusion regions, 7G] and 7G are polycrystalline silicon gate electrodes, 8 and 9 are n-type impurity diffusion regions, and 10G1 and 10G2 are polycrystalline silicon gate electrodes. C is shown respectively. In addition, n
type impurity diffusion region 5 silk p-channel transistor QP3
The p-type impurity diffused region 1i'l region 1μ (6 constitutes each source region or drain region of the n-channel transistor QP4, and the n-type impurity diffused region 8G on-channel
The region 9 in the n-type impurity expansion 11 of the transistor QN3 is n
It constitutes the source region or one Ruin region of each channel transistor QN/I. Furthermore, the third
As discussed with respect to the figures, the positions of n-channel transistors QP3 and QP4 and n-channel transistors QN3 and QN/l may be reversed.

Next, the case where various circuits are constructed using the basic cells explained in connection with FIGS. 3 and 4 will be explained by way of example.

Figure 5 4; I: Key points 74 when configuring a RAM cell
11 is an equivalent circuit diagram, and the same parts as those explained in connection with FIGS. 3 and 4 are designated with the same symbols. Furthermore, RAM
, the channel width of the added transistor is included in the same part as the conventional basic cell structure (it needs to be larger than the channel width of the transistor).

In the figure, INVI and INV2 are inverters, W
RD tl read word line, WW write word line, Di manual data signal, 5〒 inverted input data signal,
Do & O inverted 111 data signals are shown respectively.

Inverters NVI and INV2 in this circuit
+; lp channel I transistor QPI and QP2,
It is composed of n-channel transistors QNI and QN2.

Figure 6 shows a bulk circuit embodying the circuit configuration shown in Figure 5.
5 is a plan view of a main part showing a pattern, and the same parts as those explained in connection with FIG. 5 are indicated by the same symbols.

In the figure, LA is the 1st layer A7+ wiring (thick solid line), LB is the 2nd layer AA wiring (thick broken line), and NA
are the contact part between the AA wiring LA in the first layer and the semiconductor substrate (white circle: ○), and the contact part between the NB&
◎), vDI+ indicates the positive power supply level, and VSS indicates the ground power supply level. Incidentally, according to this embodiment, the area can be reduced to 1/2 in the same process compared to the case where a conventional basic cell is used. As mentioned above, four conventional basic cells are required to construct a RAM cell, and six unused transistors are left.

Figure 7 shows the equivalent circuit of the main parts when the circuit is configured from 1 to Transmission Game 1, and the same parts as those explained in relation to Figures 3 to 6 are designated with the same symbols. .

In the figure, A indicates an input signal, X an output signal, CK a clock signal, and ■ an inverted clock signal.

To configure the transmission gate circuit, each of the n-channel transistors and the n-channel transistors in adjacent basic cell rows are used for 1 (1^1). This configuration is based on the circuit configuration shown in FIG. It can be better understood by looking at Figure 8, which is a plan view of the main part without showing the actualized bulk pattern.In Figure 8, the same parts as those explained with respect to Figures 3 to 7 have the same symbols. This shows lft.

In the figure, BCI is a basic cell belonging to a basic cell column, and BC2 is a basic cell belonging to a basic cell column next to the basic cell column.

As can be seen from the figure, in order to configure the I Transmission Day 1 circuit, the n-channel transistor QN,1 in the basic cell RCI belonging to the basic cell column consisting of Basic cell EC belonging to the basic cell column
It is preferable to use an n-channel J transistor QP3 in No. 2. As seen in this example, when Tochigi cells are adjacent to each other, a transmiscicon gate circuit can be constructed by using a portion of each cell.

FIG. 9 is an equivalent circuit diagram of the main part when a clocked gate circuit is constructed, and the same parts as those explained with reference to FIGS. 3 to 8 are indicated by the same symbols and L squares.

In this case, tJ is constructed using two n-channel transistors and two n-channel transistors 11' in adjacent basic cell rows, and the circuit configuration is shown in FIG. This can be better understood by referring to FIG. 10, which is a plan view of a main part showing a bulk pattern embodying the above. In FIG. 10, the same parts as those explained with reference to FIGS. 3 to 9 are indicated by the same symbols.

As can be seen from the figure, in order to configure the clock F.day 1 circuit, the n-channel transistors QN3 and QN4 in the basic cell BCI belonging to the basic cell string and the basic cell next to the basic cell string are used. Basic cell Bc2 belonging to column
n-channel 1 to Ranjisk QP3 and QP4 in
It can be configured using . Factor Q: 2 circuits are required to construct a clocked data circuit using conventional basic cells, and in terms of area, the basic cell of the present invention requires approximately It can be reduced to 1/2.

In addition to this, it is clear that a 6-year-old can construct a circuit similar to a circuit that can be constructed using conventional basic cells.
In that case, in the present invention, newly added n-channel transistors QP3 and 2 QP/l, n-channel transistors QN3 and QN4
If they are not used, the portion where they are located can be used as a wiring area. In addition, when a plurality of basic cell rows exist, a part of each of the adjacent basic cells is used to create the same circuit as in the case of conventional basic cells, for example, two-man N
It is possible to configure an AND, an inverter, etc.

FIG. 11 is a plan view of the main part showing another embodiment, and FIG.
The same parts as those described with reference to FIGS. 10 to 10 are indicated by the same symbols.

In this example, BCLa is used as the basic cell.

The four basic cells BCI b, BCI c, and BCld are arranged vertically, and among them, the basic cells BCIa and B
C]b+ BClc has two newly added n-channel transistors QP3 and QP4.The only difference is the orientation of the two n-channel transistors QN3 and QN4 from the embodiment described with reference to FIG. It's the same. That is, in the embodiment shown in FIG. 4, each transistor QP3. QP4. QN3. The gate length direction of QN4 is transistor 3. QPI, QP2. QNI and QN2 are arranged in a direction perpendicular to that of QNI and QN2, that is, in a horizontal direction (horizontal direction when viewed from the paper). They are arranged facing in the same direction, that is, in the vertical direction (vertical direction when viewed from the paper). Note that the basic cell BC 1 dB is in the same direction as shown in FIG.

Effects of the Invention The basic cell in the mask-slicing method according to the present invention consists of 21 p-channel transistors sharing a source region or a drain region.
an n-channel transistor region consisting of two n-channel transistors sharing a transistor region and a source region or a drain region;
one n-channel transistor and two n-channel transistors
Each transistor is individually associated with an n-channel
In a basic cell formed by commonly connecting the gate of a transistor and the gate of an n-channel transistor, two further n-channel (or four n-channel) 1-transistors are arranged in parallel outside the n-channel region. In addition, two n-channel (or n-channel) transistors are arranged in parallel outside the n-channel region. That is, in contrast to the conventional basic cell horizontal i-signal, 21 fixed p-channel 1 to transistors and 2 (1? II n
It has a configuration in which a channel transistor is added, and by adopting such a configuration, for example, when configuring a two-man NAND or two-man NOR, it is the same as when using a conventional basic cell. Also, the RAM cell, 1-transmission gate circuit,
When configuring a clocked gate circuit, by using the newly added 4 (1^1) transistors, it is possible to reduce the cost by 1 compared to when configuring it using conventional basic cells.
It becomes possible to form a circuit in an area of /2 to I/3.

[Brief explanation of the drawing]

11th B; l Equivalent circuit diagram of the main part of a conventional basic cell,
FIG. 2 is a plan view of the essential parts showing the bulk pattern of the basic cell shown in FIG. 1, FIG. 3 is an equivalent circuit diagram of the essential parts of the fifth embodiment of the present invention, and FIG. A plan view of the main parts showing the bulk pattern of the basic cell, Figure 5 is the RAM
An equivalent circuit diagram of the main parts when a cell is configured; FIG. 6 is a plan view of the main parts without showing the bulk pattern of the circuit shown in FIG. 5;
Fig. 7 is an equivalent circuit diagram of the main part when a transmission gate circuit is configured, Fig. 8 is a plan view of the main part showing the bulk pattern of the circuit shown in Fig. 7, and Fig. 9 is a clocked gate circuit. Main part equivalent circuit diagram when configured, 1st
0 is a plan view of the main part showing the bulk pattern of the circuit shown in FIG. 9, and FIG. 11 is a plan view of the main part showing the bulk pattern of another embodiment. In the figure, QPI and QP2 are n-channel transistors, QNI and QN2 are n-channel transistors,
1 is an n-type impurity diffusion region; 2 is an n-type impurity diffusion region; 3
GI and 3G2 are polycrystalline silicon gate electrodes, 4CN
is an n-type substrate contact pattern, 4CP is a p-type substrate contact pattern, QP3 and QP4 are n-channel
Transistors QN3 and QN4 are n-channel transistors 6 transistors, 5 and 6 are n-type impurity diffusion regions, 701 and 7
G2 cat polysilicon gate electrodes, 8 and 9 are n-type impurity enriched It (regions, 10G1 and 10G2 are polysilicon gate electrodes, TNVI and INV2
4 inverter, WRD is the read word line, WW is the write word line, Di is the input data signal, Di is the inverted input data signal, ■τ is the inverted output data signal, LA is the first
The Aβ wiring in the first layer, LB is the e wiring to the second layer, NA is the contact part between the first layer A℃ wiring ■, 8 and the semiconductor substrate, and NB is the Aρ wiring LB in the 21st layer. 1st dark eye 7
1 Contact I/part with wiring LA, ■ Wholesale is positive side power supply level, VSS is ground side power supply level, A is input signal, X is output signal, CK is clock signal, 67 is inverted clock signal, B C] A basic cell belonging to a basic cell string consisting of B
C2 is a basic cell belonging to the basic cell column next to the basic cell column to which the basic cell BCI belongs, BCla, BCI b, B
Clc and BCld are basic cells. 7

Claims (1)

[Claims] 21 [1i1 sharing the source region or drain region
An n-channel transistor consisting of an n-channel transistor of
It has an n-channel l-transistor region consisting of two n-channel transistors sharing a transistor region and a source region or a drain region, and the two n-channel transistors and 21 n-channel transistors are each n-channel in association with A111
In a basic cell formed by commonly connecting the gates of an l-channel transistor and an n-channel transistor,
There are also 2 (ll+1 n-channels) outside the channel region.
In a mask slicing method characterized in that one to n-channel transistors are arranged in parallel and two further n-channel (or n-channel) transistors are arranged in parallel outside the n-channel region. Basic cell.