JPS6047440A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the occupying area of an LSI by constituting a fundamental cell by two P channel transistor sections, channels thereof are arranged in one direction, which share a source region or a drain region and gate electrodes thereof are each made independent, and two N channel transistor sections having the same structure and forming the fundamental cells only by fixed numbers. CONSTITUTION:P channel transistors QP1 and QP2 each having independent gate electrodes 3G1 and 3G2 are formed among N type substrate contact regions 4CN, and the regions 4CN positioned among source regions or drain regions are used as common channels. The same applies to N channel transistors QN1 and QN2 and regions 4CP are used as common channels, and gate electrodes 3G3 and 3G4 are formed to each of the N channel transistors QN1 and QN2. Accordingly, fundamental cell rows BL are constituted by the P and N transistors arranged, the cell rows are disposed at several stages, and a 2 input NAND circuit, a 2 input OR circuit, a RAM, a ROM, etc. are constituted easily.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in a semiconductor integrated circuit (LSI) manufactured by applying a mask slicing method.

Prior Art and Problems The above-mentioned mask slicing method is difficult to apply to the bulk part of a transistor, such as a p-well diffusion region, an n-well diffusion region, a gate oxide film, a polycrystalline silicon layer, a selective oxide film, and a channel.
We prepare a wafer in advance in which a stopper, n-type or p-type diffusion region, etc. are created by applying a predetermined pattern (mask), and when the user indicates a specific circuit configuration, we can use it to realize it. This method completes an LSI that meets the needs of a specific user by performing wafer processing after wiring creation using a specific mask pattern designed in advance.

With this method, a specific LSI is created by only processing after wiring creation, so the product can be completed in a shorter period of time compared to a fully custom LSI, and there is no need to create a special pattern (mask) to form the bulk part. There are advantages such as lower manufacturing costs because there are no wires, and fewer errors because the transistor pattern is fixed.

Incidentally, as the integration of LSIs progresses, more and more users are demanding L'SIs that incorporate all the functions of one system on one chip.

In such cases, rather than configuring one chip with only random logic circuits as in the conventional gate array, it is preferable to use RAM (random access
memory) and ROM (read only me
At the same time, it becomes necessary to install a memory circuit such as memory (Mory).

In a conventional so-called CMOS mask slice, the bulk part is made up of random elements, called a gate array.
It is designed to be useful for constructing logic circuits. It is not impossible to incorporate a memory circuit into such a gate array, but in that case,
Only those with significantly reduced integration density can be realized.

Further, a transmission gate circuit, which is often used when a clock synchronization method is used to control logic circuits, cannot be efficiently realized.

FIG. 1 is a plan view of the main part, but does not show the pattern of a general LSI formed by applying the mask slicing method.

As can be seen from the figure, there is a bulk area for the band PD area and the input/output (I10) cell IOC at the periphery of the chip.
Basic cell rows BLI, BL2, etc. are formed by vertically connecting basic cells inside the pattern area.
BLn are arranged at intervals. Note that the area between the basic cell columns becomes a wiring area.

FIG. 2 is a plan view of essential parts showing basic cells forming the basic cell array in FIG. 1 as a specific bulk pattern.

In the figure, 1 is a p-type impurity diffusion region, 2 is an n-type impurity diffusion region, 3G1 and 3G2 are polycrystalline silicon gate electrodes, 4CN is an n-type substrate contact pattern, 4CP
represents a p-type substrate contact pattern, QPI and QP2 represent n-channel transistors, and QNI and QN2 represent n-channel transistors, respectively. Note that the p-type impurity diffusion region 1 constitutes the source region or drain region of the n-channel transistors QPI and QP2, and the n-type impurity diffusion region 2 constitutes the n-channel transistor QPI and the drain region.
This constitutes the source region or drain region of the transistors QNI and QN2. In addition, the n-channel transistor part is formed by n-channel transistors QPI and QP2, and the n-channel transistor part is replaced by n-channel transistors QNI and QN2.
They each constitute an n-channel transistor part.

FIG. 3 is an equivalent circuit diagram of the main part of the basic cell explained in connection with FIG.

In the figure, QPI and QP2 are n-channel transistors, and QNI and QN2 are n-channel transistors, respectively.

Now, in order to configure a circuit using the basic cells described above, a required number of the basic cells arranged vertically in a certain basic cell row are used to form a small-scale circuit called a unit cell, for example, a two-man NAND circuit. , a two-man powered NOR circuit, a flip-flop circuit, etc., and is completed by connecting them by forming two layers of aluminum (A J ) wiring in the wiring area between the basic cell rows. It is.

FIG. 4 is a plan view of essential parts showing a bulk pattern when a circuit combining a two-man NAND circuit and an invert circuit is constructed using two basic cells explained in connection with FIGS. 2 and 3. The same parts as those explained with reference to FIGS. 1 to 3 are indicated by the same symbols.

In the figure, LA is the first layer Aβ wiring, and LB is the second layer A/! The wiring, NA is the contact part between the first layer AI wiring LA and the semiconductor substrate (white circle: 0), and NB is the second layer AI! The contact part between the wiring LB and the 1Nth Aβ wiring LA (double circle: ◎), ■DD is the positive power supply level,
VSS indicates the ground side power supply level.

FIG. 5 is an equivalent circuit diagram of the main part of the circuit shown in FIG. 4.

In the figure, ND is a two-man NAND circuit, INV is an inverter circuit, A1 and A2 are input signals, and X is an output signal.

By the way, the basic cell explained with reference to FIGS. 2 and 3 is effective when creating logic circuits such as two-man NAND or two-man NOR, but it is not suitable for RAM, ROM,) transmission gate circuits, etc. When configuring a circuit, there are disadvantages in that a large number of transistors are required and a large number of redundant transistors are produced.

For example, to form a RAM cell, four basic cells are required, and six unused transistors are required.
Individuals also arise. Furthermore, when forming a transmission gate circuit, since only two sets of the basic cells can be formed, unnecessary transmission gates are often formed, which is wasteful.

Purpose of the Invention The present invention improves the basic cells for configuring LSIs manufactured by applying the above-mentioned mask slicing method, and enables the production of logic circuits such as NAND and NOR, which were previously possible. In order to make it possible to easily configure RAM, ROM, transmission gate circuits, etc. with a small number of basic cells, and to avoid the generation of redundant transistors, the occupied area is reduced compared to the case using conventional technology. The aim is to reduce the

Structure of the Invention The semiconductor integrated circuit of the present invention comprises two n-channel transistors in which channels are arranged in one direction, share a source region or a drain region, and each have an independent gate electrode.・The n-channel transistor is composed of a transistor part and two n-channel transistors that are arranged so that the channels are aligned in the same direction as the one direction, share a source region or a drain region, and each have an independent gate electrode.
The basic configuration includes a basic cell consisting of a transistor part and an n-channel transistor part arranged in parallel, and also includes a plurality of rows of the basic cells arranged in one direction. , and the basic cell has an n-channel transistor part on one side and an n-channel transistor part on one side.
a first type and n in which the transistor part is present on the other side;
A configuration consisting of a second type in which a channel transistor portion is present on one side and an n-channel transistor portion on the other side, and furthermore, a basic cell row in which basic cells of the first type are arranged in one direction. and a basic cell row in which the basic cells of the second type are arranged in one direction are arranged next to each other, thereby making it possible to effectively form a NAND using conventional basic cells. Alternatively, not only logic circuits such as NOH, but also RAM, ROM, transmission gate circuits, etc. can be configured with a small number of basic cells and without surplus transistors, so they can occupy a small amount of space. This can be achieved in terms of area.

Embodiment of the Invention FIG. 6 is a plan view of the main parts of an embodiment of the present invention as a specific bulk pattern, and the same parts as those explained with respect to FIGS. 1 to 5 are indicated by the same symbols. It is.

The difference between this embodiment and the conventional example explained with reference to FIGS. 2 and 3 is that n-channel transistors QPI and Q
P2 and n-channel transistors QNI and QN2 each have independent gate electrodes 3G1.3G2.3G3
, 304. Note that BL indicates a basic cell row.

FIG. 7 is a plan view of the main parts of another embodiment of the present invention as a specific bulk pattern, and the same parts as those explained with reference to FIGS. 1 to 6 are indicated by the same symbols. .

In this embodiment, the basic cells belonging to the basic cell row BLI include an n-channel transistor QP on the left side as viewed from the figure.
I and QP2 are also arranged on the right side, and n-channel transistors QNI and QN2, respectively. Also,
The basic cells belonging to basic cell column BL2 include n-channel transistors QNI and QN2 on the left side of the figure, and n-channel transistors QPI and QP2 on the right side.
are arranged respectively.

The basic cells that belong to this basic cell column BLI are of the first type, and the basic cells that belong to the basic cell column 13L2 are of the second type.

As will be explained later, when a first type basic cell and a second type basic cell, in which the positions of the n-channel transistor part and the n-channel transistor part are simply swapped, are mixed together, an extremely large effect can be obtained. can get.

FIG. 8 is a plan view of the main parts showing the embodiment of the present invention as a specific bulk pattern, and the same parts as those explained with reference to FIGS. 1 to 7 are indicated by the same symbols.

This embodiment is only a slightly shifted representation of the embodiment shown in FIG. appears, and is basically the same as the embodiment shown in FIG.

FIG. 9 is a plan view of essential parts showing the embodiment of the present invention as a specific bulk pattern, and the same parts as those explained with reference to FIGS. 1 to 8 are indicated by the same symbols.

This embodiment is also a broader representation of the embodiment shown in FIG.

Next, cases in which various circuits are constructed using the basic cells described in connection with FIGS. 6 to 9 will be explained by way of example.

FIG. 10 is a plan view of a main part showing a bulk pattern when an 8-transistor part M cell is constructed, and the same parts as those explained with reference to FIGS. 1 to 9 are indicated by the same symbols.

In the figure, QPII, QP12. QP13゜QP14
n-channel transistor, QNII.

QN12. cube3. QN14 is an n-channel transistor, Di is an input data signal, ■Go is an inverted input data signal, ■ is an inverted output data signal, "W" W is a write word line, WRD is a read word line, NT is an external terminal (triangle: △) are shown respectively. Incidentally, the relationship between wiring and contacts in this embodiment is exactly the same as that shown in FIG. 4.

FIG. 11 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 10, and the same parts as those explained in connection with FIGS. 1 to 10 are indicated by the same symbols.

In the figure, INVI and INV2 are inverter circuits.

In the embodiment described with reference to FIGS. 10 and 11,
The n-channel transistor QPII and the n-channel transistor QNII form the inverter circuit INVI, and the n-channel transistor QP12 and the n-channel transistor
The impark circuit INV2 is constituted by the transistor QN12.

As can be seen from the figure, three basic cells are used in this embodiment, but four are required to construct the same structure using the conventional basic cells explained in connection with FIGS. 2 and 3. .

FIG. 12 is a plan view of the main parts showing the bulk pattern when a transmission gate circuit, a two-man powered NAND circuit, and a two-man powered NOR circuit are configured, and the same parts as those explained with respect to FIGS. 1 to 11 are shown. It is indicated by the same symbol.

In the figure, 5 is the transmission gate circuit part, 6 is the two-man powered NANI) circuit part, 7 is the two-man powered NOR circuit part, A is the input signal, X is the output signal, CK is the clock signal, and 100 is the inverted clock. Signals INI and IN2 indicate input signal terminals, and OUT indicates an output signal terminal, respectively.

FIG. 13 is an equivalent circuit diagram of the essential parts of the transmission gate circuit section 5, FIG. 14 is an equivalent circuit diagram of the essential parts of the two-manpower NAND circuit section 6, and FIG. 15 is the two-manpower NOR circuit section 7.
12 is an equivalent circuit diagram of the main parts, and the same parts as those explained in connection with FIG. 12 are indicated by the same symbols.

As can be seen from the figure, it is sufficient to use one basic cell to construct the circuit section 5, whereas two (2) basic cells are required in the conventional basic cell.

Further, the two-man powered NAND circuit section 6 and the two-man powered NOR circuit section 7 can be constructed of one basic cell as in the conventional case.

Now, what we should pay attention to here is the two-man powered NAND circuit part 6.
and a two-manpower NOR circuit section 7.

That is, even though the wiring patterns are exactly the same, different types of circuits can be constructed by distinguishing between the first type basic cell and the second type basic cell.

On the other hand, although polycrystalline silicon is used for the gate electrode in each of the above embodiments, the gate electrode is not limited to this, and for example, high melting point metal silicide or the like may also be used.

Effects of the Invention The semiconductor integrated circuit according to the present invention comprises two p-channel transistors in which channels are arranged in one direction, share a source region or a drain region, and each has an independent gate electrode. channel·
The transistor part is parallel to the p-channel transistor part, and consists of two n-channel transistors whose channels are arranged in one direction, share a source or drain region, and each have an independent gate electrode. Based on the basic structure that includes a basic cell consisting of an n-channel transistor section arranged in about,
RAM, ROM, and transmission gate circuits can also be easily configured with a small number of basic cells. Further, a basic cell column in which basic cells of the first type are arranged and a basic cell column in which the basic cells of the first type are arranged,
By alternately arranging and properly using basic cell rows in which basic cells of the type shown in FIG. Furthermore, when a circuit is constructed, redundant transistors are almost never generated.

[Brief explanation of the drawing]

Fig. 1 is a plan view of the main part of the gate array, Fig. 2 is a plan view of the main part showing the bulk pattern of a conventional basic cell, and Fig. 3 is a plan view of the main part of the gate array.
The figure is an equivalent circuit diagram of the main part of the basic cell shown in Fig. 2, and Fig. 4 is a plan view of the main part showing the bulk pattern when a two-man power NAND circuit and an inverter circuit are constructed using the conventional basic cell. FIG. 5 is an equivalent circuit diagram of the main part of the circuit shown in FIG. 4, FIG. 6 is a plan view of the main part showing the bulk pattern of the basic cell in the present invention, and FIG. 7 is another embodiment of the present invention. FIGS. 8 and 9 are plan views of essential parts showing the bulk pattern in the example, FIGS. 8 and 9 are plan views of essential parts showing the bulk pattern of an embodiment similar to the embodiment shown in FIG. RAM
11 is an equivalent circuit diagram of the main part of the embodiment shown in FIG. 10, and FIG. 12 is a transmission gate circuit, a two-man powered NAND circuit, and a two-man powered NAND circuit. FIGS. 13, 14, and 15 are plan views of essential parts showing bulk patterns when a NOR circuit is configured, and are equivalent circuit diagrams of essential parts of the embodiment shown in FIG. 12. In the figure, BL, BLI, BL2...BLn are basic cell rows, Q, PL and QP2 are p-channel transistors, QNI and QN2 are n-channel transistors,
1 is an n-type impurity diffusion region, 2 is an n-type impurity diffusion region, 3
G1.3G2.3G3゜3G4 is a polycrystalline silicon gate electrode, 4CN is an n-type substrate contact region, and 4CP is a p-type substrate contact region.
Type board 22 contact area, LA is the first layer A (wiring,
L13 is the second layer Aβ wiring, NA is the first layer A7
! The contact part between the wiring LA and the semiconductor substrate (white circle 20), NB is the contact part between the second layer AN wiring LB and the first layer Aβ wiring LA (double circle: ◎), ■DD is the positive side power level, VSS is ground side power level, ND is 2-person NAND circuit, INV is inverter circuit, A1 and A
2 is an input signal, X is an output signal, QPI 1. QPI2.
QPI3. QPI4 is an n-channel transistor, QN
I 1 , QNI 2', QNI3. QNI4 is n
channel transistor, Di is the input data signal, Di
is an inverted input data signal, Do is an inverted output data signal, W
W is a write word line, WRD is a read signal, NT is an external terminal (triangle: △), INVI and IN V-2 are inverter circuits, 5 is a transmission gate circuit, 6 is a two-man NAND circuit part, 7 is a 2 In the human-powered NOR circuit part, A is a human-powered signal, X is an output signal, CK is a clock signal, τY is an inverted clock signal, INI and IN2 are input signal terminals, and OUT is an output signal terminal. Patent Applicant Fujitsu Co., Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Figure 1 Figure 2 Figure 3 × Figure 5 Figure 6 Date 1 ===] Figure 7 Unexamined Patent Application Showa eo-4744tt (8-194- Fig. 13 Fig. 14 Fig. 15

Claims (4)

[Claims] (1) An n-channel transistor portion consisting of two n-channel transistors in which the channels are arranged in one direction, share a source region or drain region, and each has an independent gate electrode; consisting of two n-channel transistors arranged in the same direction as the one direction, sharing a source region or a drain region, and each having an independent gate electrode, parallel to the n-channel transistor portion. 1. A semiconductor integrated circuit comprising a basic cell consisting of an n-channel transistor portion arranged therein. (2) The semiconductor integrated circuit according to claim 1, characterized in that the semiconductor integrated circuit includes a plurality of columns in which the basic cells are arranged in one direction. (3) said basic cell is of a first type with an n-channel transistor portion on one side and an n-channel transistor portion on the other side; and an n-channel transistor portion on one side and an n-channel transistor portion 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is of a second type in which the semiconductor integrated circuit is present on the other side. (4) A basic cell row in which the first type of basic cells are arranged in one direction and a basic cell row in which the second type of basic cells are arranged in the same direction as the one direction are arranged adjacent to each other. A semiconductor integrated circuit according to claim 3, characterized in that the semiconductor integrated circuit is formed by: