JPS5944859A - Basic cell - Google Patents

Abstract

PURPOSE:To reduce the restriction of the size of systems by the size of master chips by a method wherein the group of transistors is so formed as to become symmetric left and right with the line crossing over the source region, gate electrode and drain region as the center. CONSTITUTION:P-channel MOS type transistors 141 and 142 form the group of transistors becoming symmetric left and right with the line A crossing over the source region, gate electrode and drain region as the center. N-channel MOS type transistors 161 and 162 form the group of transistors becoming symmetric left and right with the line B crossing the source region, gate region and drain region. The first basic cell composed of the transistors 141 and 142 and the second basic cell composed of the transistors 161 and 162 are successively disposed in arrays respectively in the direction of rows.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a basic cell constituting a master-slice type semiconductor device having a dirt array.

[Technical background of the invention and its problems]

2. Description of the Related Art Conventionally, as a master slice type semiconductor device having a dirt array, the one shown in FIG. 1 is known.

1 in the figure is a master chip. On this master chip 1, basic cell columns 2 for counting as a Logic creation section are arranged in rows and squares narrowing the wiring area 3 that forms the connection wiring between the basic cell columns 2.2. horizontal direction). As shown in FIG. 2(a), this basic cell row 2 consists of a first transistor pair consisting of a P-channel MO8 type transistor 41p4m and a second transistor pair consisting of an N-channel MO8 type transistor 51p52. The basic cells 6 are arranged in negative columns in the column direction (vertical direction).

In Fig. 2(a) and (b), 7 indicates the first layer Al wiring, and 81 p82 t83 indicates the second layer A.
9 is the contact of the first layer M wiring 7, 10 is the l wiring,
are the first layer An wiring 7 and the second layer Al wiring 81 $8
The dirt electrodes made of polycrystalline silicon of each of the transistors in the first and second transistor pairs are common. The basic cell 6 constitutes a two-man NAND circuit as shown in FIG. 2(b), for example.

However, the semiconductor device having the above-mentioned structure has the following drawbacks.

■ In the basic cell 6, a first transistor pair consisting of P channel MO8 type transistors 41y42 and an N
Channel MO8 type transistors 51, 5 . A second transistor pair consisting of the following transistors is a pair. therefore,
Logic Qate such as NOR and NAND is the basic cell 6...
It can be configured only within the basic cell rows 2 consisting of the following, and requires a wiring area 3 for connection between each basic cell row 2.

However, the number of wiring channels in this wiring region 3 is determined taking into account the need for a large number of wiring lines, and therefore generally requires a large area. For these reasons, if a product is developed from the state of the semiconductor device shown in FIG. 1, there will be a lot of wasted area in the wiring area 3 that is not actually used.

(2) Since the numbers of basic cell rows 2, . . . and basic cells 6, etc. in the basic cell row 2 are determined in advance, a system that cannot be physically realized may occur. In addition, in order to solve this problem, it is possible to increase the number of basic cells 6 by enlarging the area of the mass border lag 1, but in this case, between the basic cell rows 2 consisting of basic cells 6... There is a drawback that the area of the wiring region 3 also increases, and the master chip 1 becomes significantly larger than that shown in FIG.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to provide a larger number of basic cells on the master chip than before without increasing the size of the master chip, and to increase the size of the system that can be realized. It is an object of the present invention to provide a basic cell constituting a master-slice type semiconductor device in which the size of the master chip is minimized.

[Summary of the invention]

Currently, we are developing products for dirt alley.
For the master chip and Logic (such as NAND and NδR) determined by this master chip
Library) is available. However, when using a conventional basic cell, Libra is always placed on the left side of the basic cell and the N channel on the right side.
There is only one way to use y. Therefore, the inventor of the present invention
In a basic cell constituting a slice-type semiconductor device, a first conductivity type transistor group and a second conductivity type transistor group are formed whose dirt electrodes are separated from each other, and each transistor group is connected to a source region, a dirt electrode and a second conductivity type transistor group. By creating a structure that is symmetrical with respect to a line that crosses the drain region, it is possible to use the transistor group of the first conductivity type and the transistor group of the second conductivity type on either the left or right side (for example, on the left or right side). In the opposite case, Library data
), P channel,
The wiring area is varied by the W pitch of a conventional basic cell having N channels, and the basic cell row that becomes the Log1c generation section is also made variable, in order to minimize the possibility of determining a system that can be realized by master design. planned.

[Embodiments of the invention]

A case in which the basic cell of the present invention is applied to a master slice type semiconductor device will be described with reference to FIG.

11 in the figure is a master chip. A portion of the periphery of this master chip contains Logic (Logic Qate).
) The first basic cell rows 131 . . . and the second basic cell rows 132 .

As shown in FIG. 4(a), the first basic cell row 131 is a P-channel MO8 type transistor that forms a group of transistors that are symmetrical about a line A that crosses the source region, dirt electrode, and drain region. Transistors 141, . 14
A first basic cell 15 consisting of 2. ... are sequentially arranged in parallel in the column direction (vertical direction). In addition, the second basic cell row 132 includes N-channel MO transistors forming transistor pairs that are symmetrical about a line B that crosses the source region, dirt electrode, and drain region, as shown in FIG. 5(b).
A second basic cell 152 consisting of 8-type transistors 161 and 162 is sequentially arranged in parallel in the column direction (vertical direction). Note that the P-channel MO8 type transistor 14
A transistor group consisting of 1,142 transistors and an N-channel M
The respective dirt electrodes of the transistor group consisting of O8 type transistors 161 and 162 are separated. Also, the X-th first basic cell column 1 from the left of the master chip 1
The same number of basic cells 151 and 152 from the top of the master chip 1 in the 3x y (x+1)th (number, X is a natural number) second basic cell column 13□ form a pair to form a basic cell pair. are doing.

According to the semiconductor device having the above-described structure, the first part is located in the area other than the peripheral part of the master chip 11 having the same area as the conventional one.
A plurality of basic cell pairs consisting of the basic cell 131 and the second basic cell 1.92 are formed without exception, and the logic gate can be easily created by combining the first and second basic cell columns 131 and 1.92. , there is a logic gate in the wiring area.
All areas other than the creation unit 12 can be used and the wiring area can be used for the first and second basic cell rows J, 91.1, ? 2
It can be made variable by any one of the following. Therefore, a much higher degree of element integration can be obtained than in the past, and it is possible to further reduce the fact that the size of the system that can be realized is determined by the size of the master chip. Based on the same idea, there is no need to increase the size of the master chip to accommodate the size of the system, as was the case in the past.

Note that the semiconductor device to which the basic cell of the present invention is applied is not limited to the one shown in FIG. 3, but may have the structure shown in FIG. 5, for example. That is, in this semiconductor device, a first basic cell row 171 has a P-channel MO8 transistor pair (first basic cell) lax and an N-channel MO8 transistor pair (second basic cell) 182 in a row. The second basic cell row 172 adjacent to the first basic cell row 171 is the second basic cell 182.
and the first basic cell 17. The structure is such that they are arranged in order in the column direction. A semiconductor device having such a structure can also be expected to have the same effects as the one shown in FIG.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to provide a basic cell in which the size of the system that can be realized by increasing the integration of elements is reduced from being limited by the size of the master chip. be.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a conventional semiconductor device, FIG. 2 (&) is a plan view of basic cells constituting the basic cell array of the semiconductor device shown in FIG. 1, and FIG. FIG. 3 is a plan view of a semiconductor device provided with basic cells of the present invention in a master chain and fK, and FIG. A plan view of a channel MO8-type transistor group (first basic cell); FIG. plan view of
FIG. 5 is a plan view of a semiconductor device showing another embodiment of the present invention. 1 No... Master chip, 12... Logic creation section, 13□ w132 e171 1172... Basic cell row, 141 v 142 p 1612162
...MO8 type transistor, 151. 152. 1
81. 182...Basic cell. Applicant's agent Patent attorney Suzue Takehiko No. 11g1 3 Figure 2 (a) Voo GND No. 3
Figure 4 Figure 5m 256-

Claims (1)

[Claims] A basic cell constituting a master slice type semiconductor device having a gate array is formed of a first conductivity type transistor group and a second conductivity type MOS transistor group, each having a dart electrode separated from the other. A basic cell characterized in that a group of transistors has a shape that is symmetrical about a line that crosses a base region, a dirt electrode, and a drain region.