JPS58139445A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the integration of a semiconductor integrated circuit device of master slice type by providing connecting holes on X and Y lattices which are specified by the integer times of the prescribed coordinate interval and forming connecting layers except power source wirings only on the lattices in an element region. CONSTITUTION:Connecting holes 6 for mutually connecting P<+> type and N<+> type source and drain layers 3, 4 and polysilicon gates 5a, 5b as well as an Al film (power source wirings 7a, 7b and the like) are formed in X lattices 100a- 100c and Y lattices 200a-200s on an N type Si substrate to form fundamental cells of the conventional type to be used to form various function circuits. Since lattices 200b, d, e, g, i, k, m, o, p, r are however unnecessary, they are deleted, and when the fundamental cells are formed only with the 200a-i, the integration of the element can be increased to approx. twice, or similar effect can be obtained by the Y lattices 200a-j, the function circuits can be performed in sufficiently small area with the Y lattices and X lattices 100a-d, thereby obtaining a master slice type LSI of high integration.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a highly integrated circuit device, particularly a master slice type integrated circuit device.

In recent years, the master slice type L8I has been used in communication devices and combinations, and has contributed to reducing development costs and opening times. These master slice L8
I is, for example, the coordinate interval (X
The connection positions are described by a grid arranged on a pitch (referred to as a pitch and a y-pitch) (usually the pitch and grid are the same), and this is used to create a mask when integrated into an IC.

An example of this is shown in Figure 1! Star slice method L8I
In this figure, the chip lO has a human output buffer part 11. Basic cell 13 consists of wiring areas 12a, 12b, and 12c between the basic cells and between the input/output section and the basic cells.

FIG. 2 shows an example of the basic cell 13 used in FIG.
As shown in this figure, each P layer 2 formed on an N type silicon substrate 1+ has a P source drain layer 3, an N source drain layer 4, a gate polysilicon layer 5b, and a contact layer 6 on these connections. , Al (= VDD @ 7m of the rim conductive exhibition.

■Consists of 88 7b etc. 1 normal wiring area 8m, 8b8C
In K, there is an Al<=Rim conductive lattice.

Figure BE (b) is an example of a floor plan in which the basic cells in Figure 2 are refocused on grids;
An example of the circuit result is shown.

+ + P source drain layer 3. N source drain layer 4 gate polysilicon layer 5, contact hole 6 for interconnection such as 5b, and aluminum conductor for this connection are
Lattice 100F-100C.

Located on the y grid 200F~200$, various functional elements,
For example, a two-man NAND circuit, exclusive OR
Used to create circuits, etc.

+ + Here, the P source/drain layer 3. N source drain connection 4,
The gate polysilicon layer 5 serves as a layer for active devices such as P-channel MO&) transistors and N-channel transistors, and is also used as a conductive layer for interconnecting the active devices.

However, these conductive layers have a high resistance value and deteriorate electrical characteristics, so a low-resistance conductive layer such as an aluminum conductive film is mostly used for interconnecting active elements.

Early! The star slice method L8I used to have only one aluminum conductive layer, but recently two aluminum conductive layers have been used.
Layers began to be used.

FIG. 4 shows the state of the wiring in the wiring area 12 of FIG. 1. 11ii1 aluminum wiring 40aze on the X lattice and y lattice, the amount of aluminum in the second layer, i! ! 41
a-e are formed, and a contact hole 42 (usually made of an aluminum conductive film is called a through hole) is provided to establish an electrical connection between the two.

By the way, in #I3 diagram (1), the y lattice 200b.

200d, 200e, 200L 2004.200,
200m.

200o, 200p, 200r and the wiring area in FIG.
12a to 12c may be omitted without any problem depending on the target circuit. However, the contact hole arrangement shape, basic cell shape, and overall arrangement shape were determined depending on the number of wiring grids required for wiring. Therefore, in the conventional arrangement method, the occupation rate of the wiring in the wiring area on the circuit connection is extremely poor, which equivalently lowers the degree of integration of the elements.

The object of the present invention is to provide a structure that eliminates such a wiring area that is rarely used and increases the overall degree of integration of elements.

The present invention provides active elements and an active element formation layer regularly arranged within a defined element region on a silicon substrate, a conductive layer for interconnection for interconnecting the active elements, and an active element formation layer on the active element formation layer. In the i-star slice method, which has contact holes for electrically connecting with the conductive layer for connection via an insulator 1-, the contact holes are defined by an integer multiple of a determined coordinate interval, and an X lattice and a y lattice. FIG. FIG. 3 shows a detailed plan view in which the basic cell lattice of the present invention has been rewritten with emphasis on the lattice.

For the conventional basic cells shown in FIGS. 2 and 3, the unnecessary grid 200 be da ee gy 1 e k
e mto + pt' is deleted, and a basic cell is created using only the y-lattice 200a-i as shown in FIG. .

FIG. 6 shows an example of another basic cell of the present invention. In this example, as shown in FIG. 5(b), y grids 200a to 200j
The same effect 4r as in the case of (turn) in FIG. 5 can be obtained.

That is, as seen in FIG. 5, the basic cell 13 of FIG.
In the element region of the set PF...F, the y lattice 200 m-1 (in the case of (Jl)) or 200 a to j (
(b) case) and the X grid 100 determined for each basic cell 13
A functional circuit is completely realized by a to d, and this functional circuit can be realized within a sufficiently small area.

FIG. 7 shows an overall view of the basic cells shown in FIG. 5 arranged in a different manner from the method shown in FIG. 1.

In this case, the entire internal area is also considered as an element area, and for example, the wiring of a memory circuit, etc. is
00a-j repeats, the X lattice is made completely on top of the lattice made with 100a-d repeats. That is,
If it is one in the center of the basic cell, it is the first of the 51st N(a).
To the right of the basic cell 100d is a second basic cell 100a.
, 100a, the third basic cell 100d, 200
Above a, there is a fourth basic cell 2004. Below 200i, there is a fifth basic cell 200a, and all the conductive layers for connection except for power supply conductive m7m and 7b are present. Exists on a grid of contact holes.

In the present invention, the power supply conductive film 78.7b is the same layer as the aluminum conductive layer in the X direction (distribution @ 40 a''-C in FIG. 4), but It may be possible to use the same layer as the arrangement 141aza) in Figure 4.Furthermore, the wiring layer may have a three-layer structure instead of a two-layer structure, and the power lines 'Is, 'Ib
etc. as the third layer, and as shown in Figure 5 (in aJ, the
In the case of 200g (FIG. 5(b)), the X-grids 200c and 200h can be omitted, and all conductive layers for connection, including power lines, can be formed on the lattice defined by the contact holes.

The present invention not only replaces P and N as shown in FIG. Of course, it can be applied to methods as well.

As described above, according to the present invention, the effective number of gates is large for the same chip area, or the chip area is small for the same number of gates, and the master slice type LSI has a high degree of integration.
The advantages are great.

[Brief explanation of the drawing]

Figure 1 is an overall diagram of the conventional master slice method L8I.
Fig. 2 is an example of a plan view of the first basic cell, Fig. 3 is an isometric view showing the state of the lattice of a conventional basic cell, and Fig. 4 is a diagram showing the state of wiring in the wiring area. The figure is an isometric view showing the state of the basic cell lattice of the master slice type LSI of the present invention, FIG. 6 is a plan view showing the second basic cell, and FIG. 7 is a plan view showing another basic cell of the present invention. FIG. 3 is an overall diagram showing an arrangement method. In the figure, 1... old... N type silicon substrate, 2+ P fer, 3... P drain layer, 4...
...r source fin 4th layer, 5...gate polysilicon layer 6...contact hole, 7...
Aluminum conductive film, 8... Wiring area, 10.
...Chip, 11...Part of the traffic buffer, 12...Wiring area, 13...Basic ten cells, 3'... P sub-contact layer, 4'・
...N sub-contact layer, 100...X
Grid, 200...y grid Figure 5 4m

Claims (1)

[Claims] On the first conductive lid silicon substrate, active elements and an active element formation layer are regularly arranged in a defined element region, a conductive layer for connection for interconnecting the active elements, and an active element formation layer. In the master slicing method, contact holes are provided for electrically connecting with the conductive layer for connection via an insulating layer on the 1. A semiconductor integrated circuit device characterized in that, at least in the scissor element region, a conductive layer for embroidery excluding a conductive layer for a power supply line is formed only on the grid defined by the contact hole.