JPH02280353A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce parasitic resistance and cell area by forming power source and grounding wirings out of upper wirings, and forming the signal lines consisting of upper wirings on the grids whose principle axes are in the same direction, and forming through holes on the grids and contacts between grids. CONSTITUTION:The second layer power source wiring VDD and the second layer grounding wiring GND2, which are arranged in horizontal direction and in parallel with each other and are made by upper layer wirings, and the second layer Al wirings B1, B2, and B3, respectively, via through-holes T1, T2, and T3 on grids H2, H3, and H6, whose principle axes are in the same direction as these, are formed. With that, this is equipped with the first layer Al wirings A1, A2, and A3, which are formed through contacts C1...C9 being arranged between grids in the vertical direction to the wirings VDD2 and GND2, an a polycrystalline Si layer G. The intercell wiring and the in-cell element can be connected directly not through a polycrystalline Si layer, and parasitic resistance can be reduced, and cells can also be formed under power source and grounding wirings, so the cell area can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applied to polycell type semiconductor integrated circuits, and in particular improves a block layout method for a multilayer metal wiring process suitable for automatic layout design using an electronic computer. The present invention relates to a polycell type semiconductor integrated circuit.

〔overview〕

The present invention provides a polycell type semiconductor integrated circuit that includes power and ground wiring formed by upper layer wiring, upper layer signal wiring formed on a lattice whose main axis is in the same direction as the power and ground wiring, and upper layer signal wiring formed on the lattice. By providing a through hole formed in the lattice to connect the upper layer wiring and the lower layer wiring, and a contact formed between the lattices and connecting the cell to the lower layer wiring, the cell area can be reduced and the characteristics can be improved by reducing parasitic resistance. The aim is to

[Conventional technology]

2. Description of the Related Art In recent years, automatic layout design of semiconductor integrated circuits using electronic computers has become more and more popular due to the increase in the degree of integration of semiconductor integrated circuits and the adoption of multilayer metal wiring processes. To do this, a method is used in which the layout is divided into several blocks (cells), and these blocks are treated as one box, and the layout is performed on the chip and the wiring between the blocks is performed.

As this block, a cell is often used in which a power supply line and a ground line are formed in parallel, and a block pattern is formed therebetween. This is called polycell. In a narrow sense, a polycell is a state in which the cell is formed only between the power supply and ground wiring, and the intercell wiring is formed outside the power supply and ground wiring.
In a broad sense, the power supply and ground wirings may simply be formed in parallel, and the cell pattern may be formed on the outside (hereinafter, polycell will be referred to in a broad sense). Note that in a narrow sense, a standard cell library is one in which many polycells are created in advance and used repeatedly for many types of products.

The third example of polycell using conventional multilayer metal wiring process
4, and its circuit diagram is shown in FIG. 4 and FIG. 5, respectively. Here, complementary MO3 (C
This is a MO3) inverter circuit using a two-layer aluminum wiring process.

In the conventional polycell, the -layer power wiring (VDD, ) and the -layer ground wiring (GND+) are formed by the first layer aluminum wiring, and the inter-cell wiring is formed by the second layer aluminum wiring B.
1 and B2. At this time, the polycrystalline silicon layer G2 is drawn out to the outside of the power supply and ground wiring, and connected to the second layer aluminum wiring via the first layer aluminum wiring A1 outside the cell. Second layer aluminum wiring B
1 and B2 are mainly formed in the vertical direction (perpendicular to the power supply and ground wiring) (the main axis is said to be in the vertical direction), and their X coordinates can only take a predetermined value.

These are called vertical lattices V1 to V5. Similarly, outside the cell, the main axis of the first layer aluminum wiring is in the horizontal direction and is formed on a horizontal grid. The height of the block is 100
~150 μm1 and a width of about 30 to 200 mm.

Note that the second layer aluminum wiring may be used not only for inter-cell wiring but also for intra-cell wiring, or may be partially formed in the horizontal direction.

In general, the connecting parts between the first layer aluminum wiring, the diffusion layer, and the polycrystalline silicon layer are connected to each other (01 in the figure).
~Cl2) and the connecting portion between the first layer aluminum wiring and the second layer aluminum wiring through the through hole (in the figure, T
1 and T2).

Through holes and contacts cannot be formed overlapping each other.

In addition, the second layer aluminum wiring cannot be directly connected to the diffusion layer and the polycrystalline silicon layer (the second layer aluminum wiring is connected to the first layer aluminum wiring through a contact).

In FIG. 3, B1 and B2 are inter-block wirings made of second-layer aluminum wiring, and the polycrystalline silicon layer is used to connect the gates of transistors and other inter-block wirings.

In addition, in FIG. 4, 1 is a P-type silicon substrate, 2 is an N
Type well (NW), 3 is P type source/drain region (
P) 4 is the -th layer power supply wiring (VDD+), 5 is the polycrystalline silicon layer (Ga)) G, and 6 is the first layer aluminum wiring (A
l), 7 is the second layer aluminum wiring (Bl), and 8
is an insulating layer.

[Problem that the invention seeks to solve]

The conventional polycell type semiconductor integrated circuit described above has the following problems.

■ The film thickness of the first layer aluminum wiring is usually about 1/2 that of the second layer aluminum wiring, so there are problems with electromigration and potential drop (power supply wiring) or potential increase (ground wiring). It needs to be thicker. However, since the layer resistance of the diffusion layer is high, it is no longer possible to form a transistor under the power supply and ground wiring, resulting in an increase in cell area.

■ Parasitic resistance occurs because a polycrystalline silicon layer is used for connection to inter-cell wiring. Therefore, the characteristics deteriorate.

The purpose of the present invention is to solve the above-mentioned problems.
It is an object of the present invention to provide a polycell type semiconductor integrated circuit with a reduced cell area and reduced parasitic resistance.

[Means for solving problems]

The present invention provides a polycell type semiconductor integrated circuit comprising power supply and ground wiring arranged in parallel to each other, a plurality of cells forming a block pattern, and multilayer wiring.
the power supply and ground wiring formed by upper layer wiring;
Upper layer signal wiring formed on a lattice whose main axis is in the same direction as the power supply and ground wiring, through holes formed on the lattice and connecting the upper layer wiring and lower layer wiring, and through holes formed between the lattice and the lower layer wiring. It is characterized by comprising a contact that connects the wiring and the cell.

[Effect]

The power supply and ground wirings are formed as upper layer wirings, and the upper layer signal wirings formed by other upper layer wirings are also formed on a lattice with the main axis in the same direction as the power supply and ground wirings.

Then, through holes are formed on the lattice and contacts are formed between the lattices.

Therefore, through holes and contacts do not overlap, and intercell wiring and cell internal elements can be directly connected without using a polycrystalline silicon layer, reducing parasitic resistance.
It is possible to improve the characteristics. Furthermore, cells can be formed under the power supply and ground wirings, and the cell area can be reduced.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a top view showing the first embodiment of the present invention, and FIG.
This is a patterned version of the CMO3 circuit shown in the figure, and corresponds to the conventional example shown in FIG. Note that the pattern of the N-type well is omitted.

In the present embodiment, a second layer power supply wiring VDD2 and a second cylindrical ground wiring GND2, which are arranged parallel to each other in the horizontal direction and are formed by upper layer wiring, and a second layer power supply wiring VDD2 and a second cylindrical ground wiring GND2, Second-layer aluminum wiring B1, B2, and B3 formed through through-holes Tl, T2, and T3, respectively, on grids H2, H3, and H6 whose main axes are in the same direction as the layer ground wiring GND, and the second-layer power supply. The first layer aluminum wirings A1, A2, and A are formed via the wiring VDD and the second layer ground wiring GND, and contacts (contacts) C1 to C9 arranged in the interstitial space in the vertical direction.
3 and a polycrystalline silicon layer G. In addition, the -
The layer aluminum wiring A3 is also connected to the second cylindrical ground wiring GND2 via a through hole T4. In addition, in FIG. 1, N is an N-channel MOS transistor,
and P is a P-channel MOS transistor.

A feature of the present invention is that the power wiring, ground wiring, and inter-block signal wiring are arranged as shown in FIG. 1.

According to this embodiment, the contacts are formed between horizontal grids, so they do not overlap with through holes. In this way, the inter-cell wiring and the internal elements of the cell can be directly connected without using polycrystalline silicon, thereby reducing parasitic resistance.

FIG. 2 is a top view showing a second embodiment of the present invention. In the second embodiment, cells are formed below and outside the power supply wiring and ground wiring, and the N-type well pattern is omitted.

In the second embodiment, the horizontal direction is the main axis H1 to H1l,
The second layer power wiring VDD2 and the second cylindrical ground wiring GND2 formed parallel to each other in the main axis direction, and the main axis H2
a second layer aluminum wiring B1 formed on a lattice of;
Second layer aluminum interconnects B2 and B3 formed on the main axis H6 and HIO lattice via through holes T2J and T4, respectively, and a first layer aluminum formed via contacts C1 to C21 arranged between the lattices. It includes wirings A1 to A4 and a polycrystalline silicon layer G.

The P-channel MO3) transistor P is also provided under the second layer power supply wiring VDD2, and the N-channel MO
3) The transistor N is also provided under the second cylindrical ground wiring GND2, the second layer power supply wiring VDD2 and the -th layer aluminum wiring A1 are connected through the through hole T1, and the second cylindrical ground wiring GND2 and It is connected to the -th layer aluminum wiring A4 through a through hole T3.

The feature of the present invention is that power supply and ground wiring and inter-block signal wiring are arranged as shown in FIG. 2.

In the second embodiment, since the MOS transistor is formed below and outside the power supply and ground wiring, there is an advantage that the cell area can be made smaller compared to the first embodiment shown in FIG.

〔Effect of the invention〕

As explained above, the present invention forms power supply and ground wiring with upper layer wiring, forms signal lines with upper layer wiring on a lattice whose main axis is in the same direction as those lines, through holes are formed on the lattice, and contacts are formed on the lattice. Forming between lattices has the effect of reducing the width of the power supply and ground wiring, reducing the cell area by forming elements under or outside the wiring, and improving characteristics by reducing parasitic resistance.

FIG. 4 is a schematic sectional view taken along the line x-x'.

Figure 5 is a CMOS inverter circuit diagram.

DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2, NW... N-type well, 3... P-type source/drain region, 4, VDD, .
. . . -th layer power supply wiring, 5, G5G1, G2 . . . polycrystalline silicon layer, 6, A1-A4 . . . first aluminum wiring, 7, B1-B5 .
...Insulating layer, C1-C21...Contact, GND
.

...Second layer ground wiring, GND 2...Second layer ground wiring, Hl-Hlt...Horizontal lattice, N...N channel MOS transistor, P...P channel MO
3) Transistor, T1-T4...Through hole, VD
D2...Second layer power wiring, ■1-V5...Vertical grid.

[Brief explanation of drawings]

FIG. 1 is a top view showing a first embodiment of the present invention. FIG. 2 is a top view showing a second embodiment of the present invention. FIG. 3 is a top view showing a conventional example. Shoulder - Actual measurement example (upper rM: U diagram) Tail 1 time Ujinii 1st example (Yomen (12)) shoulder 2 times Yota example (two views) Shoulder 3 times Promotion east side (Seri - Figure X-X revised drawing) figure times

Claims (1)

[Claims] 1. In a polycell type semiconductor integrated circuit comprising power supply and ground wiring arranged in parallel to each other, a plurality of cells forming a block pattern, and multilayer wiring, an upper layer signal wire formed on a lattice whose main axis is in the same direction as the power supply and ground wire; a through hole formed on the lattice and connecting the upper layer wiring and the lower layer wiring; A semiconductor integrated circuit 0 characterized by comprising a contact formed between the lattices and connecting the lower wiring and the cell.