JP4334891B2 - Connectable transistor cell structure - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a connectable transistor cell structure having a drain region, a gate region, a source region, and a substrate contact region for stabilizing the operation of a transistor and arranged in parallel to constitute a semiconductor integrated circuit. . More specifically, the present invention relates to the connection design of transistor cell layouts, such as connection of substrate contact regions when connecting transistor cells.
[0002]
[Prior art]
Today, as the life cycle of systems and sets has shrunk, the design period given to IC (Integrated Circuit) design is one step in shortening, and in order to protect time to market An efficient design method is needed from time to time.
[0003]
However, more flexible layout techniques are required for designs that cannot be automated, such as special analog circuit layout designs.
[0004]
Each design flow related to the layout design of the conventional analog circuit mainly includes the following four stages.
(1) Cell generation stage: A cell design is determined based on connection information such as a net list and device parameters.
(2) Cell placement stage: Cells are optimally placed in consideration of wiring efficiency and wiring length.
(3) Inter-cell wiring stage: Wiring is performed between cells in accordance with various wiring restrictions.
(4) Cell optimization stage: The layout design is verified and a final rule check is performed.
[0005]
When forming a transistor cell according to the above design flow, it is possible to eliminate the wiring between cells as much as possible, and to use a structure that can prevent a design rule violation in advance, greatly shortens the design period and is efficient. It is an important key for realizing a smooth design flow.
[0006]
In the conventional transistor cell layout design, first, the transistor channel width is divided in parallel into the smallest units at the cell stage to form a transistor cell having a desired number of fingers.
[0007]
Specifically, the N-channel MOS transistor M1 shown in FIG. 27 is divided into the smallest divisions so that the channel width W (= α) becomes a desired number of fingers. For example, in the case of 8 fingers having 8 gate (G1) wirings, as shown in FIG. 28, the channel width is divided in parallel into the minimum unit Wmin = α / 8.
[0008]
A transistor cell is a circuit component having a pre-set function so that it can be repeatedly used as a component of a chip when designing a layout of a large number of the N-channel MOS transistors M1. The transistor cells are continuously arranged so as to have a size required for design.
[0009]
A conventional typical transistor cell will be specifically described below with reference to FIGS.
(Transistor layout sample (1))
For example, in the first N-channel MOS transistor cell 100, as shown in FIG. 29, a second substrate (P-substrate 2) 101a is formed on a first substrate (P-substrate) 101 made of a P-type semiconductor. For this purpose, a box-shaped substrate isolation region is formed by the deep N-well 107a of the process option for forming the bottom surface and the N-well 107b for forming the side surface, and further, a power supply potential is applied to the N-well 107b, thereby generating noise from the outside. Shut off. Two N-type diffusion regions (n +) 102 and 102 for forming a drain region and a source region are provided on the second substrate, and the region of the P-type semiconductor (P-substrate 2) 101a therebetween is insulated. A transistor block (Sensitive Circuit) 104 having a structure covered with an oxide as a body and a gate wiring (G1) made of a polysilicon wiring as a conductor (metal) is provided. The three structures of metal (Metal), oxide (Oxide), and semiconductor (Semiconductor) are called MOS structures. In the figure, the gate wiring (G1) forms a gate region and a gate terminal.
[0010]
As shown in FIG. 30, a substrate contact region 103 made of a P-type diffusion region is formed around the transistor block (Sensitive Circuit) 104. The substrate contact region 103 includes contacts 103a and 103a. A constant voltage (0 V in this case) is applied through the first layer metal 103b.
[0011]
The substrate contact region 103 is arranged as many as possible in an empty space, and the operation of the transistor is further stabilized by supplying a substrate potential.
[0012]
The substrate contact regions 103 are arranged together in an empty space, or the substrate contact regions 103 arranged in advance for each of the N channel MOS transistor cells 100 are connected by metal wiring.
[0013]
On the other hand, the source wiring (S1) connected to the N-type diffusion region (n +) 102 forming the source region via a contact is made of metal, and as shown in FIG. It is short-circuited. Such a layout pattern of the first MOS transistor cell 100 is mainly used for high-frequency transistors.
[0014]
In addition, the drain trunk line (D) and the gate trunk line (G) have a structure that is randomly exposed so that the drain trunk line (D) and the gate trunk line (G) can be wired with adjacent cells.
[0015]
The N-channel MOS transistor cell 100 is an example in which transistors having a size of the minimum channel width unit Wmin = 10 / 0.35 are laid out as shown in FIG.
[0016]
On the other hand, as shown in FIG. 29, dummy polysilicon wirings (Gd1) are additionally arranged on both sides of the gate wiring (G1) made of polysilicon wirings arranged continuously and uniformly, which occurs when the polysilicon layer is formed. This prevents adverse effects caused by variations in the gate wiring structure due to undercutting.
[0017]
As described above, the substrate contact region 103 in FIG. 30 is arranged as much as possible in the vacant space in the layout, so that the operation of the transistor in the second substrate (P-substrate 2) 101a is further stabilized, and the threshold value is increased. There is a role to suppress variation.
[0018]
When the N-channel MOS transistor cell 100 shown in FIG. 29 is arranged in the second substrate (P-substrate2) 101a, a drain region is formed on the second substrate (P-substrate2) 101a. And two N-type diffusion regions (n +) 102 and 102 forming a source region, a gate wiring (G1) made of polysilicon wiring, and a P-type diffusion for applying a substrate potential as shown in FIG. N channel MOS transistor cell 100 formed of regions (p +) 108 and 108 is formed.
[0019]
Here, the layout structure of the N-channel MOS transistor cell 100 shown in FIG. 31 will be further described with reference to FIGS.
[0020]
First, a layout example of the N-channel MOS transistor cell 100 having a three-terminal configuration including a gate terminal (gate wiring (G1)), a source terminal (source wiring (S1)), and a drain terminal (drain wiring (D1)) is shown in FIG. 33 (a). Further, a circuit diagram in consideration of the gate resistance Rg by the gate wiring (G1) made of the polysilicon wiring is shown in FIG. 34 (a).
[0021]
In the prior art, in order to reduce the gate wiring (G1) gate resistance Rg, the channel width W = α of the N-channel MOS transistor cell 100 is divided in parallel as shown in FIG. A technique for reducing the gate resistance Rg to ¼ or less as shown in FIG. 34B by setting α / 2 and further disposing the substrate contact region 103 at both ends of the gate wiring (G1) as shown in FIG. It is used.
[0022]
When realizing a desired transistor size using the N-channel MOS transistor cell 100 shown in FIG. 29, the devices shown in FIGS. 35 to 37 are mainly used. For example, FIG. 35 is an example in which the wiring of the drain trunk lines (D) is omitted by inverting one cell left and right and bringing the drain trunk lines (D) of adjacent cells to face each other. FIG. 36 is an example in which the wiring between the gate trunk lines (G) is omitted as in FIG. Usually, in order to prevent a design rule error that causes the substrate contact 105 to float, the inter-cell wiring 120 is performed at this stage.
[0023]
FIG. 37 shows an example in which the wiring between the source wirings (S1) in the substrate contact region 103 is omitted.
(Transistor layout sample (2))
Next, FIG. 38 shows a layout pattern of a second N-channel MOS transistor cell 200 which is another conventional technique.
[0024]
In this layout, a transistor block 204 including N-type diffusion regions (n +) 202 and 202 for forming drain and source regions on a P-type substrate and a gate wiring (G1) composed of polysilicon wiring is described with reference to P A substrate contact region 203 formed of a type diffusion region is arranged in an island shape between the upper and lower ends of the transistor block 204 and the drain trunk line (D). The source wiring (S1) is drawn out from the S1 wiring as a source trunk line (S) at the same potential as the N-type diffusion region (n +) forming the transistor. Further, substrate contact regions 203 and 203 outside the above-described dummy poly wiring are arranged outside the gate wiring (G1) made of polysilicon wiring, and the gate wiring is a top having a low resistance from G1 to the gate trunk line (G). Pulled out with metal.
(Example of transistor layout of University of California Berkeley)
Another conventional technique is a transistor layout example of Non-Patent Document 1 published in a doctoral dissertation at the University of California, Berkeley. FIG. 38 is a plan view showing a layout pattern limited to the transistors of the differential input LNA circuit in FIG.
[0025]
As described above, the channel widths of the MOS transistors (M1 to M4) constituting the LNA circuit are divided in parallel into the minimum units, and the transistor cells 300... Having the desired number of fingers are arranged in a matrix, and the periphery of the transistor cells 300. Substrate contact regions 303 are later spread in a lattice pattern.
[0026]
[Non-Patent Document 1]
Dennis Gee-Wai Yee, "A Design Methodology for Highly-Integrated Low-Power Receivers for Wireless Communications," University of California Berkeley, p170, Spring 2001.
[0027]
[Problems to be solved by the invention]
However, in the first prior art N-channel MOS transistor cell 100 configured as described above, as shown in FIG. 37, the source / substrate potential common lead-out line 108 has a substrate contact region 103, that is, an N-channel MOS transistor. Since it protrudes from the cell 100, it is subject to the restrictions of cumbersome design rules such as the clearance rule 2 between the substrate contact regions 103 and the clearance rule 1 between contact holes. May take extra time.
[0028]
Also, as shown in FIGS. 35 and 36, since the drain trunk line (D) and the gate trunk line (G) protrude from the N-channel MOS transistor cell 100, the design rule regarding the substrate contact regions 103 and 103 having the same function, etc. It is necessary to connect later by the inter-cell wiring 120 so as to satisfy the above.
[0029]
Next, in the N-channel MOS transistor 200 according to the second prior art, as shown in FIG. 38, the substrate contact regions 203 and 203 are arranged in the form of solitary islands in consideration of the restrictions of the design rules used in the layout design. It is necessary to wire each other. In this case, it is a troublesome and inefficient work of performing layout while paying attention to the rules of the intersection of adjacent metal layers and the interval between adjacent metals.
[0030]
Further, since the arrangement of the substrate contact regions 203 and 203 is geometrically asymmetric, there is a possibility that the N-channel MOS transistor cell 200 may vary in terms of stabilization, threshold value, and the like.
[0031]
On the other hand, in the layout example of the transistor cell 300, which is the third prior art published in the doctoral dissertation of the University of California, Berkeley, as shown in FIG. 39, the vertically and horizontally symmetric transistor cells 300 are equally arranged in a matrix. Thereafter, the substrate contact regions 303 are arranged in a lattice pattern between the cells. That is, in the same way as the first N-channel MOS transistor cell 100 and the second N-channel MOS transistor cell 200, taking into account the restrictions of the design rules used at the time of layout design, it is troublesome and efficient to use the empty space. I have to do bad work.
[0032]
Furthermore, in the layout sample in the first N-channel MOS transistor cell 100 and the second N-channel MOS transistor cell 200 which are the prior art, the source wiring (S1) and the substrate terminal which is the substrate are short-circuited. In general, the substrate terminal (subgnd) of the N-channel transistor must be connected to the node of the lowest potential, and the substrate terminal (subvdd) of the P-channel transistor must be connected to the node of the highest potential (here, The contact that suppresses the substrate terminal (subvdd) is referred to as the “N-well substrate contact”.)
[0033]
In these cases, the potential of the source wiring (S1) may be different from the potential of the substrate terminal. Since the channel is a region sandwiched between the gate wiring (G1) and the substrate or well, not only the potential difference between the gate and the source but also the potential difference between the source and the substrate affects the formation of the channel. For example, the gate-source voltage (V _GS ) Source / substrate voltage (V _SB ) Changes, the threshold voltage (V _T ) Changes. Source substrate voltage (V _SB ) In consideration of
V _T = V _T0 + Γ {(√ (2φ _f + V _SB ) −√φ _f ) ……… (1)
It is known that However, V _T0 Is the source / substrate voltage (V _SB ) Is the threshold voltage when zero. γ or φ _f Is a constant determined by the process.
[0034]
In other words, if the structure of the substrate contact differs for each cell in the layout, the threshold voltage (V _T ) May vary. Therefore, it is necessary to lay out the substrate contacts evenly at the cell stage so that the substrate contacts do not need to be locally deformed after the cells are arranged.
[0035]
Further, the formation of the substrate contact regions 103 and 203 after the cell placement is greatly restricted by the design rules used in the layout design, and is a troublesome and inefficient operation.
[0036]
In the conventional layout method, it is common to first place the parts that become the core of the transistor cell or the like, and there is a possibility that a sufficient substrate area cannot be secured depending on the arrangement of the parts. Furthermore, since the transistor structure including the substrate contact tends to be non-uniform, the threshold characteristics and noise resistance of the transistor may vary.
[0037]
In summary, when forming a MOS transistor cell according to the design flow as described above, the possibility of forgetting the placement of the substrate contact region, the connection error, forgetting the connection and the parameter specification error, and the occurrence of human error is extremely high. There is a high possibility that the structure becomes non-uniform and the threshold voltage varies.
[0038]
The present invention has been made in view of the above-described conventional problems, and its object is to avoid wiring between transistor cells between substrate contact regions when arranging transistor cells continuously, and to design rules when designing a layout. It is an object of the present invention to provide a connectable transistor cell structure capable of forming a substrate contact region without being restricted by the above-described restrictions and reducing the possibility of variation in threshold voltage.
[0039]
[Means for Solving the Problems]
In order to solve the above problems, the connectable transistor cell structure of the present invention includes a drain region, a gate region, a source region, and a substrate contact region for stabilizing the operation of the transistor, and constitutes a semiconductor integrated circuit. In the connectable transistor cell structure arranged in parallel as much as possible, the substrate contact region is formed to be the outermost periphery of the transistor cell.
[0040]
According to the above invention, since the substrate contact region is formed to be the outermost periphery of the transistor cell, when connecting the transistor cells, the substrate contact region existing on the outermost periphery is brought into contact with each other by connecting the transistor cells. They are in contact with each other and are electrically connected. For this reason, the trouble of wiring between the transistor cells between the substrate contact regions can be saved.
[0041]
In addition, when transistor cells are continuously arranged, if there is a gap between transistor cells and a gap between substrate contact regions, the transistor cell structure itself is re-established under the constraints of cumbersome design rules for processing the gap. There is a risk of extra work and time, such as changes or repairs in the metal layer.
[0042]
However, in the present invention, since the substrate contact region exists on the outermost periphery, there is no gap between the transistor cells and between the substrate contact regions when the transistor cells are continuously arranged. Further, it is not necessary to newly form a substrate contact region. For this reason, transistor cells can be continuously arranged without any restriction of design rules at the time of layout design.
[0043]
Further, if the structure of the substrate contact region differs for each transistor cell in the layout, the threshold voltage may vary.
[0044]
However, in the present invention, since the substrate contact region is present at the outermost periphery for any transistor cell, the transistor structures can be made completely equal, and the possibility of variations in threshold voltage can be reduced. .
[0045]
Therefore, when transistor cells are continuously arranged, wiring between the transistor contact regions of the substrate contact region is avoided, and the substrate contact region is formed without being restricted by the design rules at the time of layout design. A connectable transistor cell structure can be provided.
[0046]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein a first layer metal connected to the substrate contact region is provided, and the first layer metal is By short-circuiting at the first layer at the rising portion from the drain region / gate region / source region to each drain wiring / gate wiring / source wiring, the transistor function is disabled, and the transistor cell is made into a pseudo substrate contact block. It can be converted.
[0047]
According to the above invention, the first layer metal connected to the substrate contact region is short-circuited in the first layer at the rising portion from the drain region / gate region / source region to each drain wiring / gate wiring / source wiring. As a result, the transistor function is disabled and the transistor cell can be converted into a pseudo substrate contact block.
[0048]
That is, in the present invention, the transistor cell can be reused as a pseudo substrate contact cell by covering the first layer metal so as to short-circuit the gate / drain / source / substrate terminal over the entire transistor cell. As a result, the transistor cell is handled as a substrate contact cell.
[0049]
Therefore, by allocating transistor cells that are substrate contact cells for stabilizing the substrate potential at which the transistors are arranged in the empty space on the layout pattern, the cell empty space can be effectively used.
[0050]
Specifically, for example, a gate wiring using a TOP metal having a relatively low resistance, and a source wiring and a drain wiring that often use the second and third layers as the main signal lines, all use the first layer metal. By paying attention to the contact coupling to the upper layer via the metal, the transistor cell can be easily switched to the substrate contact cell by simply mounting the first layer metal for short circuit to the transistor cell. .
[0051]
On the other hand, when the transistor cell of the present invention is laid out in a space between the element circuits as a pseudo substrate contact cell, conversely, the first layer metal for short-circuiting the pseudo substrate contact cell is used. By removing it, it can be easily reused as the original transistor cell.
[0052]
In other words, by continuously arranging pseudo substrate contact cells in an empty space in the layout, the substrate contact cell can be removed by, for example, removing the first layer metal for short-circuiting in response to various transistor size changes. It can be efficiently reused as a channel MOS transistor. Further, the unnecessary substrate contact cell serves to enhance the substrate potential in the empty space.
[0053]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the drain wiring / source wiring connected to the drain region / source region is above the substrate contact region. Each drain trunk line / source trunk line for supplying a signal is disposed inside and above the substrate contact region of the transistor cell, and the width of the substrate contact region expands and contracts according to the width of each drain trunk line / source trunk line. It is characterized by being formed.
[0054]
According to the above invention, the width of the substrate contact region is formed by expanding and contracting according to the width of each main line of the drain main line and the source main line.
[0055]
Therefore, for example, the outermost substrate contact region can be easily maintained while maintaining the basic substrate frame structure in response to changes in the main line width of the drain main line and source main line obtained from the current value distributed for each transistor cell. It can be stretched and deformed.
[0056]
That is, since the structure of the substrate contact region is improved, versatile transistor cells can be formed without changing the basic structure of the substrate contact region. For example, it becomes possible to easily form different transistor cells for each operating current.
[0057]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the substrate contact region supplies a signal to each drain wiring / source wiring connected to the drain region / source region. The drain main line and the internal region located below the source main line are opened as much as possible.
[0058]
According to the above invention, the substrate contact region has an internal region located below each drain trunk / source trunk that supplies a signal to each drain wiring / source wiring connected to the drain region / source region as much as possible. It is open.
[0059]
Therefore, the parasitic capacitance formed between the first layer metal covering the substrate contact region and the drain trunk line / source trunk line can be reduced by cutting out the substrate contact area located below the drain trunk line / source trunk line as much as possible. it can.
[0060]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the drain trunk line / source trunk line is arranged inside the outermost periphery of the transistor cell, thereby allowing mutual drain trunk lines / The substrate contact region width is set so as to satisfy the clearance rule between metals when the source trunk lines face each other.
[0061]
According to the above invention, by arranging the drain trunk line / source trunk line inside the outermost periphery of the transistor cell, the substrate contact region satisfies the clearance rule between metals when the drain trunk line / source trunk line faces each other. The width is set.
[0062]
Therefore, since the transistor cells can be continuously arranged without worrying about the restriction of the design rule at the time of layout design, the layout efficiency is further improved.
[0063]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the gate trunk line for supplying a signal to the gate wiring connected to the gate region is provided at the outermost periphery of the transistor cell. It is characterized in that it is formed to extend to.
[0064]
According to the above invention, since the gate trunk line is formed to extend to the outermost peripheral end portion of the transistor cell, the gate trunk lines can be connected by abutting the gate trunk lines of adjacent transistor cells. Therefore, when the transistor cells are continuously connected in the opposite direction of the gate trunk line, a separate connection wiring can be omitted for the gate trunk line.
[0065]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein each drain trunk line / source that supplies a signal to each drain line / source line connected to the drain region / source region is provided. The trunk line is characterized in that it extends to the outermost periphery of the transistor cell.
[0066]
According to the above invention, each drain trunk line / source trunk line that supplies a signal to each drain wiring / source wiring connected to the drain region / source region is formed to extend to the outermost peripheral edge of the transistor cell. Yes.
[0067]
For this reason, the drain trunk lines and the source trunk lines can be connected by matching the drain trunk lines of adjacent transistor cells and by matching the source trunk lines. Therefore, when the transistor cells are continuously connected in the opposing direction of the drain trunk lines and the source trunk lines, separate connection wirings for the drain trunk lines and the source trunk lines can be omitted.
[0068]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the transistor cells have various functions depending on the purpose of design, but the transistor cells are connected to each other. The substrate contact regions of the transistor cells having different functions can be shared by abutting the substrate contact regions of the respective transistor cells.
[0069]
According to the above invention, when the transistor cells having different functions are connected to each other, the substrate contact regions of the transistor cells having different functions can be shared by matching the substrate contact regions of the respective transistor cells. It is possible to form a differential pair with good symmetry by arranging them in common.
[0070]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the transistor cell is an N-channel MOS transistor formed in a first P-type semiconductor substrate. It is a feature.
[0071]
According to the above invention, the transistor cell is an N-channel MOS transistor formed in the first P-type semiconductor substrate. Therefore, when the transistor cells are continuously arranged in the N-channel MOS transistor, the substrate contact region is formed. To provide a connectable transistor cell structure that avoids wiring between transistor cells, forms a substrate contact region without being restricted by design rules during layout design, and reduces the possibility of variation in threshold voltage Can do.
[0072]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein the transistor cell is isolated by a process option (Deep N-well) and an N-well. It is characterized in that it is formed in a type semiconductor substrate.
[0073]
According to the above invention, since the transistor cell is formed in the second P-type semiconductor substrate isolated by the process option (Deep N-well) and the N-well, the transistor cell is generated by another circuit. The influence of noise is cut off, and the transistor can operate at a stable substrate potential.
[0074]
The connectable transistor cell structure of the present invention is characterized in that in the connectable transistor cell structure described above, the substrate contact region is an N-well substrate contact region.
[0075]
According to the above invention, the substrate contact region is an N-well substrate contact region. Therefore, in the P channel MOS transistor, when the transistor cells are continuously arranged, wiring between the transistor contact regions is avoided, and the substrate contact region is formed without being restricted by the design rule at the time of layout design. A connectable transistor cell structure that can reduce the possibility of voltage variations can be provided.
[0076]
The connectable transistor cell structure of the present invention is characterized in that in the connectable transistor cell structure described above, the transistor cell has a planar shape of a polygon including a square and a triangle.
[0077]
According to the above invention, the transistor cell has a polygonal shape including a quadrangle and a triangle in plan view. That is, the transistor cell shape is not limited to a general square, and may be a triangle or another polygon.
[0078]
DETAILED DESCRIPTION OF THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described with reference to FIGS. 1 to 6 as follows.
[0079]
An N-channel MOS transistor cell 10 as a transistor cell to which the connectable transistor cell structure of the present embodiment is applied is formed on a first substrate (P-substrate) 1 made of a P-type substrate as shown in FIG. Are provided with a transistor block (Sensitive Circuit) 4 composed of an N-type diffusion region 2... For forming a drain region and a source region and a polysilicon wiring for forming a gate wiring (G 1). The above gate (G1) wiring generally uses a TOP metal layer having a relatively low resistance.
[0080]
In the present embodiment, as shown in FIG. 1, substrate contact region 3 is formed to be the outermost periphery of N-channel MOS transistor cell 10. That is, as shown in FIG. 3, the substrate contact region 3 is formed in a frame shape on the outermost periphery of the N-channel MOS transistor cell 10. As a result, the outer peripheral edge of the N channel MOS transistor cell 10 and the outer peripheral edge of the substrate contact region 3 coincide. Further, other components are also prevented from projecting from the outermost periphery of the N-channel MOS transistor cell 10 as shown in FIG.
[0081]
That is, in the present embodiment, a substrate frame in which the substrate contact regions 3 are all connected in advance is formed, and as described in the second embodiment, the third embodiment, and the like described later, according to the conventional technique. There is no need for metal connection between the substrate contact regions 3 shown in FIG. 33, FIG. 34 and FIG. That is, inter-element wiring between the substrate contact regions 3 and 3 between adjacent N-channel MOS transistor cells 10 and 10 can be omitted.
[0082]
In addition, by using the N-channel MOS transistor cell 10 according to the present embodiment, the necessity for wiring between elements and the restrictions on the design rules used at the time of layout design are drastically reduced, so that the layout work efficiency can be improved. .
[0083]
In the present embodiment, as shown in FIG. 2, dummy polysilicon wirings Gd1 are additionally arranged on both sides of the gate wiring (G1) made of polysilicon wirings that are continuously and evenly arranged. This structure prevents adverse effects due to manufacturing variations of the gate wiring (G1) due to undercut that occurs during layer formation.
[0084]
In addition, based on the arrangement shown in FIG. 27, which is an explanatory view of the prior art, the source wiring (S1), the gate wiring (G1), the drain wiring (D1), the gate wiring (G1), and the source wiring (S1) in this order. And has a repeated arrangement structure with the overlapping drain wiring (D1) as the center. Such a structure is generally called a common centroid structure.
[0085]
FIG. 4 is a simplified view of the N channel MOS transistor cell 10 shown in FIG. 1, and FIG. 5 is a cross-sectional view in which the N channel MOS transistor cell 10 is arranged in the second substrate (1a). A transistor block (Sensitive Circuit) 4 composed of two N-type diffusion regions 2 forming a source region and a drain region and a polysilicon wiring serving as a gate wiring (G1), and a transistor block (Sensitive Circuit) 4 A substrate contact region 3 formed of a P-type diffusion region for applying a substrate potential formed on the outer peripheral portion is provided.
[0086]
The framed N-type semiconductor region (N-well) 7b forming the outer wall is set to the power supply voltage by the diffusion contact hole 7c, the first to third metal layers 7d and the top metal layer 7f, the inter-metal contact hole 7e, and the like. The first substrate (P-substrate) 1 affected by other element circuits is shielded.
[0087]
The substrate contact region 3 is connected to a first layer metal (subgnd) 3a.
[0088]
By the way, in the N channel MOS transistor cell 10 of the present embodiment, as shown by a two-dot chain line in FIGS. 2 and 5, the first layer metal (subgnd) 3a connected to the substrate contact region 3 is replaced with a cell switching metal. It is possible to switch to 5.
[0089]
As a result, as shown in FIG. 6, the N-channel MOS transistor cell 10 can be easily switched to the substrate contact cell by using only a wiring composed of a simple plate-like metal made of the cell switching metal 5. The substrate contact cell is such that the drain region / gate region / source region and the substrate contact region 3 are all short-circuited by covering the entire N-channel MOS transistor cell 10 with the cell switching metal 5 in the first layer. As a result, the N channel MOS transistor cell 10 loses the transistor function, and the N channel MOS transistor cell 10 is treated as a substrate contact cell. As a result, the N channel MOS transistor cell 10 can be reused as a pseudo substrate contact cell.
[0090]
Further, since the outermost periphery is formed by the substrate contact region 3, smooth connection between the N channel MOS transistor cells 10 regardless of the upper, lower, left and right is possible. Further, the substrate contact region 3 can be expanded and contracted as shown by the broken arrows on both ends in FIG. 3 according to the change in the wiring width of the source trunk line (S) and the drain trunk line (D), and the basic structure of the substrate frame is not broken. Thus, it becomes possible to form the N-channel MOS transistor cell 10 according to the purpose. Further, as shown in FIG. 3, in order to avoid the formation of parasitic capacitance with the source trunk line (S) and the drain trunk line (D), the useless substrate contact region 3 is trimmed (cut out) 3c.
[0091]
FIG. 6 is a diagram showing means for switching the N-channel MOS transistor cell 10 according to the present embodiment to a substrate contact cell.
[0092]
The first layer metal (subgnd) 3a described with reference to FIGS. 2 and 5 is replaced with a cell switching metal 5 as a first layer metal and covered with a transistor block 4 as shown in FIG. As a result, the substrate contact region 3 and the gate wiring (G1), source wiring (S1), and drain wiring (D1) are short-circuited and can be easily switched to the substrate contact cell. Here, all of the wirings forming the gate wiring (G1), the source wiring (S1), and the drain wiring (D1) pass through the cell switching metal 5 in the lower metal layer. And can be short-circuited.
[0093]
Thus, in the structure of the connectable N channel MOS transistor cell 10 of the present embodiment, the substrate contact region 3 is formed so as to be the outermost periphery of the N channel MOS transistor cell 10. When connecting the transistor cells 10 and 10, the N-channel MOS transistor cells 10 and 10 are brought into contact with each other so that the substrate contact regions 3 and 3 existing on the outermost periphery come into contact with each other and are electrically connected. For this reason, the trouble of wiring between the transistor cells between the substrate contact regions 3 and 3 can be saved.
[0094]
Further, when the N channel MOS transistor cells 10 are continuously arranged, if there is a gap between the N channel MOS transistor cells 10 and 10 and a gap between the substrate contact regions 3 and 3, the gap is processed. Under the constraints of annoying design rules, there is a risk that it will take time and effort, such as re-changing the N-channel MOS transistor cell 10 structure itself or repairing it with a metal layer.
[0095]
However, in the present embodiment, since substrate contact region 3 exists on the outermost periphery, when N channel MOS transistor cells 10... Are arranged continuously, between N channel MOS transistor cells 10 and 10 and between substrate contact regions 3 and 3. There are no gaps. Further, it is not necessary to newly form the substrate contact region 3. Therefore, the N-channel MOS transistor cells 10 can be continuously arranged without any design rule restrictions at the time of layout design.
[0096]
Further, if the structure of the substrate contact region 3 is different for each N channel MOS transistor cell 10 in the layout, the threshold voltage may vary.
[0097]
However, in the present embodiment, since the substrate contact region 3 exists in the outermost periphery for any N channel MOS transistor cell 10..., Each transistor structure can be made completely equal, and the threshold voltage variation can be reduced. The possibility can be reduced.
[0098]
Therefore, when the N-channel MOS transistor cells 10 are continuously arranged, wiring between the N-channel MOS transistor cells 10 and 10 between the substrate contact regions 3 and 3 is avoided, and design rules are not restricted during layout design. A substrate contact region 3 can be formed to provide a connectable N-channel MOS transistor cell 10 structure that can reduce the possibility of threshold voltage variation.
[0099]
In the structure of the connectable N channel MOS transistor cell 10 of the present embodiment, the first layer metal (subgnd) 3a connected to the substrate contact region 3 is connected to each drain wiring from the drain region / gate region / source region. (D1) Short circuit in the first layer at the rising edge to the gate wiring (G1) / source wiring (S1), thereby invalidating the transistor function and making the N-channel MOS transistor cell 10 a pseudo substrate contact block Conversion is possible.
[0100]
That is, in the present embodiment, the N-channel MOS transistor cell 10 is artificially covered by covering the cell switching metal 5 so that the gate, drain, source, and substrate terminal are short-circuited to the entire N-channel MOS transistor cell 10. It can be reused as a substrate contact cell. Thereby, the N channel MOS transistor cell 10 disables the transistor function in the N channel MOS transistor cell 10 by short-circuiting the drain region, the gate region, the source region and the substrate contact region 3, and the N channel MOS transistor 10. The transistor cell 10 is handled as a substrate contact cell.
[0101]
Therefore, by effectively providing the N channel MOS transistor cell 10 which is a substrate contact cell for stabilizing the substrate potential for arranging the transistor in the empty space on the layout pattern, the cell empty space is effectively used. be able to.
[0102]
Specifically, for example, in addition to the plate-like metal using the first layer metal (subgnd) 3a, the gate wiring (G1) using a TOP metal having a relatively low resistance, the second and third layers as main signal lines, etc. Note that the source wiring (S1) and drain wiring (D1), which are often used, are all short-circuited by paying attention to the point that they are contact-coupled to the upper layer via the plate metal using the first layer metal. The N channel MOS transistor cell 10 can be easily switched to the substrate contact cell simply by mounting the cell switching metal 5 for the N channel MOS transistor cell 10.
[0103]
On the other hand, when the N-channel MOS transistor cell 10 of the present embodiment is laid out in the empty space between each element circuit as a pseudo substrate contact cell, conversely, for the short circuit of the pseudo substrate contact cell. By removing the cell switching metal 5, the original N-channel MOS transistor cell 10 can be easily reused.
[0104]
That is, by disposing the pseudo substrate contact cells continuously in an empty space on the layout, the substrate contact cells can be changed to N by simply removing the cell switching metal 5 for short-circuiting in response to various transistor size changes. The channel MOS transistor cell 10 can be efficiently reused. Further, the unnecessary substrate contact cell serves to enhance the substrate potential in the empty space.
[0105]
Further, in the structure of the connectable N-channel MOS transistor cell 10 of the present embodiment, the width of the substrate contact region 3 is expanded and contracted in accordance with the width of each drain main line (D) and source main line (S). Is done.
[0106]
Therefore, for example, the basic structure of the substrate frame is maintained with respect to the change of the main line width of the drain main line (D) and the source main line (S) obtained from the current value distributed for each N-channel MOS transistor cell 10. The outermost substrate contact region 3 can be easily stretched and deformed.
[0107]
That is, since the structure of the substrate contact region 3 is improved, versatility can be formed without changing the basic structure of the substrate contact region 3. For example, it becomes possible to easily form different N channel MOS transistor cells 10 for each operating current.
[0108]
Further, in the structure of the connectable N-channel MOS transistor cell 10 of the present embodiment, the substrate contact region 3 sends a signal to each drain wiring (D1) / source wiring (S1) connected to the drain region / source region. A portion located below each drain trunk line (D) and source trunk line (S) to be supplied is opened as much as possible.
[0109]
Accordingly, the first layer metal (subgnd) 3a and the drain trunk line (D) covering the substrate contact region 3 are cut out as much as possible by cutting out the substrate contact region 3 located below the drain trunk line (D) / source trunk line (S). -The parasitic capacitance formed between the source trunk lines (S) can be reduced.
[0110]
In the structure of the connectable N channel MOS transistor cell 10 of the present embodiment, the N channel MOS transistor cell 10 is composed of an N channel MOS transistor formed in a first substrate (P-substrate) 1. Therefore, in the N channel MOS transistor, when the N channel MOS transistor cells 10 are continuously arranged, wiring between the N channel MOS transistor cells 10 and 10 between the substrate contact regions 3 and 3 is avoided, and the design rule of the layout design is avoided. The structure of the connectable N-channel MOS transistor cell 10 that can form the substrate contact region 3 without restriction and reduce the possibility of variation in threshold voltage can be provided.
[0111]
In the structure of the connectable N-channel MOS transistor cell 10 of the present embodiment, the N-channel MOS transistor cell 10 has a second substrate (Deep N-well 7a) and a second substrate (N-well 7b) isolated by a process option (Deep N-well 7a). Since it is formed in the P-substrate 2) 1a, the influence of noise generated in other circuits can be cut off and the transistor can operate at a stable substrate potential.
[0112]
[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and descriptions thereof are omitted.
[0113]
In the present embodiment, an example will be described in which N-channel MOS transistor cells 10 are connected in the x-axis direction in FIG. 1 of the first embodiment, that is, in the extending direction of the gate wiring (G1).
[0114]
FIG. 7 is a circuit diagram of a differential pair composed of N-channel MOS transistors M1 and M2 having two kinds of roles, and an example in which the source wiring (S1) is opened for insertion of an impedance element.
[0115]
In FIG. 8, the channel width W = α of the two types of N-channel MOS transistors M1 and M2 shown in FIG. 7 is divided into 16 (Wmin = α / 16), and 8 fingers (W ′ = 8 × Wmin). N-channel MOS transistor cells M1 ′ and M2 ′, which are N-channel MOS transistor cells 10 according to the present embodiment, are formed every time (M1 ′ = M2 ′ = 2 * W ′), and the x-axis direction shown in FIG. That is, it is connected in the same direction as the gate wiring (G1) (extending direction of the gate wiring (G1)).
[0116]
As shown in the figure, the N-channel MOS transistor cells M1 'and M2' are arranged in a cross shape and geometrically symmetric with respect to the origin. Even when process variations occur, the variations between the N-channel MOS transistor M1 and the N-channel MOS transistor M2 in FIG. 7 are equal.
[0117]
Further, by using the configuration according to the present embodiment, the substrate contact regions 3 and 3 can be easily connected to each other between different transistor cells such as the N-channel MOS transistor cells M1 ′ and M2 ′ shown in FIG. Is possible. Further, when the source trunk line (S) of the N channel MOS transistor cell M1 ′ and the drain trunk line (D) of the N channel MOS transistor M2 ′ are connected in the x-axis direction at the cell stage, the substrate contact region 3. Therefore, the clearance rule between adjacent metal wirings can be satisfied without worrying about the restriction of the design rule used at the time of layout design. That is, the source trunk line (S) and the drain trunk line (D) must not be in contact with each other and should not be too close. In this regard, when the N-channel MOS transistor cells M1 ′ and M2 ′ are connected, the substrate contact regions 3 and 3 having a constant interval width exist therebetween, so that the substrate contact regions 3 and 3 having a constant interval width do not exist. Compared to the case, there is no need to worry about the distance between the source trunk line (S) and the drain trunk line (D).
[0118]
The final substrate wiring may be drawn from an arbitrary position or the like of the substrate contact region 3 at both ends of the connected N channel MOS transistor cells M1 ′ and M2 ′.
[0119]
Thus, in the structure of connectable N-channel MOS transistor cells M1 ′ and M2 ′ of the present embodiment, the N-channels in the outer end portions of the drain trunk line (D) and source trunk line (S) and the substrate contact region 3 are used. The planar spacing between the MOS transistor cells M1 ′ and M2 ′ and the outermost periphery is continuously in the extending direction of the gate wiring (G1) connecting the N-channel MOS transistor cells M1 ′ and M2 ′ to the gate region. The substrate contact region width is set in advance so as to satisfy the intermetal clearance rule when the drain trunk line (D) and the source trunk line (S) face each other by being connected.
[0120]
Therefore, since the N-channel MOS transistor cells M1 ′ and M2 ′ can be continuously arranged in a cross shape without worrying about the restriction of the design rule at the time of layout design, the layout efficiency is further improved.
[0121]
In the structure of connectable N-channel MOS transistor cells M1 ′ and M2 ′ in the present embodiment, when N-channel MOS transistor cells M1 ′ and M2 ′ having different functions are connected to each other, each N-channel MOS transistor cell Since the substrate contact regions 3 and 3 of the N channel MOS transistor cells M1 ′ and M2 ′ having different functions can be shared by abutting the substrate contact regions 3 and 3 of M1 ′ and M2 ′, the substrate contact regions 3 and 3 can be shared. It is possible to form a differential pair with good symmetry by arranging them in common.
[0122]
[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiment 1 and Embodiment 2 are given the same reference numerals, and the description thereof is omitted.
[0123]
In this embodiment, a connection example in the x-axis direction of four types of N-channel MOS transistor cells will be described.
[0124]
FIG. 9 is a circuit diagram of two differential pairs composed of four N-channel MOS transistors (M1 to M4) of a mixing unit conventionally used in a Gilbert cell mixer.
[0125]
In FIG. 10, the channel width (W = 80) of the two transistors shown in FIG. 9 is divided into 8 (Wmin = 80/8 = 10), and this operation is performed every 8 fingers (W ′ = 8 × Wmin). N-channel MOS transistor cells M1 ′, M2 ′, M3 ′, and M4 ′, which are N-channel MOS transistor cells 10 according to mode 1, are formed (M1 ′ = M2 ′ = M3 ′ = M4 ′ = W ′), and FIG. N-channel MOS transistor cells M1 ′ and M4 ′ and N-channel MOS transistor cells M2 ′ and M3 ′ are connected in the x-axis direction shown, that is, in the same direction as the gate wiring (G1) (extension direction of the gate wiring (G1)). This is an example of arrangement. For example, the N-channel MOS transistor cells M1 ′ and M2 ′ and the N-channel MOS transistor cells M3 ′ and M4 ′ may be connected to each other.
[0126]
In FIG. 10, N-channel MOS transistor cells M1 ′ and M2 ′ serving as a differential pair and N-channel MOS transistor cells M3 ′ and M4 ′ serving as a differential pair are arranged symmetrically. For this reason, even if process variations occur in the directions shown by the lower arrows in the figure, the N-channel MOS transistor cells M1 ′ and M2 ′ serving as a differential pair and the N-channel MOS transistor cells serving as a differential pair The variations of M3 ′ and M4 ′ are equal.
[0127]
In addition, by using the configuration according to the present embodiment, the substrate contact region 3 can be easily connected to other transistor cells such as the N-channel MOS transistor cells M1 ′ and M4 ′ and the N-channel MOS transistor cells M2 ′ and M3 ′.・ 3 can be connected.
[0128]
Further, when the source trunk line (S) of the N-channel MOS transistor cell M1 ′ and the drain trunk line (D) of the N-channel MOS transistor M4 ′ are connected in the x-axis direction at the cell stage, the substrate contact region 3. Therefore, the clearance rule between adjacent metal wirings can be satisfied without worrying about the restriction of the design rule used at the time of layout design.
[0129]
Further, the final substrate wiring includes the positions of the substrate contact regions 3 and 3 at both ends of the connected N channel MOS transistor cells M1 ′ and M4 ′ and the substrate contact regions 3 at both ends of the N channel MOS transistor cells M2 ′ and M3 ′. -It should be pulled out from any position of 3 etc.
[0130]
[Embodiment 4]
The following will describe still another embodiment of the present invention with reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 3 are given the same reference numerals, and descriptions thereof are omitted.
[0131]
In the present embodiment, a connection example in the y-axis direction of FIG. 1 in an N channel MOS transistor cell will be described.
[0132]
FIG. 11 shows an example in which two N-channel MOS transistors are formed for every 8 fingers and are connected in the y-axis direction (perpendicular to the gate wiring (G1)) in FIG.
[0133]
In this figure, the structure is substantially the same as that of the 16-finger N-channel MOS transistor cell 10 described in the second and third embodiments. As shown in the figure, not only between the substrate contact regions 3 and 3 of adjacent N-channel MOS transistor cells 10 and 10, but also between the gate trunk lines (G) and (G), and the source trunk lines (S) and (S). Since there is no need to lay out the connection between the drain lines and the drain main lines (D) and (D), the layout efficiency can be increased.
[0134]
As described above, in the structure of connectable N channel MOS transistor cells 10 and 10 according to the present embodiment, the gate trunk line (G) is formed to extend to the outermost peripheral edge of the N channel MOS transistor cells 10 and 10. Therefore, the gate trunk lines (G) and (G) can be connected to each other by matching the gate trunk lines (G) and (G) of the adjacent N-channel MOS transistor cells 10 and 10. Therefore, when the N-channel MOS transistor cells 10 and 10 are continuously connected in the opposing direction of the gate trunk lines (G) and (G), a separate connection wiring may be omitted for the gate trunk lines (G) and (G). it can.
[0135]
In the structure of connectable N-channel MOS transistor cells 10 and 10 according to the present embodiment, each drain that supplies a signal to each drain wiring (D1) and each source wiring (S1) connected to the drain region and the source region. The trunk line (D) and the source trunk line (S) are formed to extend to the outermost peripheral ends of the N-channel MOS transistor cells 10 and 10.
[0136]
Therefore, the drain trunk lines (D) and (D) are obtained by matching the drain trunk lines (D) and (D) of the adjacent N-channel MOS transistor cells 10 and 10 and butting the source trunk lines (S) and (S). And source trunk lines (S) and (S) can be connected. Therefore, when the N-channel MOS transistor cells 10 and 10 are continuously connected in the opposing direction of the drain trunk lines (D) and (D) and the source trunk lines (S) and (S), the drain trunk lines (D) and (D ) And the source trunk lines (S) and (S) can be omitted.
[0137]
[Embodiment 5]
The following will describe still another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 4 are given the same reference numerals, and descriptions thereof are omitted.
[0138]
In this embodiment, a P-channel MOS transistor cell will be described.
[0139]
As shown in FIG. 12, the P-channel MOS transistor cell 20 of the present embodiment includes a drain region and a source on an N-well substrate 21 formed on a first substrate (P-substrate) 1 made of a P-type substrate. It has a transistor block (Sensitive Circuit) 24 composed of a P-type diffusion region 22 forming a region and a gate wiring (G1) made of polysilicon wiring. The gate wiring (G1) generally uses a TOP metal layer having a relatively low resistance.
[0140]
Further, around the transistor block (Sensitive Circuit) 24, an N-well substrate contact region 23 composed of an N-type diffusion region for applying a substrate potential is formed.
[0141]
In the present embodiment, the N-well substrate contact region 23 is formed so as to surround the outermost periphery of the P-channel MOS transistor cell 20 as shown in FIG. Thus, in the present embodiment, inter-element wiring between the N-well substrate contact regions 23 of adjacent P-channel MOS transistor cells 20 can be omitted.
[0142]
By using the P-channel MOS transistor cell 20 according to the present embodiment, it is possible to increase the layout work efficiency because the necessity of wiring between elements and the restriction of the design rule used at the time of layout design are drastically reduced.
[0143]
FIG. 14 is a diagram showing a simplified version of the P-channel MOS transistor cell 20 of FIG.
[0144]
On the other hand, in the present embodiment, the first layer metal (subvdd) 23a connected to the N-well substrate contact region 23 shown in FIG. 15 is used as the first layer metal as shown by a two-dot chain line in FIG. Switching to the cell switching metal 25 is possible.
[0145]
Here, in the present embodiment, all of the wirings forming the gate wiring (G1), the source wiring (S1), and the drain wiring (D1) pass through the first layer in the lower metal layer. It is possible to short-circuit using layers.
[0146]
As a result, as shown in FIG. 16, the P-channel MOS transistor cell 20 can be easily switched to the N-well substrate contact cell with only a wiring composed of a simple plate metal made of the cell switching metal 25. The N-well substrate contact cell is a drain region / gate region / source region and an N-well substrate contact region by covering the entire P channel MOS transistor cell 20 with the cell switching metal 25 in the first layer. All 23 are short-circuited. As a result, the P-channel MOS transistor cell 20 loses the transistor function and is treated as an N-well substrate contact cell. As a result, the P-channel MOS transistor cell 20 can be pseudo-reused as an N-well substrate contact cell, so that the N-well power supply potential can be enhanced.
[0147]
FIG. 17 is a plan view of a layout pattern in which the N-well substrate contact region 23 of FIG. 12 is extracted. As shown in the figure, an N-well substrate frame in which all N-well substrate contact regions 23 are connected in advance is formed. Further, since the outermost periphery is formed by the N-well substrate contact region 23, smooth connection between the P-channel MOS transistor cells 20 irrespective of the upper, lower, left and right sides is made possible.
[0148]
Further, according to the change in the wiring width of the source trunk line (S) and the drain trunk line (D) shown in FIG. 13, the N-well substrate contact region 23 can be expanded and contracted as shown by the double-ended arrows in FIG. It is possible to form the P-channel MOS transistor cell 20 according to the purpose without destroying the basic structure of the well substrate frame.
[0149]
In the present embodiment, in order to avoid the formation of parasitic capacitance with the source trunk line (S) and the drain trunk line (D), the useless N-well substrate contact region 23 is trimmed (cut out) 23c.
[0150]
Thus, in the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the substrate contact region is the N-well substrate contact region 23. Therefore, in the P channel MOS transistor, when the P channel MOS transistor cells 20 are continuously arranged, the wiring between the P channel MOS transistor cells 20 and 20 between the N-well substrate contact regions 23 and 23 is avoided, and the layout design is performed. The N-well substrate contact region 23 can be formed without being restricted by the design rule, and the structure of connectable P-channel MOS transistor cells 20 and 20 that can reduce the possibility of variation in threshold voltage can be provided. Here, since the N-well substrate itself automatically overlaps by connecting the N-well substrate contact regions 23, 23, there is no need to worry about the design rule.
[0151]
In the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the first layer metal (subvdd) 23a connected to the N-well substrate contact region 23 is formed from the drain region, the gate region, and the source region. By making use of the feature of short-circuiting in the first layer at the rising portion to each drain wiring (D1), gate wiring (G1), and source wiring (S1), it is electrically connected to the drain region, gate region, and source region. The cell switching metal 25 can be used.
[0152]
That is, by covering the entire P channel MOS transistor cell 20 with the cell switching metal 25, the P channel MOS transistor cell 20 can be reused as a pseudo N-well substrate contact cell. As a result, the drain region, gate region, source region and N-well substrate contact region 23 are all short-circuited in the P-channel MOS transistor cell 20 to invalidate the transistor function in the P-channel MOS transistor cell 20. The P channel MOS transistor cell 20 is handled as an N-well substrate contact cell.
[0153]
Accordingly, by arranging the P-channel MOS transistor cell 20 which is an N-well substrate contact cell for stabilizing the transistor in the empty space on the layout pattern, the cell empty space can be effectively used. it can.
[0154]
On the other hand, when the P-channel MOS transistor cell 20 is laid out in the space between the element circuits as a pseudo substrate contact cell, the cell switching metal 25 of the pseudo substrate contact cell is removed. Thus, the original P channel MOS transistor cell 20 can be easily reused.
[0155]
Further, in the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the width of the N-well substrate contact region 23 is expanded or contracted according to the widths of the drain main line (D) and source main line (D). Formed.
[0156]
Therefore, for example, the basic structure of the substrate frame is maintained with respect to changes in the main line widths of the drain main line (D) and the source main line (D) obtained from the current value distributed for each P-channel MOS transistor cell 20. The outermost N-well substrate contact region 23 can be easily stretched and deformed.
[0157]
That is, since the structure of the N-well substrate contact region 23 is improved, the P-channel MOS transistor cell 20 rich in variations can be obtained without changing the basic structure of the N-well substrate contact region 23. Can be formed. For example, it becomes possible to easily form a different P channel MOS transistor cell 20 for each operating current.
[0158]
In the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the N-well substrate contact region 23 includes the drain wiring (D1) and the source wiring (S1) connected to the drain region and the source region. An internal region located below each drain trunk line (D) and source trunk line (D) for supplying a signal to the gate is opened as much as possible.
[0159]
Therefore, the first layer metal (subvdd) 23a covering the N-well substrate contact region 23 is cut by cutting out the N-well substrate contact region 23 located below the drain trunk line (D) / source trunk line (D) as much as possible. And parasitic capacitance formed between the drain trunk line (D) and the source trunk line (D) can be reduced.
[0160]
In the structure of the connectable P-channel MOS transistor cell 20 according to the present embodiment, the substrate contact region is an N-well substrate contact region 23.
[0161]
Therefore, in the P channel MOS transistor, when the P channel MOS transistor cells 20 are continuously arranged, the wiring between the P channel MOS transistor cells 20 and 20 between the N-well substrate contact regions 23 and 23 is avoided, and the layout design is performed. It is possible to provide a structure of connectable P-channel MOS transistor cells 20 and 20 that can form a substrate contact region without being restricted by design rules and reduce the possibility of variation in threshold voltage.
[0162]
[Embodiment 6]
The following will describe another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 5 are given the same reference numerals, and descriptions thereof are omitted.
[0163]
In the present embodiment, an example in which the P-channel MOS transistor cells 20 are connected in the x-axis direction in FIG. 13 of the fifth embodiment, that is, the extending direction of the gate wiring (G1) will be described.
[0164]
FIG. 18 is a circuit diagram of a differential pair composed of two types of P-channel MOS transistors M1 and M2. In FIG. 19, the channel width W = α of the two types of P-channel MOS transistors M1 and M2 shown in FIG. 18 is divided into 16 (Wmin = α / 16), and 8 fingers (W ′ = 8 × Wmin). Each time, P-channel MOS transistor cells M1 ′ and M2 ′, which are P-channel MOS transistor cells 20 according to the present embodiment, are formed (M1 ′ = M2 ′ = 2 * W ′), and the x-axis direction shown in FIG. That is, it is connected in the same direction as the gate wiring (G1) (extending direction of the gate wiring (G1)).
[0165]
As shown in the figure, the P-channel MOS transistor cells M1 ′ and M2 ′ are arranged in a cross shape and geometrically symmetrical with respect to the origin. Even when process variations occur, the variations between P channel MOS transistor M1 and P channel MOS transistor M2 in FIG. 19 are equal.
[0166]
Further, by using the configuration according to the present embodiment, it is possible to easily connect N-well substrate contact regions 23... Between transistor cells having different roles, such as P channel MOS transistor cells M 1 ′ and M 2 ′ shown in FIG. 23 can be connected. Further, when the source trunk line (S) of the P-channel MOS transistor cell M1 ′ and the drain trunk line (D) of the P-channel MOS transistor cell M2 ′ are connected in the x-axis direction at the cell stage, an N-well substrate is interposed therebetween. Since the contact regions 23 and 23 exist, the clearance rule between adjacent metal wirings can be satisfied without worrying about the restriction of the design rule used in the layout design. That is, the source trunk line (S) and the drain trunk line (D) must not be in contact with each other and should not be too close. In this respect, when the P-channel MOS transistor cells M1 ′ and M2 ′ are connected, there are N-well substrate contact regions 23 and 23 having a constant interval width therebetween. There is no need to worry about the distance between the source trunk line (S) and the drain trunk line (D) as compared with the case where 23 and 23 do not exist.
[0167]
The final substrate wiring may be drawn from an arbitrary position or the like of the N-well substrate contact region 23 at both ends of the connected P-channel MOS transistor cells M1 ′ and M2 ′.
[0168]
As described above, in the structure of the connectable P channel MOS transistor cells M1 ′ and M2 ′ according to the present embodiment, the drain trunk line (D) and the source trunk line (D) are connected to the top of the P channel MOS transistor cells M1 ′ and M2 ′. The substrate contact region width is set so as to satisfy the intermetal clearance rule when the drain trunk line and the source trunk line are opposed to each other by being arranged inside the outer periphery.
[0169]
In the present embodiment, the outer end portions of the drain trunk line (D) and the source trunk line (D) and the outermost peripheries of the P-channel MOS transistor cells M1 ′ and M2 ′ in the N-well substrate contact regions 23 and 23 The planar spacing between them is such that the P-channel MOS transistor cells M1 'and M2' are continuously connected in the extending direction of the gate wiring (G1) connected to the gate region, thereby allowing mutual drain trunk lines (D) and sources. It is set so as to satisfy the clearance rule between metals when the main line (D) faces.
[0170]
Therefore, since the P-channel MOS transistor cells M1 ′ and M2 ′ can be continuously arranged without worrying about the restriction of the design rule at the time of layout design, the layout efficiency is further improved.
[0171]
In the structure of connectable P-channel MOS transistor cells M1 ′ and M2 ′ according to the present embodiment, when two types of P-channel MOS transistor cells M1 ′ and M2 ′ are connected to each other, each P-channel MOS transistor cell M1 Since the N-well substrate contact regions 23 and 23 of '· M2' are abutted with each other, a differential pair with good symmetry can be formed by sharing and arranging the N-well substrate contact regions 23 and 23.
[0172]
[Embodiment 7]
The following will describe still another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 6 are given the same reference numerals, and descriptions thereof are omitted.
[0173]
In the present embodiment, a connection example in the y-axis direction of FIG. 13 in the P-channel MOS transistor cell 20 will be described.
[0174]
FIG. 20 shows an example in which two P-channel MOS transistor cells 20 are formed for every 8 fingers and are connected in the y-axis direction (perpendicular to the gate wiring (G1)) in FIG.
[0175]
In the figure, the structure is substantially the same as that of a 16-finger P-channel MOS transistor cell 20. As shown in the figure, not only between the N-well substrate contact regions 23 and 23 of adjacent P-channel MOS transistor cells 20 and 20, but also between the gate trunk lines (G) and (G) and the source trunk line (S) Since it is not necessary to lay out the connection between (S) and between the drain trunk lines (D) and (D), the efficiency of layout can be improved. Here, since the N-well substrate itself automatically overlaps by connecting the N-well substrate contact regions 23, 23, there is no need to worry about the design rule.
[0176]
Thus, in the structure of connectable P channel MOS transistor cells 20 and 20 according to the present embodiment, the gate trunk line (G) is formed to extend to the outermost peripheral end of the P channel MOS transistor cells 20 and 20. Therefore, the gate trunk lines (G) and (G) can be connected by matching the gate trunk lines (G) and (G) of the adjacent P-channel MOS transistor cells 20 and 20. Therefore, when the P-channel MOS transistor cells 20 and 20 are continuously connected in the opposing direction of the gate trunk lines (G) and (G), separate connection wirings may be omitted for the gate trunk lines (G) and (G). it can.
[0177]
In the structure of connectable P-channel MOS transistor cells 20 and 20 according to the present embodiment, each drain that supplies a signal to each drain wiring (D1) and source wiring (S1) connected to the drain region and the source region. The trunk line (D) and the source trunk line (D) are formed to extend to the outermost peripheral ends of the P-channel MOS transistor cells 20 and 20.
[0178]
Therefore, the drain trunk lines (D) and (D) are obtained by matching the drain trunk lines (D) and (D) of the adjacent P-channel MOS transistor cells 20 and 20 and butting the source trunk lines (D) and (D). And source trunk lines (D) and (D) can be connected. Therefore, when the P channel MOS transistor cells 20 and 20 are continuously connected in the opposing direction of the drain trunk lines (D) and (D) and the source trunk lines (D) and (D), the drain trunk lines (D) and (D A separate connection wiring can be omitted for D) and the source trunk lines (D) and (D).
[0179]
FIG. 21 is a simplified diagram of FIG. Furthermore, the CC sectional view taken on the line in FIG. 21 is shown in FIG. From the figure, by using the transistor structure of this embodiment, the gate trunk line (G), the substrate contact metal layer (subvdd) 23a, and the N-type diffusion region (n +) can be connected without being aware of the design rule. It turns out that it is. Similarly, by overlapping N-wells, it can be seen that they are electrically connected as one N-well without being restricted by design rules.
[0180]
[Embodiment 8]
The following will describe still another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 7 are given the same reference numerals, and descriptions thereof are omitted. The N-type diffusion region 32, the substrate contact region 33, and the transistor block (Sensitive Circuit) 34 described in the present embodiment are the same as the N-type diffusion region 2, the substrate contact region 3, the transistor block (Sensitive Circuit) 34 of the first embodiment. Circuit) 4 has the same function.
[0181]
The transistor cell applied in the connectable transistor cell structure of the present invention is not limited to a rectangle. That is, the present invention can be applied to other polygons.
[0182]
In the present embodiment, an N-channel MOS transistor cell configured with a triangle will be described.
[0183]
As shown in FIG. 23, the N-channel MOS transistor cell 30 of the present embodiment has an N-type diffusion region 32 that forms a drain region and a source region on a first substrate (P-substrate) 1 made of a P-type substrate. And a transistor block (Sensitive Circuit) 34 having a triangular structure composed of a gate wiring (G1) made of polysilicon wiring. The gate wiring (G1) generally uses a TOP metal layer having a relatively low resistance.
[0184]
Around the transistor block (Sensitive Circuit) 34, a substrate contact region 33 made of a P-type diffusion region for applying a substrate potential is formed.
[0185]
In the present embodiment, the substrate contact region 33 is formed so as to surround the outermost periphery of the N-channel MOS transistor cell 30 as shown in FIG. Thus, in the present embodiment, inter-element wiring between the substrate contact regions 33 of adjacent N-channel MOS transistor cells 30 can be omitted.
[0186]
By using the N-channel MOS transistor cell 30 according to the present embodiment, the necessity for wiring between elements and the restrictions on the design rules used at the time of layout design are drastically reduced, so that the layout work efficiency can be improved.
[0187]
On the other hand, in the present embodiment, like the square N-channel MOS transistor cell 10 described in the first embodiment, the first layer metal connected to the substrate contact region 33 is replaced with a triangular cell switching metal (not shown). It is possible to switch to.
[0188]
As a result, the N-channel MOS transistor cell 30 can be easily switched to the substrate contact cell with only a short-circuit wiring made of a first-layer metal using a triangular cell switching metal. As a result, the N channel MOS transistor cell 30 can be reused as a pseudo substrate contact cell.
[0189]
In the present embodiment, the substrate contact region 33 is formed in advance as a substrate frame, and the outermost periphery is formed by the substrate contact region 33. Therefore, a smooth N channel that does not affect the upper, lower, left, and right sides. Connection between the MOS transistor cells 30 is made possible.
[0190]
Further, the substrate contact region 33 can be expanded and contracted in accordance with the change in the wiring width of the source trunk line (S) and the drain trunk line (D), and the N-channel MOS transistor cell 30 according to the purpose without breaking the basic structure of the substrate frame. Can be formed.
[0191]
Also in this embodiment, the useless substrate contact region 33 is trimmed (not shown) in order to avoid the formation of parasitic capacitance with the source trunk line (S) and the drain trunk line (D).
[0192]
24 and 25 show an example in which the N-channel MOS transistor cells 30 are efficiently arranged. As shown in the figure, the gate trunk lines (G) and (G), the drain trunk lines (D) and (D), and the source trunk lines (S) and (S) are arranged so as to face each other, thereby facilitating wiring. I have to.
[0193]
In this embodiment,
Thus, in the structure of the connectable N channel MOS transistor cell 30 of the present embodiment, the N channel MOS transistor cell 30 has a polygonal shape including a square and a triangle in plan view. That is, the transistor cell shape is not limited to a general square, and may be a triangle or another polygon.
[0194]
[Embodiment 9]
The following will describe still another embodiment of the present invention with reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 8 are given the same reference numerals, and descriptions thereof are omitted. The P-channel MOS transistor cell 40 described in the present embodiment is functionally the same as the P-channel MOS transistor cell 20 described in the fifth embodiment. Therefore, the P-type diffusion region 42, the N-well substrate contact region 43, and the transistor block (Sensitive Circuit) 44 are the same as the P-type diffusion region 22, the N-well substrate contact region 23, the transistor block (Sensitive Circuit) of the fifth embodiment. ) 24 has the same function.
[0195]
The transistor cell applied in the connectable transistor cell structure of the present invention is not limited to a quadrangular shape as to the P-channel MOS transistor cell, and the present invention can be applied to other polygonal shapes.
[0196]
In the present embodiment, a P-channel MOS transistor cell configured with a triangle will be described.
[0197]
As shown in FIG. 26, the P-channel MOS transistor cell 40 of the present embodiment has a drain region and an N-well substrate 41 formed on a first substrate (P-substrate) made of a P-type substrate (not shown). It has a triangular transistor block (Sensitive Circuit) 44 composed of a P-type diffusion region 42 forming a source region and a gate wiring (G1) made of polysilicon wiring. The gate wiring (G1) generally uses a TOP metal layer having a relatively low resistance.
[0198]
Further, around the transistor block (Sensitive Circuit) 44, an N-well substrate contact region 43 composed of an N-type diffusion region for applying a substrate potential is formed.
[0199]
In the present embodiment, the N-well substrate contact region 43 is formed so as to surround the outermost periphery of the P-channel MOS transistor cell 40. Thus, in the present embodiment, the inter-element wiring between the N-well substrate contact regions 43 of the adjacent P channel MOS transistor cells 40 can be omitted.
[0200]
By using the P-channel MOS transistor cell 40 according to the present embodiment, the necessity of wiring between elements and the restrictions on the design rules used at the time of layout design are drastically reduced, so that the layout work efficiency can be improved.
[0201]
On the other hand, also in the present embodiment, the function of the transistor can be disabled by using a triangular cell switching metal (not shown) for the first layer metal (subvdd) 43a connected to the N-well substrate contact region 43. ing.
[0202]
Here, in the present embodiment, all of the wirings forming the gate wiring (G1), the source wiring (S1), and the drain wiring (D1) pass through the first layer in the lower metal layer. It is possible to short-circuit using layers.
[0203]
As a result, the triangular P-channel MOS transistor cell 40 can be easily switched to the triangular N-well substrate contact cell with only the wiring composed of a simple plate-like metal made of triangular cell switching metal. As a result, the P-channel MOS transistor cell 40 can be reused as a pseudo N-well substrate contact cell.
[0204]
In the present embodiment, since the outermost periphery of the triangular P-channel MOS transistor cell 40 is formed by the N-well substrate contact region 43, the smooth P-channel MOS transistor cell 40 between the upper, lower, left and right sides is formed. It can be connected.
[0205]
In addition, the N-well substrate contact region 43 can be expanded and contracted in accordance with the change in the wiring width of the source trunk line (S) and the drain trunk line (D), so that the basic structure of the N-well substrate frame can be adapted to the purpose without breaking. P channel MOS transistor cell 40 can be formed.
[0206]
In the present embodiment, the useless N-well substrate contact region 43 is trimmed (not shown) in order to avoid the formation of parasitic capacitances with the source trunk line (S) and the drain trunk line (D). ).
[0207]
Thus, in the structure of the connectable P-channel MOS transistor cell 40 of the present embodiment, the P-channel MOS transistor cell 40 has a polygonal shape including a square and a triangle in plan view. That is, the transistor cell shape is not limited to a general square, and may be a triangle or another polygon.
[0208]
The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.
[0209]
【The invention's effect】
As described above, the connectable transistor cell structure of the present invention is such that the substrate contact region is the outermost periphery of the transistor cell.
[0210]
Therefore, since the substrate contact region is formed so as to be the outermost periphery of the transistor cell, when connecting the transistor cells, the substrate contact regions existing on the outermost periphery are mutually connected by abutting the transistor cells. Touch and be electrically connected. For this reason, the trouble of wiring between the transistor cells between the substrate contact regions can be saved.
[0211]
In addition, since the substrate contact region exists on the outermost periphery, there is no gap between the transistor cells and between the substrate contact regions when the transistor cells are continuously arranged. Further, it is not necessary to newly form a substrate contact region. For this reason, transistor cells can be continuously arranged without any restriction of design rules at the time of layout design.
[0212]
Further, since the substrate contact region is present on the outermost periphery in any transistor cell, the transistor structures can be made completely equal, and the possibility of variation in threshold voltage can be reduced.
[0213]
Therefore, when transistor cells are continuously arranged, wiring between the transistor contact regions of the substrate contact region is avoided, and the substrate contact region is formed without being restricted by the design rules at the time of layout design. It is possible to provide a connectable transistor cell structure capable of reducing the above.
[0214]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein a first layer metal connected to the substrate contact region is provided, and the first layer metal is By short-circuiting at the first layer at the rising portion from the drain region / gate region / source region to each drain wiring / gate wiring / source wiring, the transistor function is disabled, and the transistor cell is made into a pseudo substrate contact block. It can be converted.
[0215]
Therefore, the transistor cell can be easily switched to the substrate contact cell by simply attaching the first metal layer for short-circuiting to the transistor cell. Therefore, by providing the transistor cells that are the substrate contact cells for stabilizing the transistors in the empty space on the layout pattern, it is possible to effectively use the cell empty space.
[0216]
On the other hand, when the transistor cell of the present invention is laid out in a space between each element circuit as a pseudo substrate contact cell, conversely, the first layer metal for short circuit of this pseudo substrate contact cell is used. By removing it, there is an effect that it can be easily reused as the original transistor cell.
[0217]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the drain wiring / source wiring connected to the drain region / source region is above the substrate contact region. Each drain trunk line / source trunk line for supplying a signal is disposed inside and above the substrate contact region of the transistor cell, and the width of the substrate contact region expands and contracts according to the width of each drain trunk line / source trunk line. Is formed.
[0218]
Therefore, since the structure of the substrate contact region is improved, versatile transistor cells can be formed without changing the basic structure of the substrate contact region.
[0219]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the substrate contact region supplies a signal to each drain wiring / source wiring connected to the drain region / source region. Each drain trunk line / inner region located below the source trunk line is opened as much as possible.
[0220]
Therefore, the parasitic capacitance formed between the first layer metal covering the substrate contact region and the drain trunk line / source trunk line is reduced by cutting out the substrate contact area located below the drain trunk line / source trunk line as much as possible. There is an effect that can be.
[0221]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the drain trunk line / source trunk line is arranged inside the outermost periphery of the transistor cell, thereby allowing mutual drain trunk lines / The substrate contact region width is set so as to satisfy the clearance rule between metals when the source trunk lines face each other.
[0222]
Therefore, since the transistor cells can be continuously arranged without worrying about the restriction of the design rule at the time of layout design, the layout efficiency is further improved.
[0223]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the gate trunk line for supplying a signal to the gate wiring connected to the gate region is provided at the outermost periphery of the transistor cell. It is formed to extend to.
[0224]
Therefore, the gate trunk lines can be connected by matching the gate trunk lines of adjacent transistor cells. Therefore, when the transistor cells are continuously connected in the opposite direction of the gate trunk line, there is an effect that a separate connection wiring can be omitted for the gate trunk line.
[0225]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein each drain trunk line / source that supplies a signal to each drain line / source line connected to the drain region / source region is provided. The trunk line is formed to extend to the outermost periphery of the transistor cell.
[0226]
Therefore, the drain trunk lines and the source trunk lines can be connected by butting the drain trunk lines of adjacent transistor cells and butting the source trunk lines. Therefore, when the transistor cells are continuously connected in the opposing direction of the drain trunk lines and the source trunk lines, there is an effect that a separate connection wiring can be omitted for the drain trunk lines and the source trunk lines.
[0227]
Further, the connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the transistor cells have various functions depending on the purpose of design, but the transistor cells are connected to each other. The substrate contact regions of the transistor cells having different functions can be shared by abutting the substrate contact regions of the transistor cells.
[0228]
Therefore, when transistor cells having different functions are connected to each other, the substrate contact regions of the transistor cells having different functions can be shared by matching the substrate contact regions of the respective transistor cells. By arranging them, it is possible to form a differential pair with good symmetry.
[0229]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the transistor cell is an N-channel MOS transistor formed in a first P-type semiconductor substrate. is there.
[0230]
Therefore, in the N-channel MOS transistor, when the transistor cells are continuously arranged, wiring between the transistor contact regions between the substrate contact regions is avoided, and the substrate contact region is formed without being restricted by the design rule at the time of layout design, There is an effect that it is possible to provide a connectable transistor cell structure that can reduce the possibility of variation in threshold voltage.
[0231]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein the transistor cell is isolated by a process option (Deep N-well) and an N-well. Formed in the mold semiconductor substrate.
[0232]
Therefore, the effect of noise generated in other circuits is cut off, and the transistor can operate at a stable substrate potential.
[0233]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the substrate contact region is an N-well substrate contact region.
[0234]
Therefore, in the P channel MOS transistor, when the transistor cells are continuously arranged, the wiring between the transistor contact regions between the substrate contact regions is avoided, and the substrate contact region is formed without being restricted by the design rule at the time of layout design, There is an effect that it is possible to provide a connectable transistor cell structure that can reduce the possibility of variation in threshold voltage.
[0235]
The connectable transistor cell structure of the present invention is the connectable transistor cell structure described above, wherein the transistor cell has a polygonal shape including a quadrangle and a triangle.
[0236]
According to the above invention, the transistor cell has a polygonal shape including a quadrangle and a triangle in plan view. That is, the transistor cell shape is not limited to a general square, and may be a triangle or another polygon. Also by this, the effect of the said invention can be show | played.
[Brief description of the drawings]
FIG. 1 is a plan view showing a layout pattern according to an embodiment of an N-channel MOS transistor cell according to the present invention.
2 is a cross-sectional view taken along line AA of FIG. 4 showing an N-channel MOS transistor cell disposed in a first substrate (P-substrate).
FIG. 3 is a plan view showing a layout pattern in which a substrate contact region of the N-channel MOS transistor cell is extracted.
FIG. 4 is a plan view showing a simplified layout pattern of the N-channel MOS transistor cell.
5 is a cross-sectional view taken along line AA of FIG. 4 showing an N-channel MOS transistor cell disposed in the Deep N-well.
FIG. 6 is a plan view showing a state in which an N-channel MOS transistor cell is switched to a substrate contact cell by cell switching metal.
FIG. 7 is a circuit diagram showing a differential pair composed of two N-channel MOS transistors (M1 and M2).
FIG. 8 is a plan view showing a state in which N channel MOS transistor cells (M1 ′, M2 ′) of the N channel MOS transistors (M1, M2) are connected and arranged.
FIG. 9 is a circuit diagram showing two differential pairs composed of four N-channel MOS transistors (M1 to M4).
FIG. 10 is a plan view showing a state in which N channel MOS transistor cells (M1 ′ to M4 ′) of the N channel MOS transistors (M1 to M4) are connected and arranged.
FIG. 11 is a plan view showing a state in which the N-channel MOS transistor cell is connected to a gate wiring in a vertical direction.
12 shows another embodiment of a connectable transistor cell structure according to the present invention, and is a cross-sectional view taken along line BB of FIG. 14 showing a P-channel MOS transistor cell.
FIG. 13 is a plan view showing a layout pattern of the P-channel MOS transistor cell.
FIG. 14 is a plan view showing a simplified layout pattern of the P-channel MOS transistor cell.
15 is a cross-sectional view taken along line B-B of FIG. 14 showing a state in which the P-channel MOS transistor cell is switched to the substrate contact cell by the cell switching metal.
FIG. 16 is a plan view showing a state in which a P-channel MOS transistor cell is switched to a substrate contact cell by a cell switching metal.
FIG. 17 is a plan view showing a layout pattern in which an N-well substrate contact region of the P-channel MOS transistor cell is extracted.
FIG. 18 is a circuit diagram showing a differential pair composed of two P-channel MOS transistors (M1 and M2).
FIG. 19 is a plan view showing a state in which P channel MOS transistor cells (M1 ′ and M2 ′) of the P channel MOS transistors (M1 and M2) are connected and arranged.
FIG. 20 is a plan view showing a state in which the P-channel MOS transistor cell is connected to the gate wiring in the vertical direction.
FIG. 21 is a plan view showing the simplified layout pattern of FIG. 20;
22 is a cross-sectional view taken along the line CC of FIG. 21, showing a state in which the P-channel MOS transistor cell is connected in the vertical direction to the gate wiring.
FIG. 23 is a plan view showing a triangular N-channel MOS transistor cell according to still another embodiment of the connectable transistor cell structure in the present invention.
FIG. 24 is a plan view showing a state in which the triangular N-channel MOS transistor cells are connected and arranged.
FIG. 25 is a plan view showing a state in which a large number of triangular N-channel MOS transistor cells are connected and arranged.
FIG. 26 is a plan view showing a triangular P-channel MOS transistor cell;
FIG. 27 is a circuit diagram showing an N-channel MOS transistor having a channel width W of α.
FIG. 28 is a circuit diagram showing an N-channel MOS transistor in which a channel width is divided in parallel with a minimum unit.
29 shows the structure of a conventional connectable transistor cell, and is a cross-sectional view taken along the line DD of FIG. 31 showing an N-channel MOS transistor cell arranged in the deep N-well.
FIG. 30 is a plan view showing an N-channel MOS transistor cell arranged in the deep N-well.
FIG. 31 is a plan view showing a simplified layout pattern of the P-channel MOS transistor cell.
FIG. 32 is a circuit diagram showing the P-channel MOS transistor.
FIGS. 33A and 33B are plan views showing a layout example of a MOS transistor having a three-terminal configuration including a gate, a source, and a drain, schematically showing a gate resistance. FIGS.
34 (a) and 34 (b) are circuit diagrams in consideration of gate resistance due to polysilicon wiring in the MOS transistor.
FIG. 35 is a plan view showing a state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 36 is a plan view showing another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 37 is a plan view showing still another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 38 is a plan view showing still another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 39 is a plan view showing still another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 40 is a circuit diagram showing N-channel MOS transistors (M1 to M4) limited to transistors of a differential input type LNA circuit.
[Explanation of symbols]
1. First substrate (P-substrate) (first P-type semiconductor substrate)
1a Second substrate (P-substrate2) (second P-type semiconductor substrate)
2 N-type diffusion region (drain region, source region)
3 Substrate contact area
3a 1st layer metal (subgnd)
3c Trimming (opening)
4 Transistor block (Sensitive Circuit)
5 Cell switching metal (first layer metal)
10 N-channel MOS transistor cell (transistor cell)
20 P-channel MOS transistor cell (transistor cell)
21 N-well substrate
22 P-type diffusion region (drain region, source region)
23 N-well substrate contact area
23a 1st layer metal (subvdd)
25 Cell switching metal (first layer metal)
30 N-channel MOS transistor cell (transistor cell)
40 P-channel MOS transistor cell (transistor cell)
D Drain trunk line
D1 Drain wiring
G Gate trunk line
G1 gate wiring
Gd1 dummy poly wiring
M1, M2, M3, M4 MOS transistors
M1 ', M2', M3 ', M4' MOS transistor cell
S source trunk line
S1 Source wiring

Claims (11)

In a connectable transistor cell structure having a drain region, a gate region, a source region, and a substrate contact region for stabilizing the operation of the transistor and arranged in parallel to constitute a semiconductor integrated circuit,
The substrate contact region is formed to be the outermost periphery of the transistor cell ,
Above the substrate contact region, each drain trunk line / source trunk line for supplying a signal to each drain wiring / source wiring connected to the drain region / source region is disposed inside and above the substrate contact region of the transistor cell. And
A connectable transistor cell structure, wherein the width of the substrate contact region is expanded and contracted according to the width of each drain main line / source main line . A first layer metal connected to the substrate contact region is provided;
The first layer metal disables the transistor function by short-circuiting in the first layer at the rising portion from the drain region / gate region / source region to each drain wiring / gate wiring / source wiring, thereby making the transistor cell 2. The connectable transistor cell structure according to claim 1, wherein the transistor cell structure can be converted into a pseudo substrate contact block. In the substrate contact region, an internal region located below each drain main line / source main line that supplies a signal to each drain wiring / source wiring connected to the drain region / source region is opened as much as possible. linkable transistor cell structure of claim 1, wherein. By arranging the drain trunk line / source trunk line inside the outermost periphery of the transistor cell, the substrate contact region width is set so as to satisfy the clearance rule between metals when the drain trunk line / source trunk line faces each other. linkable transistor cell structure according to any one of claims 1 to 3, characterized in that. Gate main line for supplying a signal to a gate wiring connected to the gate region, according to any one of claims 1 to 4, characterized in that it is formed to extend up to the outermost peripheral edge portion of the transistor cell Transistor cell structure that can be connected. The drain trunk line / source trunk line for supplying a signal to each drain wiring / source wiring connected to the drain region / source region is formed to extend to the outermost peripheral edge of the transistor cell. Item 6. The connectable transistor cell structure according to any one of Items 1 to 5 . Although the transistor cells have various functions depending on the purpose of design, when the transistor cells are connected to each other, the substrate contact regions of the transistor cells having different functions can be obtained by matching the substrate contact regions of the transistor cells. linkable transistor cell structure according to any one of claims 1 to 6, characterized in that the share. The connectable transistor cell structure according to any one of claims 1 to 7 , wherein the transistor cell is an N-channel MOS transistor formed in a first P-type semiconductor substrate. The transistor cells, a process option (Deep N-well) and a second linkable transistor cell of claim 8, wherein it is characterized in that is formed on the P-type semiconductor substrate which is isolated by the N-well Construction. It said substrate contact region, linkable transistor cell structure according to any one of claims 1 to 7, characterized in that a N- well substrate contact region. The transistor cells, linkable transistor cell structure according to any one of claims 1 to 10, wherein the planar shape is a polygon including a square and a triangle.

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