JP2004281467A - Linkable transistor cell structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a linkable transistor cell capable of eliminating wiring between the transistor cells of the substrate contact regions when continuously disposing transistor cells, forming a substrate contact region without restricting the design rules at designing a layout, and reducing the possibility of variations of the threshold voltage. <P>SOLUTION: Each n-channel MOS transistor cell 10 has a substrate contact region 3 for stabilizing the operations of a drain region, a gate region, a source region and a transistor; and the transistor cells 10 are arranged to forma a semiconductor integrated circuit. The transistor cell 10 is constituted so that the region 3 is positioned at the outermost portion of the transistor cell 10. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a connectable transistor cell structure having a drain region, a gate region, a source region, and a substrate contact region for stabilizing the operation of a transistor, and being connectable in parallel to form a semiconductor integrated circuit. . More particularly, the present invention relates to a method of designing a layout of a transistor cell, which relates to connection of respective substrate contact regions when connecting transistor cells.
[0002]
[Prior art]
As the life cycle of systems and sets has shrunk, the design period given to IC (Integrated Circuit) design is one step of shortening, and in order to protect the time to market (time to market), Efficient design methods are needed from time to time.
[0003]
However, for a design that cannot be automated, such as a layout design of a special analog circuit or the like, a more flexible layout method is required.
[0004]
Each design flow relating to the layout design of a conventional analog circuit mainly includes the following four stages.
(1) Cell generation stage: A cell design is determined based on connection information such as a net list and device parameters.
{Circle around (2)} Cell arranging stage: The cells are optimally arranged in consideration of the wiring efficiency and the wiring length.
{Circle over (3)} Wiring between cells: Wiring between cells while observing various wiring restrictions.
{Circle around (4)} Cell optimization stage: The layout design is verified, and the final rule check is performed.
[0005]
When forming a transistor cell according to the above design flow, using a structure that can minimize wiring between cells and prevent violation of design rules beforehand can greatly reduce the design period and improve efficiency. It is an important key to achieving a smooth design flow.
[0006]
In the layout design of a conventional transistor cell, first, at the cell stage, the channel width of the transistor is divided in parallel into minimum units to form a transistor cell having a desired number of fingers.
[0007]
More specifically, the N-channel MOS transistor M1 shown in FIG. 27 is divided into minimums so that the channel width W (= α) becomes a desired number of fingers. For example, in the case of an eight finger having eight gate (G1) wirings, as shown in FIG. 28, it is divided in parallel into the minimum unit of channel width Wmin = α / 8.
[0008]
When a large number of the N-channel MOS transistors M1 are designed in a layout, a transistor cell is a component of a chip that has a circuit pattern having a predetermined function so that it can be used repeatedly. Each of the transistor cells is continuously arranged so as to have a size required for design.
[0009]
A conventional typical transistor cell will be specifically described below with reference to FIGS.
(Transistor layout sample (1))
For example, in the first N-channel MOS transistor cell 100, as shown in FIG. 29, a second substrate (P-substrate2) 101a is formed on a first substrate (P-substrate) 101 made of a P-type semiconductor. For this purpose, a box-shaped substrate isolation region is formed by a process option Deep N-well 107a for forming a bottom surface and an N-well 107b for forming a side surface, and a power supply potential is further applied to the N-well 107b to reduce external noise. Cut off. On the second substrate, two N-type diffusion regions (n +) 102 for forming a drain region and a source region are provided, and a region of a P-type semiconductor (P-substrate 2) 101a therebetween is insulated. A transistor block (Sensitive Circuit) 104 having a structure covered with an oxide as a body and a gate wiring (G1) formed of a polysilicon wiring as a conductor (metal) is provided. The three structures of the metal (Metal), the oxide (Oxide), and the semiconductor (Semiconductor) are called a MOS structure. The gate wiring (G1) forms a gate region and a gate terminal in FIG.
[0010]
As shown in FIG. 30, a substrate contact region 103 made of a P-type diffusion region is formed around the transistor block (Sensitive Circuit) 104. The substrate contact region 103 includes a contact 103a and a contact 103a. A constant voltage (here, 0 V) is applied through the first layer metal 103b.
[0011]
The substrate contact region 103 is arranged as much as possible in a vacant space, and is supplied with a substrate potential to further stabilize the operation of the transistor.
[0012]
The substrate contact regions 103 are collectively arranged in an empty space, or the substrate contact regions 103 arranged in advance for each N-channel MOS transistor cell 100 are connected by metal wiring.
[0013]
On the other hand, the source wiring (S1) connected via a contact to the N-type diffusion region (n +) 102 forming the source region is made of metal, and short-circuited with the substrate contact region 103 as shown in FIG. Have been. Note that such a layout pattern of the first MOS transistor cell 100 is mainly used for a high-frequency transistor.
[0014]
Further, the drain trunk line (D) and the gate trunk line (G) have a structure in which the drain trunk line (D) and the gate trunk line (G) are randomly exposed so that they can be connected to adjacent cells.
[0015]
Note that this N-channel MOS transistor cell 100 is an example in which a transistor having a size of a minimum unit of channel width Wmin = 10 / 0.35 is laid out as shown in FIG.
[0016]
On the other hand, as shown in FIG. 29, dummy polysilicon wirings (Gd1) are additionally arranged on both sides of a gate wiring (G1) made of polysilicon wirings arranged continuously and evenly, which occurs when forming a polysilicon layer. An adverse effect due to variations in the gate wiring structure due to undercut is prevented.
[0017]
As described above, by arranging the substrate contact region 103 in FIG. 30 as much as possible in an empty space on the layout, the operation of the transistor in the second substrate (P-substrate 2) 101a is further stabilized, and the threshold It plays a role in suppressing variations.
[0018]
When the N-channel MOS transistor cell 100 shown in FIG. 29 is arranged in the second substrate (P-substrate 2) 101a, the drain region is formed on the second substrate (P-substrate 2) 101a. And two N-type diffusion regions (n +) 102 and 102 forming a source region, a gate wiring (G1) made of polysilicon wiring, and a P-type diffusion region for applying a substrate potential as shown in FIG. An N-channel MOS transistor cell 100 composed of (p +) 108 is formed.
[0019]
Here, the layout structure of the N-channel MOS transistor cell 100 shown in FIG. 31 will be additionally described with reference to FIGS.
[0020]
First, a layout example of the N-channel MOS transistor cell 100 having a three-terminal configuration including a gate terminal (gate wiring (G1)), a source terminal (source wiring (S1)), and a drain terminal (drain wiring (D1)) is shown in FIG. 33 (a). FIG. 34A shows a circuit diagram in which the gate resistance Rg due to the gate wiring (G1) made of the polysilicon wiring is taken into consideration.
[0021]
In the prior art, in order to reduce the gate wiring (G1) gate resistance Rg, as shown in FIG. 33B, the channel width W = α of the N-channel MOS transistor cell 100 is divided in parallel, and the channel width W ′ = As shown in FIG. 34B, a technique for reducing the gate resistance Rg to １ ／ or less by widely arranging the substrate contact region 103 at both ends of the gate wiring (G1) is set to α / 2. Used.
[0022]
When realizing a desired transistor size using the N-channel MOS transistor cell 100 shown in FIG. 29, the devices as shown in FIGS. 35 to 37 are mainly used. For example, FIG. 35 shows an example in which one cell is horizontally inverted and the drain trunks (D) of adjacent cells face each other, thereby omitting the wiring between the drain trunks (D). FIG. 36 is an example in which the wiring between the gate trunk lines (G) is omitted as in FIG. Usually, in order to prevent a design rule error in which the substrate contact 105 becomes floating, the inter-cell wiring 120 is performed at this stage.
[0023]
FIG. 37 is an example in which the wiring between the source wirings (S1) in the substrate contact region 103 is omitted.
(Transistor layout sample (2))
Next, a layout pattern of a second N-channel MOS transistor cell 200 according to another related art is shown in FIG.
[0024]
In this layout, a P-type transistor block 204 including N-type diffusion regions (n +) 202 and 202 forming a drain region and a source region on a P-type substrate and a gate wiring (G1) formed of polysilicon wiring is used. The substrate contact region 203 composed of a diffusion region is arranged in an island shape between the upper and lower ends of the transistor block 204 and the drain main line (D). The source wiring (S1) is drawn as a source trunk line (S) from the S1 wiring at the same potential as the N-type diffusion region (n +) forming the transistor. Further, the substrate contact regions 203 outside the above-mentioned dummy poly wiring outside the gate wiring (G1) made of a polysilicon wiring are arranged. It is pulled out with metal.
(Transistor layout example of University of California Berkeley)
Another conventional technique is a transistor layout example in Non-Patent Document 1 published in a doctoral dissertation at Berkeley University, California. FIG. 38 is a plan view showing a layout pattern limited to the transistors of the differential input type LNA circuit in FIG.
[0025]
As described above, the channel width of the MOS transistors (M1 to M4) constituting the LNA circuit is divided in parallel into minimum units, and the transistor cells 300 having a desired number of fingers are arranged in a matrix. The substrate contact region 303 is laid out later in a lattice shape.
[0026]
[Non-patent document 1]
Dennis Gee-Wai Yee, "A Design Methodology for Highly-Integrated Low-Power Receivers for Wireless Communications, University of California.
[0027]
[Problems to be solved by the invention]
However, in the N-channel MOS transistor cell 100 of the first prior art configured as described above, as shown in FIG. 37, the source / substrate potential common lead-out line 108 is connected to the substrate contact region 103, that is, the N-channel MOS transistor Since it protrudes from the cell 100, it is subject to troublesome design rules such as a clearance rule2 between the substrate contact regions 103 and a clearance rule1 between the contact holes, so that the cell structure itself needs to be changed or repaired with a metal layer. It may take extra time.
[0028]
Further, as shown in FIGS. 35 and 36, since the drain trunk line (D) and the gate trunk line (G) protrude from the N-channel MOS transistor cell 100, the design rule for the substrate contact regions 103 having the same function is reduced. It is necessary to connect later with the inter-cell wiring 120 to satisfy the condition.
[0029]
Next, in the N-channel MOS transistor 200 of the second prior art, as shown in FIG. 38, taking into account the constraints of the design rules used in the layout design, the substrate contact regions 203 are arranged in an island shape. It is necessary to wire each other. In this case, it is a troublesome and inefficient operation to perform the layout while paying attention to the rules of the intersection between the same-layer metals and the distance between adjacent metals.
[0030]
In addition, since the arrangement of the substrate contact regions 203 is asymmetrical geometrically, there is a possibility that the N channel MOS transistor cell 200 may have a stabilization or a variation in threshold value.
[0031]
On the other hand, in the layout example of the third prior art transistor cell 300... Published in a doctoral dissertation at the University of California, Berkeley, as shown in FIG. Thereafter, the substrate contact regions 303 are arranged in a lattice pattern between the cells. That is, as in the case of the first N-channel MOS transistor cell 100 and the second N-channel MOS transistor cell 200, taking into account the constraints of the design rules used at the time of the layout design and utilizing the empty space, it is troublesome and efficient. You have to do bad work.
[0032]
Further, in the layout samples of the first N-channel MOS transistor cell 100 and the second N-channel MOS transistor cell 200 according to the related art, the source wiring (S1) and the substrate terminal as the substrate are short-circuited. Generally, the substrate terminal (subgnd) of the N-channel transistor must be connected to the node of the lowest potential, and the substrate terminal (subvdd) of the P-channel transistor must be connected to the node of the highest potential. The contact that suppresses the substrate terminal (subvdd) is referred to as an “N-well substrate contact”.)
[0033]
In these cases, the potential of the source wiring (S1) may be different from the potential of the substrate terminal. Since the channel is a region between the gate wiring (G1) and the substrate or well, not only the potential difference between the gate and the source but also the potential difference between the source and the substrate affects the formation of the channel. That is, even if the gate-source voltage (V _GS ) Does not change, the source substrate voltage (V _SB ) Changes, the threshold voltage (V _T ) Changes. Source substrate voltage (V _SB ), The voltage is
V _T = V _T0 + Γ ｛(√ (2φ _f + V _SB ) -√φ _f ) ……… (1)
It is known that Where V _T0 Is the source substrate voltage (V _SB ) Is the threshold voltage when zero. γ and φ _f Is a constant determined by the process.
[0034]
That is, if the structure of the substrate contact differs from cell to cell on the layout, the threshold voltage (V _T ) May vary. Therefore, it is necessary to uniformly lay out the substrate contacts at the cell stage so that the substrate contacts do not need to be locally deformed after the cell arrangement.
[0035]
Further, the formation of the substrate contact regions 103 and 203 after the cell arrangement is greatly troublesome and inefficient due to the restrictions of the design rules used in the layout design.
[0036]
In the conventional layout method, it is normal to first arrange the core parts of the transistor cells and the like, and there is a possibility that a sufficient substrate area cannot be secured depending on the arrangement of the parts. Furthermore, since the transistor structure including the substrate contact tends to be non-uniform, there is a possibility that the threshold characteristics and noise resistance of the transistor may vary.
[0037]
In summary, when forming a MOS transistor cell according to the above design flow, the possibility of occurrence of human error, such as misplacement of the substrate contact region, connection error, connection error, parameter designation error, and the like becomes extremely high. There is a high possibility that the structure becomes non-uniform and the threshold voltage varies.
[0038]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has as its object to avoid wiring between transistor cells in a substrate contact region when arranging transistor cells successively, and to reduce the design rule during layout design. It is an object of the present invention to provide a connectable transistor cell structure capable of forming a substrate contact region without being restricted by the above and reducing the possibility of variation in threshold voltage.
[0039]
[Means for Solving the Problems]
In order to solve the above problems, the connectable transistor cell structure of the present invention has a drain region, a gate region, a source region, and a substrate contact region for stabilizing the operation of the transistor, and constitutes a semiconductor integrated circuit. Preferably, in the connectable transistor cell structure arranged in parallel, the substrate contact region is formed so as to be the outermost periphery of the transistor cell.
[0040]
According to the above invention, since the substrate contact region is formed so as to be the outermost periphery of the transistor cell, when connecting the transistor cells, the transistor cell is abutted against the substrate contact region existing at the outermost periphery. They are in contact with each other and are electrically connected. Therefore, the trouble of wiring between the transistor cells in the substrate contact regions can be omitted.
[0041]
In addition, when a transistor cell is continuously arranged, if a gap is formed between the transistor cells and a gap is formed between the substrate contact regions, a complicated design rule for processing the gap is required, and the transistor cell structure itself needs to be reconfigured. There is a risk that extra work and time will be required, such as changing or repairing the metal layer.
[0042]
However, in the present invention, since the substrate contact region exists at the outermost periphery, there is no gap between the transistor cells or between the substrate contact regions when the transistor cells are continuously arranged. Further, it is not necessary to newly form a substrate contact region. Therefore, the transistor cells can be continuously arranged without any restrictions of the design rules at the time of layout design.
[0043]
Further, if the structure of the substrate contact region is different for each transistor cell in the layout, the threshold voltage may vary.
[0044]
However, in the present invention, since the substrate contact region exists at the outermost periphery in any of the transistor cells, the transistor structures can be completely equalized, and the possibility of variation in threshold voltage can be reduced. .
[0045]
Therefore, when continuously arranging the transistor cells, wiring between the transistor cells in the substrate contact region is avoided, and the substrate contact region is formed without being restricted by the design rule at the time of the layout design. Can be provided.
[0046]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein a first layer metal connected to the substrate contact region is provided, and the first layer metal is: The transistor function is disabled by short-circuiting in the first layer at the rising portion from the drain region / gate region / source region to each drain wiring / gate wiring / source wiring, and the transistor cell is turned into a pseudo substrate contact block. It can be converted.
[0047]
According to the above invention, the first layer metal connected to the substrate contact region is short-circuited in the first layer at a rising portion from the drain region / gate region / source region to each drain line / gate line / source line. By doing so, the transistor function is invalidated, and the transistor cell can be converted to a pseudo substrate contact block.
[0048]
That is, in the present invention, by covering the first layer metal such that the gate, drain, source and substrate terminals are short-circuited over the entire transistor cell, the transistor cell can be reused as a pseudo substrate contact cell. As a result, the transistor cell is treated as a substrate contact cell.
[0049]
Therefore, by arranging a transistor cell serving as a substrate contact cell for stabilizing the substrate potential for arranging the transistor in an empty space on the layout pattern, the cell empty space can be effectively used.
[0050]
Specifically, for example, the first-layer metal is used for the gate wiring using a TOP metal having a relatively small resistance and the source wiring and the drain wiring that often use the second and third layers as the main signal lines. By paying attention to the fact that the upper layer is contact-coupled via the metal, the transistor cell can be easily switched to the substrate contact cell simply by mounting a simple short-circuit first layer metal on the transistor cell. .
[0051]
On the other hand, when the transistor cell of the present invention is laid out in a vacant space between the element circuits as a pseudo substrate contact cell, on the other hand, the first-layer metal for short circuit of the pseudo substrate contact cell is By removing it, it can be easily reused as the original transistor cell.
[0052]
In other words, by continuously arranging pseudo substrate contact cells in the empty space on the layout, the substrate contact cell can be replaced with, for example, N by only removing the first-layer metal for short-circuiting in response to various changes in transistor size. It can be efficiently reused as a channel MOS transistor. Unnecessary substrate contact cells serve to enhance the substrate potential in the empty space.
[0053]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure according to the above description, wherein the drain wiring and the source wiring connected to the drain region and the source region are provided above the substrate contact region. Each drain main line / source main line for supplying a signal is arranged inside and above the substrate contact region of the transistor cell, and the width of the substrate contact region expands and contracts according to each main line width of the drain main line / source main line. It is characterized by being formed.
[0054]
According to the above invention, the width of the substrate contact region is formed to expand and contract according to the width of each of the drain trunk line and the source trunk line.
[0055]
Therefore, for example, in response to a change in each trunk line width of the drain trunk line and the source trunk line obtained from the current value distributed for each transistor cell, the outermost substrate contact region can be easily formed while maintaining the basic substrate frame structure. It can expand and contract.
[0056]
That is, since the structure of the substrate contact region is improved in versatility, a variety of transistor cells can be formed without changing the basic structure of the substrate contact region. For example, different transistor cells can be easily formed for each operation current.
[0057]
In the connectable transistor cell structure according to the present invention, in the connectable transistor cell structure described above, the substrate contact region supplies a signal to each drain wiring / source wiring connected to the drain region / source region. An internal region located below each of the drain trunk lines and the source trunk lines is as open as possible.
[0058]
According to the above invention, the substrate contact region has an internal region located below each drain main line and source main line for supplying a signal to each drain wiring / source wiring connected to the drain region / source region as much as possible. It is open.
[0059]
Therefore, the parasitic capacitance formed between the first-layer metal covering the substrate contact region and the drain trunk line / source trunk line can be reduced by cutting out the substrate contact region located below the drain trunk line / source trunk line as much as possible. it can.
[0060]
Further, in the connectable transistor cell structure of the present invention, in the connectable transistor cell structure described above, the drain trunk line and the source trunk line are disposed inside the outermost periphery of the transistor cell, so that the drain trunk line and the source trunk line are connected to each other. The width of the substrate contact region is set so as to satisfy a clearance rule between metals when the source trunk lines face each other.
[0061]
According to the above invention, the drain main line and the source main line are arranged inside the outermost periphery of the transistor cell, so that the substrate contact region meets the metal-to-metal clearance rule when the mutual drain main line and the source main line face each other. The width is set.
[0062]
Therefore, the transistor cells can be continuously arranged without worrying about the restrictions of the design rules at the time of layout design, so that the layout efficiency is further improved.
[0063]
In the connectable transistor cell structure according to the present invention, in the connectable transistor cell structure described above, a gate trunk line for supplying a signal to a gate wiring connected to the gate region is provided at an outermost peripheral end of the transistor cell. It is characterized by being formed so as to extend to the right.
[0064]
According to the above invention, since the gate trunk is formed to extend to the outermost peripheral end of the transistor cell, the gate trunk can be connected to each other by abutting the gate trunks of adjacent transistor cells. Therefore, when connecting the transistor cells continuously in the direction opposite to the gate trunk line, a separate connection wiring for the gate trunk line can be omitted.
[0065]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein each drain main line and source for supplying a signal to each drain wiring and source wiring connected to the drain region and the source region are provided. The main line is characterized in that it extends to the outermost peripheral end of the transistor cell.
[0066]
According to the above invention, each drain trunk / source trunk supplying a signal to each drain wiring / source wiring connected to the drain region / source region is formed to extend to the outermost peripheral end of the transistor cell. I have.
[0067]
For this reason, the drain trunk lines and the source trunk lines can be connected to each other by abutting the drain trunk lines and the source trunk lines of the adjacent transistor cells. Therefore, when the transistor cells are continuously connected in the direction in which the drain trunk lines and the source trunk lines are opposed to each other, it is possible to omit a separate connection wiring for the drain trunk line and the source trunk line.
[0068]
Further, the connectable transistor cell structure according to the present invention is the same as the connectable transistor cell structure described above, wherein the transistor cells have various functions depending on the purpose of design, but the transistor cells are connected to each other. The substrate contact regions of the transistor cells having different functions can be shared by abutting the substrate contact regions of the respective transistor cells.
[0069]
According to the above invention, when the transistor cells having different functions are connected to each other, the substrate contact regions of the transistor cells having different functions can be shared by abutting the substrate contact regions of the respective transistor cells. , A differential pair having good symmetry can be formed.
[0070]
Further, the connectable transistor cell structure according to the present invention is the above connectable transistor cell structure, wherein the transistor cell is an N-channel MOS transistor formed in a first P-type semiconductor substrate. Features.
[0071]
According to the above invention, the transistor cell is formed by the N-channel MOS transistor formed in the first P-type semiconductor substrate. Therefore, in the N-channel MOS transistor, when the transistor cells are continuously arranged, the substrate contact region To provide a connectable transistor cell structure that avoids wiring between transistor cells, forms a substrate contact region without being restricted by design rules during layout design, and can reduce the possibility of variation in threshold voltage. Can be.
[0072]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure according to the above description, wherein the transistor cell is separated by a process option (Deep N-well) and an N-well. It is formed in a mold semiconductor substrate.
[0073]
According to the above invention, since the transistor cell is formed in the second P-type semiconductor substrate separated by the process option (Deep N-well) and the N-well, it is generated by another circuit. The influence of noise is cut off, and the transistor can operate at a stable substrate potential.
[0074]
Further, the connectable transistor cell structure according to the present invention is characterized in that, in the connectable transistor cell structure described above, the substrate contact region is an N-well substrate contact region.
[0075]
According to the above invention, the substrate contact region is an N-well substrate contact region. Therefore, in a P-channel MOS transistor, when arranging the transistor cells continuously, it is possible to avoid the wiring between the transistor cells of the substrate contact regions, to form the substrate contact region without being restricted by the design rule at the time of layout design, A connectable transistor cell structure that can reduce the possibility of voltage variations can be provided.
[0076]
According to the connectable transistor cell structure of the present invention, in the connectable transistor cell structure described above, the transistor cell is characterized in that the planar shape is a polygon including a square and a triangle.
[0077]
According to the above invention, the transistor cell has a polygonal planar shape including a square and a triangle. That is, the shape of the transistor cell is not limited to a general square, but may be a triangle or another polygon.
[0078]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.
[0079]
An N-channel MOS transistor cell 10 as a transistor cell to which the connectable transistor cell structure of the present embodiment is applied, as shown in FIG. 2, is on a first substrate (P-substrate) 1 made of a P-type substrate. And a transistor block (Sensitive Circuit) 4 composed of N-type diffusion regions 2 forming a drain region and a source region and a polysilicon wiring forming a gate wiring (G1). The above-mentioned gate (G1) wiring generally uses a TOP metal layer having a relatively small resistance.
[0080]
In the present embodiment, as shown in FIG. 1, substrate contact region 3 is formed to be the outermost periphery of N-channel MOS transistor cell 10. That is, as shown in FIG. 3, the substrate contact region 3 is formed in a frame shape at the outermost periphery of the N-channel MOS transistor cell 10. Thereby, the outer peripheral edge of N-channel MOS transistor cell 10 and the outer peripheral edge of substrate contact region 3 match. Also, as shown in FIG. 1, the other components do not protrude from the outermost periphery of the N-channel MOS transistor cell 10.
[0081]
That is, in the present embodiment, a substrate frame in which the substrate contact regions 3 are all connected in advance is formed, and as described in later-described Embodiments 2 and 3, etc., a conventional technique is used. It is not necessary to connect the metal between the substrate contact regions 3 shown in FIGS. 33, 34 and 36 like the inter-cell wiring 120. That is, it is possible to omit the inter-element wiring between the substrate contact regions 3, 3 between the adjacent N-channel MOS transistor cells 10, 10.
[0082]
Further, by using the N-channel MOS transistor cell 10 according to the present embodiment, the necessity of wiring between elements and the restrictions on design rules used in layout design are drastically reduced, so that layout work efficiency can be improved. .
[0083]
In this embodiment, as shown in FIG. 2, dummy polysilicon wirings Gd1 are additionally arranged on both sides of a gate wiring (G1) made of polysilicon wirings which are continuously and evenly arranged. The structure is such that an adverse effect due to manufacturing variation of the gate wiring (G1) due to undercut that occurs during layer formation is prevented.
[0084]
Also, based on the arrangement shown in FIG. 27, which is an explanatory diagram of the prior art, the order of the source wiring (S1), the gate wiring (G1), the drain wiring (D1), the gate wiring (G1), and the source wiring (S1). And a repetitive arrangement structure in which the legs are opened centering on the overlapping drain wiring (D1). Such a structure is generally called a common centroid structure.
[0085]
FIG. 4 is a simplified view of the N-channel MOS transistor cell 10 shown in FIG. 1, and FIG. 5 is a cross-sectional view in which the N-channel MOS transistor cell 10 is arranged in the second substrate (1a). A transistor block (Sensitive Circuit) 4 composed of two N-type diffusion regions 2 forming a source region and a drain region and a polysilicon wiring serving as a gate wiring (G1), and a transistor block (Sensitive Circuit) 4 It has a substrate contact region 3 formed of a P-type diffusion region for providing a substrate potential formed on the outer peripheral portion.
[0086]
The framework N-type semiconductor region (N-well) 7b forming the outer wall is set to a power supply voltage by the diffusion contact hole 7c, the first to third metal layers 7d and the top metal layer 7f, the intermetal contact hole 7e, and the like. , And is shielded from the first substrate (P-substrate) 1 affected by other element circuits.
[0087]
The substrate contact region 3 is connected to a first-layer metal (subgnd) 3a.
[0088]
By the way, in the N-channel MOS transistor cell 10 of the present embodiment, the first layer metal (subgnd) 3a connected to the substrate contact region 3 is replaced with a cell switching metal as shown by a two-dot chain line in FIGS. 5 can be switched.
[0089]
As a result, as shown in FIG. 6, the N-channel MOS transistor cell 10 can be easily switched to the substrate contact cell only with the wiring composed of a simple plate-shaped metal formed by the cell switching metal 5. In the substrate contact cell, the drain region / gate region / source region and the substrate contact region 3 are all short-circuited by covering the cell switching metal 5 in the first layer over the entire N-channel MOS transistor cell 10. As a result, the N-channel MOS transistor cell 10 loses the transistor function, and the N-channel MOS transistor cell 10 is treated as a substrate contact cell. As a result, the N-channel MOS transistor cell 10 can be reused as a pseudo substrate contact cell.
[0090]
Further, since the outermost periphery is formed by the substrate contact region 3, a smooth connection between the N-channel MOS transistor cells 10 regardless of up, down, left and right can be achieved. Furthermore, the substrate contact region 3 can expand and contract as shown by the dashed arrows at both ends in FIG. 3 in accordance with the change in the wiring width of the source trunk line (S) and the drain trunk line (D), without breaking the basic structure of the substrate frame. It is possible to form the N-channel MOS transistor cell 10 according to the purpose. Further, as shown in FIG. 3, in order to avoid formation of a parasitic capacitance with the source main line (S) and the drain main line (D), a useless substrate contact region 3 is trimmed (cut out) 3c.
[0091]
FIG. 6 is a diagram showing a means for switching the N-channel MOS transistor cell 10 according to the present embodiment to a substrate contact cell.
[0092]
As shown in FIG. 6, the first layer metal (subgnd) 3a described with reference to FIGS. 2 and 5 is replaced with a cell switching metal 5 as the first layer metal to cover the transistor block (Sensitive Circuit) 4. As a result, the substrate contact region 3 is short-circuited with the gate wiring (G1), the source wiring (S1), and the drain wiring (D1), so that it is possible to easily switch to the substrate contact cell. Here, the wirings forming the gate wiring (G1), the source wiring (S1), and the drain wiring (D1) always pass through the cell switching metal 5 in the lower metal layer. Can be used to short circuit.
[0093]
As described above, in the structure of connectable N-channel MOS transistor cell 10 of the present embodiment, substrate contact region 3 is formed so as to be the outermost periphery of N-channel MOS transistor cell 10, so that N-channel MOS transistor cell 10 is formed. When the transistor cells 10 are connected to each other, the N-channel MOS transistor cells 10 are brought into contact with each other, so that the outermost substrate contact regions 3 are in contact with each other and are electrically connected. For this reason, the trouble of wiring the transistor cell between the substrate contact regions 3 and 3 can be omitted.
[0094]
When the N-channel MOS transistor cells 10 are continuously arranged, if a gap is formed between the N-channel MOS transistor cells 10 and a gap is formed between the substrate contact regions 3, the gap is processed. Due to troublesome design rules, extra work and time may be required, such as re-modification of the structure of the N-channel MOS transistor cell 10 itself or repair with a metal layer.
[0095]
However, in the present embodiment, since substrate contact region 3 exists at the outermost periphery, when N channel MOS transistor cells 10 are continuously arranged, between N channel MOS transistor cells 10 and between substrate contact regions 3 and 3. There is no gap in the space. Further, it is not necessary to newly form the substrate contact region 3. Therefore, N-channel MOS transistor cells 10 can be continuously arranged without any restrictions on design rules during layout design.
[0096]
If the structure of the substrate contact region 3 is different for each N-channel MOS transistor cell 10 on the layout, the threshold voltage may vary.
[0097]
However, in the present embodiment, since substrate contact region 3 exists at the outermost periphery in any of N-channel MOS transistor cells 10, it is possible to make the respective transistor structures completely equal, and to reduce the variation in threshold voltage. Possibilities can be reduced.
[0098]
Therefore, when the N-channel MOS transistor cells 10 are continuously arranged, wiring between the N-channel MOS transistor cells 10 in the substrate contact regions 3 is avoided, and the layout rules are not restricted by design rules. It is possible to provide a structure of the connectable N-channel MOS transistor cell 10 in which the substrate contact region 3 is formed and the possibility of variation in threshold voltage can be reduced.
[0099]
Further, in the structure of the connectable N-channel MOS transistor cell 10 of the present embodiment, the first layer metal (subgnd) 3a connected to the substrate contact region 3 is formed from the drain region / gate region / source region to each drain wiring. (D1) The transistor function is invalidated by short-circuiting in the first layer at the rising portion to the gate line (G1) and the source line (S1), and the N-channel MOS transistor cell 10 becomes a pseudo substrate contact block. Conversion is possible.
[0100]
That is, in the present embodiment, the N-channel MOS transistor cell 10 is simulated by covering the cell switching metal 5 so that the gate, drain, source, and substrate terminals are short-circuited to the entire N-channel MOS transistor cell 10. It can be reused as a substrate contact cell. As a result, the N-channel MOS transistor cell 10 invalidates the transistor function of the N-channel MOS transistor cell 10 because the drain region, the gate region, the source region, and the substrate contact region 3 are all short-circuited. The transistor cell 10 will be treated as a substrate contact cell.
[0101]
Therefore, by arranging N-channel MOS transistor cell 10 which is a substrate contact cell for stabilizing the substrate potential on which the transistor is arranged in an empty space on the layout pattern, effective use of the cell empty space is achieved. be able to.
[0102]
Specifically, for example, in addition to a plate-shaped metal using the first layer metal (subgnd) 3a, a gate wiring (G1) using a TOP metal having a relatively small resistance, and a second or third layer as a main signal line. Of the source wiring (S1) and the drain wiring (D1), which are often used, are connected to the upper layer via a plate-shaped metal using the first-layer metal. The N-channel MOS transistor cell 10 can be easily switched to the substrate contact cell simply by mounting the cell switching metal 5 for the N-channel MOS transistor cell 10.
[0103]
On the other hand, when the N-channel MOS transistor cell 10 of the present embodiment is laid as a pseudo-substrate contact cell in an empty space between the element circuits, conversely, when the pseudo-substrate contact cell is short-circuited. By removing the cell switching metal 5, the N-channel MOS transistor cell 10 can be easily reused.
[0104]
In other words, by continuously arranging pseudo substrate contact cells in the empty space on the layout, the substrate contact cells can be reduced to N by only removing the short-circuit cell switching metal 5 in response to various changes in transistor size. The channel MOS transistor cell 10 can be efficiently reused. Unnecessary substrate contact cells serve to enhance the substrate potential in the empty space.
[0105]
Further, in the structure of the connectable N-channel MOS transistor cell 10 of the present embodiment, the width of the substrate contact region 3 is formed by expanding and contracting according to the respective trunk line widths of the drain trunk line (D) and the source trunk line (S). Is done.
[0106]
Therefore, for example, the structure of the basic substrate frame is maintained with respect to the change of each trunk line width of the drain trunk line (D) and the source trunk line (S) obtained from the current value distributed for each N-channel MOS transistor cell 10. The outermost substrate contact region 3 can be easily expanded and contracted as it is.
[0107]
In other words, since the structure of the substrate contact region 3 is improved in versatility, the N-channel MOS transistor cell 10 with various variations can be formed without changing the basic structure of the substrate contact region 3. For example, different N-channel MOS transistor cells 10 can be easily formed for each operation current.
[0108]
In the structure of the connectable N-channel MOS transistor cell 10 according to the present embodiment, the substrate contact region 3 transmits a signal to each drain wiring (D1) and source wiring (S1) connected to the drain region and the source region. The portion located below each of the drain main lines (D) and the source main lines (S) to be supplied is opened as much as possible.
[0109]
Therefore, by cutting out as much as possible the substrate contact region 3 located below the drain trunk line (D) and the source trunk line (S), the first layer metal (subgnd) 3a covering the substrate contact region 3 and the drain trunk line (D) The parasitic capacitance formed between the source trunk lines (S) can be reduced.
[0110]
In the structure of the connectable N-channel MOS transistor cell 10 according to the present embodiment, the N-channel MOS transistor cell 10 is formed by an N-channel MOS transistor formed in the first substrate (P-substrate) 1. Therefore, in the N-channel MOS transistors, when the N-channel MOS transistor cells 10 are continuously arranged, the wiring between the N-channel MOS transistor cells 10 in the substrate contact regions 3.3 is avoided, and the design rule is The structure of the connectable N-channel MOS transistor cell 10 that can form the substrate contact region 3 without restriction and reduce the possibility of variation in threshold voltage can be provided.
[0111]
Further, in the structure of the connectable N-channel MOS transistor cell 10 of the present embodiment, the N-channel MOS transistor cell 10 includes a second substrate (Deep N-well 7a) and a second substrate (N-well 7b) separated by an N-well 7b. Since it is formed in the P-substrate 2) 1a, the influence of noise generated by other circuits is cut off, and the transistor can operate at a stable substrate potential.
[0112]
[Embodiment 2]
The following will describe another embodiment of the present invention with reference to FIGS. For convenience of description, members having the same functions as those shown in the drawings of the first embodiment are given the same reference numerals, and descriptions thereof will be omitted.
[0113]
In the present embodiment, an example in which N-channel MOS transistor cells 10 are connected in the x-axis direction in FIG. 1 of the first embodiment, that is, in the extension direction of the gate line (G1) will be described.
[0114]
FIG. 7 is a circuit diagram of a differential pair composed of N-channel MOS transistors M1 and M2 having two kinds of roles, in which the source wiring (S1) is open for inserting an impedance element.
[0115]
FIG. 8 shows that the channel width W = α of the two types of N-channel MOS transistors M1 and M2 shown in FIG. 7 is divided into 16 (Wmin = α / 16), respectively, and 8 fingers (W ′ = 8 × Wmin) In each case, N-channel MOS transistor cells M1 'and M2', which are the N-channel MOS transistor cells 10 according to the present embodiment, are formed (M1 '= M2' = 2 * W '), and the x-axis direction shown in FIG. In other words, they are connected in the same direction as the gate wiring (G1) (extending direction of the gate wiring (G1)).
[0116]
As shown in the figure, the N-channel MOS transistor cells M1 'and M2' are arranged in a cross shape and have a geometric origin symmetrical structure. 7, the variations between the N-channel MOS transistor M1 and the N-channel MOS transistor M2 in FIG. 7 are equal.
[0117]
In addition, by using the configuration according to the present embodiment, it is possible to easily connect substrate contact regions 3.3 even between different transistor cells like N-channel MOS transistor cells M1 ′ and M2 ′ shown in FIG. Becomes possible. Further, when the source trunk line (S) of the N-channel MOS transistor cell M1 'and the drain trunk line (D) of the N-channel MOS transistor M2' are connected in the x-axis direction at the cell stage, the substrate contact region 3. 3, the clearance rule between the adjacent metal wirings can be satisfied without concern for the restriction of the design rule used in the layout design. That is, the source trunk line (S) and the drain trunk line (D) must not be in contact with each other and must not be too close. In this regard, when the N-channel MOS transistor cells M1 ′ and M2 ′ are connected, the substrate contact regions 3.3 with a constant interval width exist between them, so that the substrate contact regions 3.3 with a constant interval width do not exist. Compared to the case, there is no need to worry about the distance between the source trunk (S) and the drain trunk (D).
[0118]
The final substrate wiring may be drawn from any position of the substrate contact region 3 at both ends of the connected N-channel MOS transistor cells M1 'and M2'.
[0119]
As described above, in the structure of the connectable N-channel MOS transistor cells M1 'and M2' of the present embodiment, the N-channel in the outer ends of the drain trunk line (D) and the source trunk line (S) and in the substrate contact region 3 The planar spacing between the outermost periphery of the MOS transistor cells M1 ′ and M2 ′ is such that the N-channel MOS transistor cells M1 ′ and M2 ′ are continuous in the direction in which the gate line (G1) connected to the gate region extends. The width of the substrate contact region is set in advance so as to satisfy the intermetal clearance rule when the drain trunk line (D) and the source trunk line (S) face each other by being connected.
[0120]
Therefore, the N-channel MOS transistor cells M1 'and M2' can be continuously arranged in a cross shape without worrying about design rule restrictions at the time of layout design, so that layout efficiency is further improved.
[0121]
In the structure of the connectable N-channel MOS transistor cells M1 'and M2' of the present embodiment, when the N-channel MOS transistor cells M1 'and M2' having different functions are connected to each other, The substrate contact regions 3.3 of the N-channel MOS transistor cells M1 'and M2' having different functions can be shared by abutting the substrate contact regions 3.3 of M1 'and M2'. , A differential pair having good symmetry can be formed.
[0122]
[Embodiment 3]
The following will describe still another embodiment of the present invention with reference to FIGS. 9 and 10. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 and 2 are given the same reference numerals, and descriptions thereof are omitted.
[0123]
In this embodiment, an example of connection of four types of N-channel MOS transistor cells in the x-axis direction will be described.
[0124]
FIG. 9 is a circuit diagram of two differential pairs including four N-channel MOS transistors (M1 to M4) of a mixing unit conventionally used in a Gilbert cell mixer.
[0125]
FIG. 10 shows that the channel width (W = 80) of the two transistors shown in FIG. 9 is divided into eight (Wmin = 80/8 = 10), and the present embodiment is performed for every eight fingers (W ′ = 8 × Wmin). An N-channel MOS transistor cell M1 ', M2', M3 ', M4', which is the N-channel MOS transistor cell 10 according to mode 1, is formed (M1 '= M2' = M3 '= M4' = W '). The N-channel MOS transistor cells M1 'and M4' and the N-channel MOS transistor cells M2 'and M3' are connected in the x-axis direction shown, that is, in the same direction as the gate line (G1) (extending direction of the gate line (G1)). This is an example of arrangement. Note that the present invention is not limited to the above combination, and for example, the N-channel MOS transistor cells M1 'and M2' and the N-channel MOS transistor cells M3 'and M4' may be connected and arranged.
[0126]
In FIG. 10, N-channel MOS transistor cells M1 'and M2' as a differential pair and N-channel MOS transistor cells M3 'and M4' as a differential pair are arranged so as to be symmetrical. Therefore, even if the process variation occurs in the direction as indicated by the lower arrow in the figure, the N-channel MOS transistor cells M1 'and M2' as a differential pair and the N-channel MOS transistor cells as a differential pair The variations of M3 'and M4' become equal.
[0127]
Further, by using the configuration according to the present embodiment, the substrate contact region 3 can be easily formed between different transistor cells such as N-channel MOS transistor cells M1 'and M4' and N-channel MOS transistor cells M2 'and M3'.・ 3 can be connected.
[0128]
Further, when the source trunk line (S) of the N-channel MOS transistor cell M1 'and the drain trunk line (D) of the N-channel MOS transistor M4' are connected in the x-axis direction at the cell stage, the substrate contact region 3. 3, the clearance rule between the adjacent metal wirings can be satisfied without concern for the restriction of the design rule used in the layout design.
[0129]
Further, the final substrate wiring is formed by the positions of the substrate contact regions 3.3 at both ends of the connected N-channel MOS transistor cells M1 'and M4' and the substrate contact regions 3 at both ends of the N-channel MOS transistor cells M2 'and M3'.・ It is only necessary to pull out from any position 3 and the like.
[0130]
[Embodiment 4]
Another embodiment of the present invention will be described below with reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to third embodiments are denoted by the same reference numerals, and description thereof is omitted.
[0131]
In this embodiment, an example of connection in the y-axis direction in FIG. 1 in an N-channel MOS transistor cell will be described.
[0132]
FIG. 11 shows an example in which two N-channel MOS transistors are formed for every eight fingers and connected in the y-axis direction (perpendicular to the gate line (G1)) in FIG.
[0133]
In this figure, the structure is substantially the same as that of the 16-finger N-channel MOS transistor cell 10 described in the second and third embodiments. As shown in the drawing, not only between the substrate contact regions 3.3 of the adjacent N-channel MOS transistor cells 10, but also between the gate trunks (G) and (G), and between the source trunks (S) and (S). Since there is no need to lay out the connections between the drain trunk lines (D) and (D), the layout efficiency can be improved.
[0134]
As described above, in the structure of the connectable N-channel MOS transistor cells 10 of the present embodiment, the gate trunk line (G) is formed to extend to the outermost end of the N-channel MOS transistor cells 10. Therefore, the gate trunks (G) and (G) can be connected to each other by abutting the gate trunks (G) and (G) of the adjacent N-channel MOS transistor cells 10. Therefore, when the N-channel MOS transistor cells 10 are continuously connected in the direction opposite to the gate trunk lines (G) and (G), separate connection wiring for the gate trunk lines (G) and (G) can be omitted. it can.
[0135]
In the structure of the connectable N-channel MOS transistor cells 10 of the present embodiment, each drain for supplying a signal to each drain wiring (D1) / source wiring (S1) connected to the drain region / source region. The trunk line (D) and the source trunk line (S) are formed to extend to the outermost ends of the N-channel MOS transistor cells 10.
[0136]
For this reason, the drain trunks (D) and (D) of the adjacent N-channel MOS transistor cells 10 and 10 are matched with each other and the source trunks (S) and (S) are matched with each other. And source trunk lines (S) and (S) can be connected to each other. Therefore, when the N-channel MOS transistor cells 10 are continuously connected in the direction in which the drain trunks (D) and (D) and the source trunks (S) and (S) face each other, the drain trunks (D) and (D) ) Separate connection wiring can be omitted for each other and for the source trunk lines (S) and (S).
[0137]
[Embodiment 5]
The following will describe still another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of the above-described first to fourth embodiments are given the same reference numerals, and descriptions thereof are omitted.
[0138]
In this embodiment, a P-channel MOS transistor cell will be described.
[0139]
As shown in FIG. 12, a P-channel MOS transistor cell 20 of the present embodiment has a drain region and a source on an N-well substrate 21 formed on a first substrate (P-substrate) 1 made of a P-type substrate. A transistor block (Sensitive Circuit) 24 composed of a P-type diffusion region 22 forming a region and a gate wiring (G1) made of polysilicon wiring is provided. In general, a TOP metal layer having a relatively small resistance is used for the gate wiring (G1).
[0140]
An N-well substrate contact region 23 formed of an N-type diffusion region for applying a substrate potential is formed around the transistor block (Sensitive Circuit) 24.
[0141]
In the present embodiment, the N-well substrate contact region 23 is formed so as to surround the outermost periphery of the P-channel MOS transistor cell 20, as shown in FIG. Thereby, in the present embodiment, it is possible to omit the inter-element wiring between the N-well substrate contact regions 23 of the adjacent P-channel MOS transistor cells 20.
[0142]
By using the P-channel MOS transistor cell 20 according to the present embodiment, the necessity of wiring between elements and the restrictions on design rules used in layout design are drastically reduced, so that layout work efficiency can be improved.
[0143]
FIG. 14 is a diagram showing a simplified version of P-channel MOS transistor cell 20 of FIG.
[0144]
On the other hand, in the present embodiment, the first layer metal (subvdd) 23a connected to the N-well substrate contact region 23 shown in FIG. 15 is used as the first layer metal as shown by a two-dot chain line in FIG. It is possible to switch to the cell switching metal 25.
[0145]
Here, in this embodiment, the wirings forming the gate wiring (G1), the source wiring (S1), and the drain wiring (D1) are all lower metal layers and always pass through the first layer. It is possible to short-circuit using layers.
[0146]
Thus, as shown in FIG. 16, the P-channel MOS transistor cell 20 can be easily switched to the N-well substrate contact cell only by the wiring composed of a simple plate-shaped metal formed by the cell switching metal 25. Note that the N-well substrate contact cell is defined as a drain region, a gate region, a source region, and an N-well substrate contact region by covering the cell switching metal 25 in the first layer over the entire P-channel MOS transistor cell 20. 23 are all short-circuited. As a result, the P-channel MOS transistor cell 20 loses the transistor function and is treated as an N-well substrate contact cell. As a result, the P-channel MOS transistor cell 20 can be reused as an N-well substrate contact cell in a pseudo manner, so that the power supply potential of the N-well can be enhanced.
[0147]
FIG. 17 is a plan view of a layout pattern in which the N-well substrate contact region 23 of FIG. 12 is extracted. As shown in the figure, an N-well substrate frame is formed in which all N-well substrate contact regions 23 are connected in advance. In addition, since the outermost periphery is formed by the N-well substrate contact region 23, smooth connection between the P-channel MOS transistor cells 20 irrespective of up, down, left and right is enabled.
[0148]
17, the N-well substrate contact region 23 can expand and contract according to the change in the wiring width of the source trunk line (S) and the drain trunk line (D) shown in FIG. It is possible to form the P-channel MOS transistor cell 20 according to the purpose without breaking the basic structure of the well substrate frame.
[0149]
Further, in the present embodiment, in order to avoid formation of a parasitic capacitance with the source main line (S) and the drain main line (D), useless N-well substrate contact region 23 is trimmed (cut out) 23c.
[0150]
Thus, in the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the substrate contact region is the N-well substrate contact region 23. Therefore, in the P-channel MOS transistor, when the P-channel MOS transistor cells 20 are continuously arranged, wiring between the P-channel MOS transistor cells 20 in the N-well substrate contact regions 23 is avoided, and the layout is designed at the time of layout design. By forming the N-well substrate contact region 23 without being restricted by the design rules, it is possible to provide a structure of the connectable P-channel MOS transistor cells 20 which can reduce the possibility of variation in threshold voltage. Here, since the N-well substrates themselves are automatically overlapped by connecting the N-well substrate contact regions 23, there is no need to worry about design rules.
[0151]
Further, in the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the first layer metal (subvdd) 23a connected to the N-well substrate contact region 23 is formed from the drain region, the gate region, and the source region. By utilizing the feature of short-circuiting in the first layer at the rising portion to each of the drain wiring (D1), the gate wiring (G1), and the source wiring (S1), it is electrically connected to these drain, gate, and source regions. It can be used as the cell switching metal 25.
[0152]
That is, by covering the cell switching metal 25 over the entire P-channel MOS transistor cell 20, the P-channel MOS transistor cell 20 can be reused as an N-well substrate contact cell in a pseudo manner. Thereby, the P-channel MOS transistor cell 20 disables the transistor function in the P-channel MOS transistor cell 20 because the drain region, the gate region, the source region, and the N-well substrate contact region 23 are all short-circuited. The P-channel MOS transistor cell 20 will be treated as an N-well substrate contact cell.
[0153]
Therefore, by arranging the P-channel MOS transistor cell 20 serving as an N-well substrate contact cell for stabilizing the transistor in an empty space on the layout pattern, it is possible to effectively use the empty cell space. it can.
[0154]
On the other hand, if the P-channel MOS transistor cell 20 is laid out in a vacant space between the element circuits as a pseudo substrate contact cell, the cell switching metal 25 of the pseudo substrate contact cell is removed. Thus, the original P-channel MOS transistor cell 20 can be easily reused.
[0155]
In the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the width of the N-well substrate contact region 23 expands and contracts according to the width of each of the drain trunk line (D) and the source trunk line (D). Formed.
[0156]
Therefore, for example, the structure of the basic substrate frame is maintained with respect to the change of each trunk line width of the drain trunk line (D) and the source trunk line (D) obtained from the current value distributed to each P-channel MOS transistor cell 20. The outermost N-well substrate contact region 23 can be easily expanded and contracted as it is.
[0157]
That is, since the structure of the N-well substrate contact region 23 is enhanced for general versatility, the P-channel MOS transistor cell 20 having various variations can be formed without changing the basic structure of the N-well substrate contact region 23. Can be formed. For example, it becomes possible to easily form a P-channel MOS transistor cell 20 that differs for each operating current.
[0158]
Further, in the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the N-well substrate contact region 23 includes the drain wiring (D1) and the source wiring (S1) connected to the drain region and the source region. An internal region below each drain main line (D) / source main line (D) for supplying a signal to the semiconductor device is opened as much as possible.
[0159]
Therefore, the first-layer metal (subvdd) 23a covering the N-well substrate contact region 23 is cut out as much as possible from the N-well substrate contact region 23 located below the drain main line (D) and the source main line (D). The parasitic capacitance formed between the drain main line (D) and the source main line (D) can be reduced.
[0160]
In the structure of the connectable P-channel MOS transistor cell 20 of the present embodiment, the substrate contact region is the N-well substrate contact region 23.
[0161]
Therefore, in the P-channel MOS transistor, when the P-channel MOS transistor cells 20 are continuously arranged, wiring between the P-channel MOS transistor cells 20 in the N-well substrate contact regions 23 is avoided, and the layout is designed at the time of layout design. It is possible to provide a structure of connectable P-channel MOS transistor cells 20 which can form a substrate contact region without being restricted by design rules and can reduce the possibility of variation in threshold voltage.
[0162]
[Embodiment 6]
The following will describe another embodiment of the present invention with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of the above-described first to fifth embodiments are denoted by the same reference numerals, and description thereof is omitted.
[0163]
In the present embodiment, an example will be described in which the P-channel MOS transistor cells 20 are connected in the x-axis direction in FIG. 13 of the fifth embodiment, that is, in the extension direction of the gate line (G1).
[0164]
FIG. 18 is a circuit diagram of a differential pair including two types of P-channel MOS transistors M1 and M2. Also, FIG. 19 shows that the channel width W = α of the two types of P-channel MOS transistors M1 and M2 shown in FIG. 18 is divided into 16 (Wmin = α / 16), and 8 fingers (W ′ = 8 × Wmin). Each time, P-channel MOS transistor cells M1 'and M2', which are the P-channel MOS transistor cells 20 according to the present embodiment, are formed (M1 '= M2' = 2 * W '), and the x-axis direction shown in FIG. In other words, they are connected in the same direction as the gate wiring (G1) (extending direction of the gate wiring (G1)).
[0165]
As shown in the figure, the P-channel MOS transistor cells M1 'and M2' are arranged in a cross shape and have a geometrical origin symmetric structure. 19, the variation between the P-channel MOS transistor M1 and the P-channel MOS transistor M2 in FIG. 19 becomes equal.
[0166]
Further, by using the configuration according to the present embodiment, it is easy for transistor cells having different roles, such as P-channel MOS transistor cells M1 'and M2' shown in FIG. 23 can be connected. Further, when the source trunk line (S) of the P-channel MOS transistor cell M1 'and the drain trunk line (D) of the P-channel MOS transistor cell M2' are connected in the x-axis direction at the cell stage, an N-well substrate is interposed therebetween. Since the contact regions 23 exist, the clearance rules between adjacent metal wirings can be satisfied without concern for the design rules used during layout design. That is, the source trunk line (S) and the drain trunk line (D) must not be in contact with each other and must not be too close. In this regard, when the P-channel MOS transistor cells M1 'and M2' are connected, the N-well substrate contact regions 23 with a constant interval width exist between them, so that the N-well substrate contact regions with a constant interval width exist. There is no need to worry about the distance between the source trunk line (S) and the drain trunk line (D) as compared to the case where 23 does not exist.
[0167]
The final substrate wiring may be drawn from any position of the N-well substrate contact region 23 at both ends of the connected P-channel MOS transistor cells M1 'and M2'.
[0168]
As described above, in the structure of the connectable P-channel MOS transistor cells M1 'and M2' of the present embodiment, the drain trunk (D) and the source trunk (D) are connected to the ends of the P-channel MOS transistor cells M1 'and M2'. By arranging it inside rather than the outer periphery, the width of the substrate contact region is set so as to satisfy the metal-to-metal clearance rule when the drain trunk line and the source trunk line face each other.
[0169]
Further, in the present embodiment, each of the outer ends of the drain trunk line (D) and the source trunk line (D) and the outermost periphery of the P-channel MOS transistor cells M1 'and M2' in the N-well substrate contact regions 23 and 23 are arranged. The planar interval between the drain trunk lines (D) and the sources is established by continuously connecting the P-channel MOS transistor cells M1 'and M2' in the direction of extension of the gate line (G1) connected to the gate region. It is set so as to satisfy the metal-to-metal clearance rule when the main line (D) faces each other.
[0170]
Therefore, the P-channel MOS transistor cells M1 'and M2' can be continuously arranged without worrying about the restrictions of the design rules at the time of layout design, and the layout efficiency is further improved.
[0171]
In the structure of the connectable P-channel MOS transistor cells M1 'and M2' of the present embodiment, when the two types of P-channel MOS transistor cells M1 'and M2' are connected to each other, each P-channel MOS transistor cell M1 Since the N-well substrate contact regions 23 of '.M2' are abutted against each other, a differential pair having good symmetry can be formed by arranging the N-well substrate contact regions 23 and 23 in common.
[0172]
[Embodiment 7]
Another embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, members having the same functions as the members shown in the drawings of the above-described first to sixth embodiments are given the same reference numerals, and descriptions thereof are omitted.
[0173]
In the present embodiment, an example of connection in the y-axis direction in FIG. 13 in the P-channel MOS transistor cell 20 will be described.
[0174]
FIG. 20 shows an example in which two P-channel MOS transistor cells 20 are formed for every eight fingers and connected in the y-axis direction (perpendicular to the gate line (G1)) in FIG.
[0175]
In the figure, the structure is substantially the same as that of the 16-finger P-channel MOS transistor cell 20. As shown in the figure, not only between the N-well substrate contact regions 23 of adjacent P-channel MOS transistor cells 20, but also between the gate trunks (G) and (G), and between the source trunks (S) and Since there is no need to lay out connections between (S) and between the drain main lines (D) and (D), the layout efficiency can be improved. Here, since the N-well substrates themselves are automatically overlapped by connecting the N-well substrate contact regions 23, there is no need to worry about design rules.
[0176]
As described above, in the structure of the connectable P-channel MOS transistor cells 20 of the present embodiment, the gate trunk line (G) is formed to extend to the outermost end of the P-channel MOS transistor cells 20. Therefore, the gate trunks (G) and (G) of the adjacent P-channel MOS transistor cells 20 and 20 can be connected to each other by abutment of the gate trunks (G) and (G). Therefore, when the P-channel MOS transistor cells 20 and 20 are continuously connected in the direction opposite to the gate trunk lines (G) and (G), a separate connection wiring for the gate trunk lines (G) and (G) can be omitted. it can.
[0177]
In the structure of the connectable P-channel MOS transistor cells 20 of the present embodiment, each drain for supplying a signal to each drain wiring (D1) and source wiring (S1) connected to the drain region and the source region is provided. The trunk line (D) and the source trunk line (D) are formed to extend to the outermost ends of the P-channel MOS transistor cells 20.
[0178]
Therefore, the drain trunk lines (D) and (D) of the adjacent P-channel MOS transistor cells 20 and 20 are matched with each other and the source trunk lines (D) and (D) are matched with each other. And source trunk lines (D) and (D) can be connected to each other. Therefore, when the P-channel MOS transistor cells 20 are continuously connected in the direction in which the drain trunks (D) and (D) and the source trunks (D) and (D) face each other, the drain trunks (D) and ( Separate connection wiring can be omitted for D) and source trunk lines (D) and (D).
[0179]
FIG. 21 is a simplified diagram of FIG. FIG. 22 is a cross-sectional view taken along the line CC in FIG. From the figure, it is possible to connect the gate main line (G), the metal layer for substrate contact (subvdd) 23a, and the N-type diffusion region (n +) without considering the design rule by using the transistor structure of the present embodiment. It turns out that it becomes. Similarly, by overlapping the N-wells, it can be seen that they are electrically connected as one N-well without being restricted by the design rules.
[0180]
Embodiment 8
Another embodiment of the present invention will be described below with reference to FIGS. For convenience of explanation, members having the same functions as those shown in the drawings of Embodiments 1 to 7 are given the same reference numerals, and descriptions thereof will be omitted. Further, the N-type diffusion region 32, the substrate contact region 33, and the transistor block (Sensitive Circuit) 34 described in the present embodiment are the N-type diffusion region 2, the substrate contact region 3, and the transistor block (Sensitive Circuit) of the first embodiment. Circuit 4).
[0181]
The transistor cell applied in the connectable transistor cell structure of the present invention is not limited to a square. That is, the present invention can be applied to other polygons.
[0182]
In the present embodiment, an N-channel MOS transistor cell having a triangular configuration will be described.
[0183]
As shown in FIG. 23, an N-channel MOS transistor cell 30 of the present embodiment has an N-type diffusion region 32 for forming a drain region and a source region on a first substrate (P-substrate) 1 made of a P-type substrate. And a triangular transistor block (Sensitive Circuit) 34 composed of a gate wiring (G1) made of polysilicon wiring. In general, a TOP metal layer having a relatively small resistance is used for the gate wiring (G1).
[0184]
Around the transistor block (Sensitive Circuit) 34, a substrate contact region 33 formed of a P-type diffusion region for applying a substrate potential is formed.
[0185]
In the present embodiment, the substrate contact region 33 is formed so as to surround the outermost periphery of the N-channel MOS transistor cell 30, as shown in FIG. Thereby, in the present embodiment, it is possible to omit the inter-element wiring between the substrate contact regions 33 of the adjacent N-channel MOS transistor cells 30.
[0186]
By using the N-channel MOS transistor cell 30 according to the present embodiment, the necessity of wiring between elements and the restrictions on design rules used during layout design are drastically reduced, so that layout work efficiency can be improved.
[0187]
On the other hand, in the present embodiment, the first layer metal connected to the substrate contact region 33 is replaced with a triangular cell switching metal (not shown), similarly to the rectangular N-channel MOS transistor cell 10 described in the first embodiment. It is possible to switch to.
[0188]
As a result, the N-channel MOS transistor cell 30 can be easily switched to the substrate contact cell only by the simple first-layer metal short-circuit wiring made of the triangular cell switching metal. As a result, the N-channel MOS transistor cell 30 can be reused as a pseudo substrate contact cell.
[0189]
Further, in the present embodiment, since the substrate frame in which the substrate contact regions 33 are all connected in advance is formed, and the outermost periphery is formed by the substrate contact regions 33, a smooth N channel The connection between the MOS transistor cells 30 is enabled.
[0190]
Further, the substrate contact region 33 can be expanded and contracted in accordance with the change in the wiring width of the source main line (S) and the drain main line (D), so that the N-channel MOS transistor cell 30 can be used without breaking the basic structure of the substrate frame. Can be formed.
[0191]
Also in the present embodiment, useless substrate contact region 33 is trimmed (not shown) in order to avoid formation of parasitic capacitance with source main line (S) and drain main line (D).
[0192]
24 and 25 show an example in which the N-channel MOS transistor cells 30 are arranged efficiently. As shown in the figure, the wiring is facilitated by arranging the gate trunks (G) and (G), the drain trunks (D) and (D), and the source trunks (S) and (S) to face each other. I have to.
[0193]
In the present embodiment,
As described above, in the structure of the connectable N-channel MOS transistor cell 30 of the present embodiment, the N-channel MOS transistor cell 30 has a polygonal shape including a quadrangle and a triangle. That is, the shape of the transistor cell is not limited to a general square, but may be a triangle or another polygon.
[0194]
[Embodiment 9]
The following will describe still another embodiment of the present invention with reference to FIG. For convenience of explanation, members having the same functions as those shown in the drawings of the first to eighth embodiments are denoted by the same reference numerals, and description thereof is omitted. Further, P-channel MOS transistor cell 40 described in the present embodiment is functionally the same as P-channel MOS transistor cell 20 described in the fifth embodiment. Therefore, the P-type diffusion region 42, the N-well substrate contact region 43, and the transistor block (Sensitive Circuit) 44 correspond to the P-type diffusion region 22, the N-well substrate contact region 23, and the transistor block (Sensitive Circuit) of the fifth embodiment. ) Has the same function as 24.
[0195]
The transistor cell applied in the connectable transistor cell structure of the present invention is not limited to a square P-channel MOS transistor cell, and the present invention can be applied to other polygons.
[0196]
In the present embodiment, a P-channel MOS transistor cell having a triangular configuration will be described.
[0197]
As shown in FIG. 26, the P-channel MOS transistor cell 40 of the present embodiment has a drain region and an N-well substrate 41 formed on a first substrate (P-substrate) formed of a P-type substrate (not shown). A transistor block (Sensitive Circuit) 44 having a triangular structure constituted by a P-type diffusion region 42 forming a source region and a gate line (G1) formed of a polysilicon line is provided. In general, a TOP metal layer having a relatively small resistance is used for the gate wiring (G1).
[0198]
An N-well substrate contact region 43 formed of an N-type diffusion region for applying a substrate potential is formed around the transistor block (Sensitive Circuit) 44.
[0199]
In the present embodiment, the N-well substrate contact region 43 is formed so as to surround the outermost periphery of the P-channel MOS transistor cell 40. As a result, in the present embodiment, it is possible to omit the inter-element wiring between the N-well substrate contact regions 43 of the adjacent P-channel MOS transistor cells 40.
[0200]
By using the P-channel MOS transistor cell 40 according to the present embodiment, the necessity of wiring between elements and the restrictions on design rules used in layout design are drastically reduced, so that layout work efficiency can be improved.
[0201]
On the other hand, also in the present embodiment, the function of the transistor can be disabled by using a triangular cell switching metal (not shown) in the first layer metal (subvdd) 43a connected to the N-well substrate contact region 43. ing.
[0202]
Here, in this embodiment, the wirings forming the gate wiring (G1), the source wiring (S1), and the drain wiring (D1) are all lower metal layers and always pass through the first layer. It is possible to short-circuit using layers.
[0203]
Thus, the triangular P-channel MOS transistor cell 40 can be easily switched to the triangular N-well substrate contact cell only with the wiring composed of a simple plate-shaped metal formed by the triangular cell switching metal. As a result, the P-channel MOS transistor cell 40 can be reused as a pseudo N-well substrate contact cell.
[0204]
Further, in the present embodiment, the outermost periphery of triangular P-channel MOS transistor cell 40 is formed by N-well substrate contact region 43, so that smooth P-channel MOS transistor cells 40 irrespective of the vertical and horizontal directions are formed. The connection is made possible.
[0205]
Further, the N-well substrate contact region 43 can be expanded and contracted according to the change in the wiring width of the source trunk line (S) and the drain trunk line (D), so that the basic structure of the N-well substrate frame can be changed without breaking the purpose. The P-channel MOS transistor cell 40 can be formed.
[0206]
In this embodiment, useless N-well substrate contact region 43 is trimmed (cut out) in order to avoid formation of parasitic capacitance with source main line (S) and drain main line (D). ).
[0207]
As described above, in the structure of the connectable P-channel MOS transistor cell 40 of the present embodiment, the P-channel MOS transistor cell 40 has a polygonal shape including a quadrangle and a triangle. That is, the shape of the transistor cell is not limited to a general square, but may be a triangle or another polygon.
[0208]
It should be noted that the present invention is not limited to each of the above-described embodiments, and various changes can be made within the scope of the claims, and the technical means disclosed in different embodiments can be appropriately combined. Such embodiments are also included in the technical scope of the present invention.
[0209]
【The invention's effect】
As described above, the connectable transistor cell structure of the present invention is formed such that the substrate contact region is the outermost periphery of the transistor cell.
[0210]
Therefore, since the substrate contact region is formed so as to be the outermost periphery of the transistor cell, when connecting the transistor cells, the substrate contact regions existing at the outermost periphery are mutually connected by abutting the transistor cells. Contact and electrical connection. Therefore, the trouble of wiring between the transistor cells in the substrate contact regions can be omitted.
[0211]
Further, since the substrate contact region exists at the outermost periphery, no gap is formed between the transistor cells or between the substrate contact regions when the transistor cells are continuously arranged. Further, it is not necessary to newly form a substrate contact region. Therefore, the transistor cells can be continuously arranged without any restrictions of the design rules at the time of layout design.
[0212]
In addition, since the substrate contact region exists at the outermost periphery in any of the transistor cells, the respective transistor structures can be completely equalized, and the possibility of variation in threshold voltage can be reduced.
[0213]
Therefore, when continuously arranging the transistor cells, wiring between the transistor cells in the substrate contact region is avoided, and the substrate contact region is formed without being restricted by the design rule at the time of the layout design. This provides an effect that it is possible to provide a connectable transistor cell structure that can reduce the number of transistors.
[0214]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein a first layer metal connected to the substrate contact region is provided, and the first layer metal is: The transistor function is disabled by short-circuiting in the first layer at the rising portion from the drain region / gate region / source region to each drain wiring / gate wiring / source wiring, and the transistor cell is turned into a pseudo substrate contact block. It can be converted.
[0215]
Therefore, the transistor cell can be easily switched to the substrate contact cell simply by mounting the simple short-circuit first layer metal on the transistor cell. Therefore, by arranging a transistor cell serving as a substrate contact cell for stabilizing a transistor in an empty space on the layout pattern, an effect of effectively utilizing the cell empty space can be achieved.
[0216]
On the other hand, when the transistor cell of the present invention is laid out in a vacant space between the element circuits as a pseudo substrate contact cell, on the other hand, the first-layer metal for short circuit of the pseudo substrate contact cell is By removing it, it is possible to easily reuse it as the original transistor cell.
[0219]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure according to the above description, wherein the drain wiring and the source wiring connected to the drain region and the source region are provided above the substrate contact region. Each drain main line / source main line for supplying a signal is arranged inside and above the substrate contact region of the transistor cell, and the width of the substrate contact region expands and contracts according to each main line width of the drain main line / source main line. Is formed.
[0218]
Therefore, since the structure of the substrate contact region is improved in versatility, it is possible to form a transistor cell with various variations without changing the basic structure of the substrate contact region.
[0219]
In the connectable transistor cell structure according to the present invention, in the connectable transistor cell structure described above, the substrate contact region supplies a signal to each drain wiring / source wiring connected to the drain region / source region. The internal region located below each of the drain trunk lines and the source trunk lines is as open as possible.
[0220]
Therefore, the parasitic capacitance formed between the first layer metal covering the substrate contact region and the drain / source trunk line is reduced by cutting out the substrate contact region located below the drain / source trunk line as much as possible. This has the effect that it can be performed.
[0221]
Further, in the connectable transistor cell structure of the present invention, in the connectable transistor cell structure described above, the drain main line and the source main line are arranged inside the outermost periphery of the transistor cell, so that the mutual drain main line The width of the substrate contact region is set so as to satisfy the metal-to-metal clearance rule when the source trunk lines face each other.
[0222]
Therefore, the transistor cells can be continuously arranged without worrying about the restrictions of the design rules at the time of layout design, so that the layout efficiency is further improved.
[0223]
In the connectable transistor cell structure according to the present invention, in the connectable transistor cell structure described above, a gate trunk line for supplying a signal to a gate wiring connected to the gate region is provided at an outermost peripheral end of the transistor cell. It is formed to extend up to.
[0224]
Therefore, the gate trunks can be connected to each other by abutting the gate trunks of the adjacent transistor cells. Therefore, when the transistor cells are continuously connected in the direction opposite to the gate trunk line, there is an effect that a separate connection wiring can be omitted for the gate trunk line.
[0225]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein each drain main line and source for supplying a signal to each drain wiring and source wiring connected to the drain region and the source region are provided. The main line extends to the outermost peripheral end of the transistor cell.
[0226]
Therefore, the drain trunk lines and the source trunk lines can be connected to each other by abutting the drain trunk lines and the source trunk lines of the adjacent transistor cells. Therefore, when the transistor cells are continuously connected in the direction in which the drain trunk lines and the source trunk lines are opposed to each other, an effect is obtained that a separate connection wiring can be omitted for the drain trunk lines and the source trunk lines.
[0227]
Further, the connectable transistor cell structure according to the present invention is the same as the connectable transistor cell structure described above, wherein the transistor cells have various functions depending on the purpose of design, but the transistor cells are connected to each other. The substrate contact regions of the transistor cells having different functions can be shared by abutting the substrate contact regions of the respective transistor cells.
[0228]
Therefore, when connecting transistor cells having different functions to each other, the substrate contact regions of the transistor cells having different functions can be shared by abutting the substrate contact regions of the respective transistor cells. By arranging them, a differential pair having good symmetry can be formed.
[0229]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein the transistor cell is an N-channel MOS transistor formed in a first P-type semiconductor substrate. is there.
[0230]
Therefore, in the N-channel MOS transistor, when continuously arranging the transistor cells, the wiring between the transistor cells in the substrate contact region is avoided, and the substrate contact region is formed without being restricted by the design rule at the time of layout design. This has the effect of providing a connectable transistor cell structure that can reduce the possibility of variations in threshold voltage.
[0231]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure according to the above description, wherein the transistor cell is separated by a process option (Deep N-well) and an N-well. It is formed in a mold semiconductor substrate.
[0232]
Therefore, there is an effect that the influence of noise generated by another circuit is cut off and the transistor can operate at a stable substrate potential.
[0233]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein the substrate contact region is an N-well substrate contact region.
[0234]
Therefore, in the P-channel MOS transistor, when arranging the transistor cells continuously, it is possible to avoid wiring between the transistor cells of the substrate contact regions and form the substrate contact regions without being restricted by the design rules during layout design. This has the effect of providing a connectable transistor cell structure that can reduce the possibility of variations in threshold voltage.
[0235]
The connectable transistor cell structure according to the present invention is the connectable transistor cell structure described above, wherein the transistor cell has a polygonal shape including a quadrangle and a triangle.
[0236]
According to the above invention, the transistor cell has a polygonal planar shape including a square and a triangle. That is, the shape of the transistor cell is not limited to a general square, but may be a triangle or another polygon. Also according to this, the effects of the above invention can be obtained.
[Brief description of the drawings]
FIG. 1 shows an embodiment of an N-channel MOS transistor cell according to the present invention, and is a plan view showing a layout pattern.
FIG. 2 is a cross-sectional view taken along line AA of FIG. 4, showing an N-channel MOS transistor cell disposed in a first substrate (P-substrate).
FIG. 3 is a plan view showing a layout pattern in which a substrate contact region of the N-channel MOS transistor cell is extracted.
FIG. 4 is a plan view showing a simplified layout pattern of the N-channel MOS transistor cell.
FIG. 5 is a cross-sectional view taken along the line AA of FIG. 4, illustrating an N-channel MOS transistor cell arranged in a Deep N-well;
FIG. 6 is a plan view showing a state where an N-channel MOS transistor cell is switched to a substrate contact cell by a cell switching metal.
FIG. 7 is a circuit diagram showing a differential pair including two N-channel MOS transistors (M1 and M2).
FIG. 8 is a plan view showing a state in which N-channel MOS transistor cells (M1 ′ and M2 ′) of the N-channel MOS transistors (M1 and M2) are connected to each other.
FIG. 9 is a circuit diagram showing two differential pairs composed of four N-channel MOS transistors (M1 to M4).
FIG. 10 is a plan view showing a state in which N-channel MOS transistor cells (M1 ′ to M4 ′) of the N-channel MOS transistors (M1 to M4) are connected and arranged.
FIG. 11 is a plan view showing a state where the N-channel MOS transistor cell is connected to a gate wiring in a vertical direction.
12 shows another embodiment of the connectable transistor cell structure according to the present invention, and is a cross-sectional view taken along the line BB of FIG. 14, showing a P-channel MOS transistor cell.
FIG. 13 is a plan view showing a layout pattern of the P-channel MOS transistor cell.
FIG. 14 is a plan view showing a simplified layout pattern of the P-channel MOS transistor cell.
15 is a cross-sectional view taken along the line BB of FIG. 14, showing a state in which a P-channel MOS transistor cell is switched to a substrate contact cell by a cell switching metal.
FIG. 16 is a plan view showing a state in which a P-channel MOS transistor cell is switched to a substrate contact cell by a cell switching metal.
FIG. 17 is a plan view showing a layout pattern in which an N-well substrate contact region of the P-channel MOS transistor cell is extracted.
FIG. 18 is a circuit diagram showing a differential pair including two P-channel MOS transistors (M1 and M2).
FIG. 19 is a plan view showing a state in which P-channel MOS transistor cells (M1 ′ and M2 ′) of the P-channel MOS transistors (M1 and M2) are connected to each other.
FIG. 20 is a plan view showing a state where the P-channel MOS transistor cell is connected to a gate wiring in a vertical direction.
FIG. 21 is a plan view showing a simplified layout pattern of FIG. 20;
FIG. 22 is a cross-sectional view taken along the line CC of FIG. 21, showing a state where the P-channel MOS transistor cell is connected to a gate wiring in a vertical direction.
FIG. 23 is a plan view showing still another embodiment of the connectable transistor cell structure according to the present invention, and showing a triangular N-channel MOS transistor cell.
FIG. 24 is a plan view showing a state where the triangular N-channel MOS transistor cells are connected and arranged;
FIG. 25 is a plan view showing a state in which a large number of triangular N-channel MOS transistor cells are connected and arranged.
FIG. 26 is a plan view showing a triangular P-channel MOS transistor cell.
FIG. 27 is a circuit diagram showing an N-channel MOS transistor having a channel width W of α.
FIG. 28 is a circuit diagram showing an N-channel MOS transistor in which the channel width is divided in parallel into minimum units.
29 shows the structure of a conventional connectable transistor cell, and is a cross-sectional view taken along the line DD of FIG. 31, showing an N-channel MOS transistor cell arranged in a Deep N-well.
FIG. 30 is a plan view showing an N-channel MOS transistor cell arranged in the Deep N-well.
FIG. 31 is a plan view showing a simplified layout pattern of the P-channel MOS transistor cell.
FIG. 32 is a circuit diagram showing the P-channel MOS transistor.
FIGS. 33A and 33B are plan views showing layout examples of a three-terminal MOS transistor composed of a gate, a source, and a drain schematically showing gate resistance.
FIGS. 34A and 34B are circuit diagrams in which the gate resistance of a polysilicon wiring is considered in the MOS transistor.
FIG. 35 is a plan view showing a state where the N-channel MOS transistor cells are connected and arranged;
FIG. 36 is a plan view showing another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 37 is a plan view showing still another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 38 is a plan view showing still another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 39 is a plan view showing still another state in which the N-channel MOS transistor cells are connected and arranged.
FIG. 40 is a circuit diagram showing N-channel MOS transistors (M1 to M4) limited to transistors of a differential input type LNA circuit.
[Explanation of symbols]
1. First substrate (P-substrate) (first P-type semiconductor substrate)
1a Second substrate (P-substrate 2) (second P-type semiconductor substrate)
2 N-type diffusion region (drain region, source region)
3 Substrate contact area
3a First layer metal (subgnd)
3c trimming (opening)
4 Transistor block (Sensitive Circuit)
5 Cell switching metal (first layer metal)
10 N-channel MOS transistor cell (transistor cell)
20 P-channel MOS transistor cell (transistor cell)
21 N-well substrate
22 P-type diffusion region (drain region, source region)
23 N-well substrate contact area
23a First layer metal (subvdd)
25 Cell Switching Metal (First Layer Metal)
30 N-channel MOS transistor cell (transistor cell)
40 P-channel MOS transistor cell (transistor cell)
D drain main line
D1 drain wiring
G gate trunk line
G1 Gate wiring
Gd1 dummy poly wiring
M1, M2, M3, M4 MOS transistors
M1 ', M2', M3 ', M4' MOS transistor cells
S source trunk line
S1 source wiring

Claims (12)

In a connectable transistor cell structure having a drain contact region, a gate contact region, a source contact region, and a substrate contact region for stabilizing the operation of the transistor, the connectable transistor cell structure is arranged in parallel to constitute a semiconductor integrated circuit;
A connectable transistor cell structure, wherein the substrate contact region is formed so as to be the outermost periphery of the transistor cell. A first layer metal connected to the substrate contact region is provided;
The first-layer metal disables the transistor function by short-circuiting in the first layer at a rising portion from the drain region / gate region / source region to each drain wiring / gate wiring / source wiring, thereby disabling the transistor cell. The connectable transistor cell structure according to claim 1, wherein the structure can be converted into a pseudo substrate contact block. Above the substrate contact region, each drain main line and source main line for supplying a signal to each drain wiring / source wiring connected to the drain region / source region are arranged inside and above the substrate contact region of the transistor cell. Along with
3. The connectable transistor cell structure according to claim 1, wherein the width of the substrate contact region is formed to expand and contract according to the width of each of the drain trunk line and the source trunk line. In the substrate contact region, an internal region located below each drain main line / source main line for supplying a signal to each drain line / source line connected to the drain region / source region is opened as much as possible. The connectable transistor cell structure according to claim 3, wherein: By arranging the drain trunk line and the source trunk line inside the outermost periphery of the transistor cell, the width of the substrate contact region is set so as to satisfy the metal-to-metal clearance rule when the drain trunk line and the source trunk line face each other. The connectable transistor cell structure according to any one of claims 1 to 4, wherein: 6. The gate trunk line for supplying a signal to a gate wiring connected to the gate region, the gate trunk line extending to the outermost peripheral end of the transistor cell, and formed. Connectable transistor cell structure. The drain trunk line / source trunk line for supplying a signal to each drain wiring / source wiring connected to the drain region / source region is formed to extend to the outermost peripheral end of the transistor cell. Item 7. A connectable transistor cell structure according to any one of Items 1 to 6. Although the transistor cells have various functions depending on the design purpose, when connecting the transistor cells to each other, the substrate contact regions of the transistor cells having different functions are formed by abutting the substrate contact regions of the respective transistor cells. The connectable transistor cell structure according to any one of claims 1 to 7, wherein 9. The connectable transistor cell structure according to claim 1, wherein said transistor cell is an N-channel MOS transistor formed in a first P-type semiconductor substrate. 10. The connectable transistor cell according to claim 9, wherein the transistor cell is formed in a second P-type semiconductor substrate separated by a process option (Deep N-well) and an N-well. Construction. 9. The connectable transistor cell structure according to claim 1, wherein the substrate contact region is an N-well substrate contact region. 12. The connectable transistor cell structure according to claim 1, wherein the transistor cell has a polygonal shape including a quadrangle and a triangle.

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