CN114068522A

CN114068522A - Method for latticed winding of transistor

Info

Publication number: CN114068522A
Application number: CN202111342691.XA
Authority: CN
Inventors: 袁天浩
Original assignee: Hangzhou Guangli Microelectronics Co ltd
Current assignee: Hangzhou Guangli Microelectronics Co ltd
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-02-18

Abstract

The invention provides a latticed winding method of a transistor, which comprises the following steps: selecting a plurality of transistors to be wound; distributing end winding areas based on the number of the transistors to be wound and the pins needing to be wound; predefining, wherein the definition content comprises the number of metal layers, and the line width and the gap size of metal lines in each metal layer; filling corresponding metal wires in the end winding area according to the number of the metal layers, the line width and the size of the gap; setting the direction of the extending line of the pin to be wound as the horizontal direction, and extending the metal line in the vertical direction in the filled metal lines until the extending line of the pin to be wound is intersected and connected; and/or after the filled metal wire is extended to the edge of the metal layer where the metal wire is located, the metal wire is connected with the pin extension wire needing to be wound through arranging a connecting structure. The method can realize network-shaped automatic winding of the transistor, greatly simplifies the winding process, can be repeatedly used in different processes, customers and manufacturing methods, and has wide application range and great application potential.

Description

Method for latticed winding of transistor

Technical Field

The invention belongs to the field of semiconductor design and production, and particularly relates to a latticed winding method for a transistor.

Background

Transistors are basic units of integrated circuits, and are devices commonly used in semiconductor chips. With the wide application of integrated circuits, the requirement for integration level is higher and higher, the higher the integration level is, the more miniaturized various electronic components are, and the more significant the influence of the performance of the transistor on the integrated circuit is. In the production process of the transistor, factors influencing the performance of the transistor are various, and different types of tests of the transistor need to be completed to ensure that the performance of the transistor is good. In the transistor testing stage, the source (S), the drain (D), the gate (G), and the substrate (B) are generally required to be pressurized separately to implement different types of tests. However, since there is a certain resistance in the winding line between the D, G, S, B four terminals and the Pin (Pin), there is a certain voltage drop from the voltage applying terminal to the testing terminal, and the testing result may have a deviation. In order to reduce the resistance of the winding, grid-shaped windings are usually used, and the metal layers are usually connected in parallel in an interleaving manner.

The traditional grid winding has two types, and both types are manually wound. The first is to dig holes in a large area of metal layer to form a grid to reduce the winding resistance, as shown in fig. 1; the second is to connect multiple metal lines in a staggered manner through vias to form a dense grid to reduce resistance, as shown in fig. 2. With the continuous upgrade of the integrated circuit technology, the metal layer in the current advanced process is not allowed to turn and only can go straight, so the first method for digging holes in bulk metal is not suitable for the advanced process and has insufficient application potential. The multilayer multi-metal-wire staggered connection can be suitable for different process requirements (whether the process allows metal to turn or not), but the manual winding process is complicated, through hole dislocation is easy to occur, connection errors are caused, winding needs to be rearranged for each project according to different process nodes and different customer requirements, repeatability among different projects is poor, accuracy is low, and the customer requirements and actual production application cannot be well met.

Therefore, at present, a method for latticed winding of a transistor needs to be researched, so that the method has better application potential, automatic winding can be realized according to a Pin (Pin), repeatability and accuracy are improved, and efficiency is optimized while the process is perfected, so that deep development and wide application of a transistor testing technology are further promoted.

Disclosure of Invention

In order to solve all or part of the problems in the prior art, the invention provides a latticed winding method for a transistor, which can realize automatic winding according to a Pin (Pin) and solve the latticed winding problem of the transistor.

The invention provides a method for latticed winding of a transistor, which comprises the following steps: selecting a plurality of transistors to be wound, wherein the transistors to be wound comprise a source electrode (S) end, a drain electrode (D) end, a grid electrode (G) end and a substrate electrode (B) end; distributing end winding areas based on the number of the transistors to be wound and the pins needing to be wound; predefining, wherein the definition content comprises the number of metal layers, and the line width and the gap size of metal lines in each metal layer; filling corresponding metal wires in the end winding area according to the number of the metal layers, the line width and the size of the gap; setting the direction of the extending line of the pin to be wound as the horizontal direction, and extending the metal line in the vertical direction in the filled metal lines until the extending line of the pin to be wound is intersected and connected; and/or after the filled metal wire is extended to the edge of the metal layer where the metal wire is located, the metal wire is connected with the pin extension wire needing to be wound through arranging a connecting structure. In some embodiments, the metal layers are filled with corresponding metal lines according to the number of the metal layers, the line width and the gap size, and then the end routing regions are allocated according to the positions of the pins to be routed. Or the end winding area can be distributed according to the position of the pin needing to be wound, and then the filling winding is carried out. The practice in conjunction with actual processes and specific cases is not limiting.

And distributing the end winding area according to the position of the pin to be wound comprises distributing according to a nearby principle. Follow the principle nearby, be favorable to furthest reducing the influence that produces because of connecting wire resistance.

And when the number of the transistors to be wound is multiple, distributing transistor winding areas with the same size for each transistor to be wound. The area with the same size is distributed to each transistor to be wound, so that the resistance error of the end winding area distributed by the same pin of different transistors to be wound is reduced.

The definition further includes an area ratio for assigning the transistor routing regions to different terminals; and distributing the transistor winding area to obtain the end winding area according to the area proportion. And the transistor winding area of each transistor to be wound is distributed to different ends, such as a source electrode (S) end, a drain electrode (D) end, a grid electrode (G) end and a substrate electrode (B) end. Different ends of the transistor to be wound can be divided into the transistor winding area according to different actual requirements and designs in proportion to size.

In some embodiments, the width of the end winding area is obtained and recorded as W, the width of the metal wire in the metal layer is recorded as MiWidth, the size of the gap is recorded as misspace, wherein i is a positive integer, and a specific metal layer is represented; the number of metal lines that can be filled in the end winding region is defined as misum = Int ((W + misspace)/(MiWidth + misspace)).

And after the corresponding metal wires are filled, the metal wires positioned on the same metal layer in the same end winding area are parallel to each other.

When the corresponding metal lines are filled, the extending directions of the metal lines in the adjacent metal layers are staggered, mutually vertical or parallel.

The number of the metal layers is at least two. I.e. the routing metal layer is at least two layers. The routing metal layers may be from two layers of the foundation up to all of the metal layers used in the process.

In some implementation cases, if the number of the metal layers is more than one, for the pin to be routed in the same metal layer, setting the direction of the extending line of the pin to be routed as the horizontal direction, and extending the vertical metal line in the filled metal line until the vertical metal line is connected with the extending line of the pin to be routed of the metal layer in an intersecting manner; and for the pins needing to be wound and positioned on different metal layers, the filled metal wires are firstly extended to the edges of the metal layers where the metal wires are positioned, and then the metal wires are mutually connected with the pins needing to be wound and positioned on different metal layers through arranging a connecting structure.

And the metal wires in the adjacent metal layers are connected through a preset through hole.

The preset through holes are formed by presetting through holes at the intersection points of every other metal line in the adjacent metal layers.

The filling the respective metal lines comprises: filling the end winding regions at one or more ends of the source electrode (S), the drain electrode (D), the grid electrode (G) and the substrate electrode (B); and directly connecting the metal wire in the corresponding metal layer with the to-be-wound pin extension wire in the end winding area of the unfilled metal wire. One or more of the terminals of the to-be-routed transistor G, D, S, B may be net-routed, and for the other terminal routing regions, the metal lines in the metal layer may be directly connected to the pin extension lines to be routed.

The end winding area is rectangular. The regularly shaped end winding area facilitates simplified distribution and facilitates filling of the metal wire.

The number of the transistors to be wound is 1-100.

The transistor to be wound comprises a logic device and/or a storage device; and taking the selected transistors to be wound as a test unit in the transistor test stage after the winding of the transistors to be wound is completed. And the selected plurality of transistors to be wound are wound to obtain a test unit with small winding resistance, so that the test is conveniently carried out in the transistor test stage, the test error is reduced, and the accuracy of the transistor test result is further improved.

Compared with the prior art, the invention has the main beneficial effects that:

the grid winding method for the transistor has the advantages that the steps are simple, the terminal winding area is distributed for the base pins required to be wound by the transistor, and winding is carried out in the distributed area, so that the grid automatic winding of the transistor can be realized, the winding process is greatly simplified, the beat time is further reduced, and the production efficiency is improved; the wire winding machine is suitable for being repeatedly used in different processes, different customers and different manufacturing methods, has huge application potential, is favorable for continuously optimizing a wire winding process, and saves the manufacturing cost. The method obtains a plurality of transistors as a test unit, has small winding resistance, is used for further improving the test efficiency and the reliability of the test result in the subsequent transistor test, provides a positive and effective scheme for improving the technical level of the transistor test, and perfects the basic link in the development of the crystal test technology.

Drawings

FIG. 1 is a schematic diagram of a wire winding of a bulk metal with a mesh of holes.

Fig. 2 is a schematic diagram of multiple layers of metal connected by vias in a staggered manner.

Fig. 3 is a schematic process diagram of a method for forming a grid-shaped routing of a transistor according to a first embodiment of the invention.

Fig. 4 is a diagram illustrating a distribution end winding area according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a network-shaped routing of transistors according to a first embodiment of the invention.

Detailed Description

The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings. In the figures, parts of the same structure or function are denoted by the same reference numerals, and not all parts shown are denoted by the associated reference numerals in all figures for reasons of clarity of presentation.

The operations of the embodiments are depicted in the following embodiments in a particular order, which is provided for better understanding of the details of the embodiments and to provide a thorough understanding of the present invention, but the order is not necessarily one-to-one correspondence with the methods of the present invention, and is not intended to limit the scope of the present invention.

Example one

In an embodiment of the present invention, a method for grid-shaped winding of a transistor as shown in fig. 3 includes: selecting a plurality of transistors to be wound, wherein the transistors to be wound comprise a source electrode (S) end, a drain electrode (D) end, a grid electrode (G) end and a substrate electrode (B) end; distributing end winding areas based on the number of the transistors to be wound and the pins needing to be wound; predefining, wherein the definition content comprises the number of metal layers, and the line width and the gap size of metal lines in each metal layer; filling corresponding metal wires in the end winding area according to the defined number of the metal layers, the defined line width and the defined gap size; and setting the direction of the extending line of the pin to be wound of the transistor to be wound as the horizontal direction, and extending the metal line in the vertical direction in the filled metal line until the extending line of the pin to be wound is intersected and connected. In this embodiment, the metal layer has more than one layer, the filling metal wire is firstly extended to the edge of the metal layer where the filling metal wire is located, and then the connection structure is arranged to realize the interconnection of the wire winding pin extension wire which is not located on the same metal layer as the filling metal wire. The interconnection with the specific wire-winding-required pin extension line can be implemented according to the number of the metal layers and the specific metal layer where the wire-winding-required pin is located in practical application, and is not limited. The pre-definition may be performed before or after the selection of the transistor to be routed, and is not limited herein.

In this embodiment, the corresponding metal lines are filled according to the number of the metal layers, the line width and the size of the gap, and then the end winding area is distributed according to the positions of the pins of the transistor to be wound. In some embodiments, the terminal winding area may be distributed according to the positions of the pins of the transistor to be wound, and then the winding may be filled. The practice in conjunction with actual processes and specific cases is not limiting. In the implementation of this embodiment, the winding regions of the terminals are allocated according to the positions of the pins to be wound of the transistors to be wound and according to the principle of proximity.

In the embodiment, N transistors to be wound are selected, wherein N is more than or equal to 1 and less than or equal to 100. The two selected transistors to be wound, transistor 1 and transistor 2, are taken as examples for explanation. In this embodiment, the transistor to be routed includes a logic device, which may also be a memory device in some implementation cases, but is not limited to this, and the selected transistor to be routed is used as a test unit in a transistor test stage after the routing is completed.

And when a plurality of selected transistors to be wound are provided, distributing transistor winding areas with the same size for each transistor to be wound. The pre-defined content in this embodiment further includes allocating the transistor routing areas to the area ratios of the different terminals; and distributing the transistor winding area to obtain the end winding area according to the area proportion. The transistor winding area of each transistor to be wound is distributed to different ends, such as a source electrode (S) end, a drain electrode (D) end, a grid electrode (G) end and a substrate electrode (B) end. Each end winding region of the example is rectangular. As shown in fig. 4, the blank region on the side close to the transistor 1 is set as the winding regions D1 and G1 of the transistor 1, and the size ratio of the winding regions D1 and G1 is 5: 2. setting the blank area close to one side of the transistor 2 as winding areas at the ends D2 and G2 of the transistor 2, wherein the size ratio of the winding areas at the ends D2 and G2 is 5: 2; the upper part of the transistor is provided with a B-end winding area which is connected in common, and the lower part of each transistor to be wound is provided with an S-end winding area which is connected in common. In some embodiments, the S and B terminals of the plurality of transistors are not connected in common, and the S and B terminals of different transistors are respectively allocated to the respective end winding regions.

In this embodiment, the width of the winding area of the obtaining end is denoted as W, the width of the metal wire in the metal layer is denoted as MiWidth, the size of the gap is denoted as misspace, where i is a positive integer, and different metal layers are represented; the number of metal lines that can be filled in the end winding region is munum = Int ((W + misspace)/(MiWidth + misspace)). As illustrated in fig. 5, the number of the previously defined metal layers is two, the Width of the D1 area is W _ D1, the metal line in the vertical direction is a metal line of the second metal layer, and the Width and the gap thereof are M2Width and M2Space, and the metal line in the horizontal direction is a metal line of the first metal layer, and the Width and the gap thereof are M1Width and M1 Space. Then the second metal layer may fill metal lines by the number: m2Num = Int ((W _ D1+ M2 Space)/(M2 Width + M2 Space)). By analogy, the number of the metal wires in each end winding area can be obtained. The metal lines extending in the vertical direction are intersected with the extension lines of the pins, and the metal lines in the adjacent metal layers are connected with each other through a preset through hole serving as a connecting structure. The preset through holes are formed in every other metal line in the adjacent metal layers in advance. Exemplary vias are all of equal size as in fig. 5, indicated by V1 size. The number of metal layers is two for illustrative purposes only, and in practical applications the routing metal layers may be from two underlying layers up to all metal layers used in the process. The process nodes can range from 18 μm up to 7nm, an even more advanced process.

In this embodiment, after the end winding regions of the source (S) end, the drain (D) end, the gate (G) end, and the substrate (B) end are filled with corresponding metal wires, the metal wires in the same end winding region are parallel to each other. The extending directions of the metal lines in the metal layers of the adjacent layers can be staggered, perpendicular or parallel when the metal lines are filled.

Example two

In this embodiment, filling the corresponding metal line includes: filling end winding regions at one or more ends of a source electrode (S), a drain electrode (D), a grid electrode (G) and a substrate electrode (B); and directly connecting the metal wire in the corresponding metal layer with the pin extension wire needing to be wound in the end winding area of the unfilled metal wire. In this embodiment, a plurality of transistors to be routed are selected and arranged in an up-down manner, so that the transistor routing area of each transistor to be routed can be selected at will.

For clarity of description, the use of certain conventional and specific terms and phrases is intended to be illustrative and not restrictive, but rather to limit the scope of the invention to the particular letter and translation thereof.

The present invention has been described in detail, and the structure and operation principle of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method and core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims

1. A method for latticed winding of a transistor is characterized in that: the process comprises the following steps:

selecting a plurality of transistors to be wound, wherein the transistors to be wound comprise a source terminal, a drain terminal, a grid terminal and a substrate terminal;

distributing end winding areas based on the number of the transistors to be wound and the pins needing to be wound;

predefining, wherein the definition content comprises the number of metal layers, and the line width and the gap size of metal lines in each metal layer; filling corresponding metal wires in the end winding area according to the number of the metal layers, the line width and the size of the gap;

setting the direction of the extending line of the pin to be wound as the horizontal direction, and extending the metal line in the vertical direction in the filled metal lines until the extending line of the pin to be wound is intersected and connected; or/and after the filled metal wire is extended to the edge of the metal layer where the metal wire is located, the metal wire is connected with the pin extension wire needing to be wound through arranging a connecting structure.

2. The method of claim 1, wherein: and when the number of the transistors to be wound is multiple, distributing transistor winding areas with the same size for each transistor to be wound.

3. The method of claim 1, wherein: and after the corresponding metal wires are filled, the metal wires positioned on the same metal layer in the same end winding area are parallel to each other.

4. The method of claim 1, wherein: when the corresponding metal lines are filled, the extending directions of the metal lines in the adjacent metal layers are staggered, mutually vertical or parallel.

5. The method of claim 1, wherein: the number of the metal layers is at least two.

6. A method of latticed routing as claimed in any one of claims 1 to 5, wherein: the filling the respective metal lines comprises: filling the terminal winding area of one or more of the source terminal, the drain terminal, the gate terminal and the substrate terminal; and directly connecting the metal wire in the corresponding metal layer with the to-be-wound pin extension wire in the end winding area of the unfilled metal wire.

7. A method of latticed routing as claimed in any one of claims 1 to 5, wherein: the number of the transistors to be wound is 1-100.

8. A method of latticed routing as claimed in any one of claims 1 to 5, wherein: the end winding area is rectangular.