JPS59167036A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To eliminate an idle space region to be created due to the difference between the sizes of an output circuit and an input circuit in an MOS IC by a method wherein the input circuit only is arranged on at least one side out of four sides along the circumference of a chip. CONSTITUTION:An input circuit only is arranged on at least one side (a part of 12) out of four sides along the circumference of a chip. As a result, a vacant region, which is created due to the difference between the block sizes of the input circuit and an output circuit and cannot be utilized as a region for transistor and as a region for wiring, is eliminated, thereby enabling to make the chip size smaller. Moreover, the yield can be upgraded by lessening the chip size.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a layout of peripheral input/output circuits in an MO8 type integrated circuit.

Description of prior art FIG. 1 shows a conventional layout of an MO8 type integrated circuit.

Conventionally, input/output circuits (hereinafter referred to as input/output circuits) including pads and protection circuits have input terminals and output terminals concentrated for each function to some extent on the four sides around the chip, and each side has
The input circuit and output circuit were arranged separately. This is not a problem for integrated circuits with a small number of external input/output terminals, but as large-scale integrated circuits become larger, the number of external input/output terminals increases, and the input/output circuits have to be laid out all over the periphery of the chip. Protection circuit 5 is placed on top of pad 4 as shown in the figure.
A human output buffer 6 is laid out on top of it, forming a vertically long block. When comparing the sizes of the input circuit shown in FIG. 3 and the output circuit shown in FIG. 4, since the transistor size of the output circuit is large, the output circuit block size is correspondingly large. On one side of the periphery of the chip, there is an input circuit 9 as shown in FIG.
When the output circuits 10 are arranged, a wasteful empty area 11 that cannot be used as a transistor area or a wiring area is created above the input circuit, and as the proportion of the input circuits 9 increases on the negative side, the empty area also increases. This has the disadvantage of increasing the chip size and lowering the yield.

The present invention conventionally has an input circuit on one side of the periphery of the chip.

In order to eliminate the wasted free space caused by the placement of the output circuit, only the input circuit is placed on at least one of the four sides around the chip, eliminating the wasted free space due to the difference in size between the output circuit and the input circuit. This eliminates the problem, reduces the chip size, and improves the yield.

Structure of the Invention The structure of the present invention will be explained with reference to FIG. The central part 1 is an internal logic part, and the peripheral part 2 is an input/output circuit including pads.

In the present invention, at least one side (one
2 part), place only the input circuit, and input circuit (Fig. 3)
The chip size is reduced by eliminating the empty area (FIG. 5, 11) that cannot be used as a transistor area and a wiring area due to the difference in block size between the output circuit and the output circuit (FIG. 4).

Next, examples of the present invention will be described.

FIG. 7 shows a conventional chip layout diagram.

Both an input circuit and an output circuit 10 are arranged on each side of the chip. In FIG. 8, only the input circuit 12 is arranged on one side around the chip. In FIG. 9, when half of the external input/output terminals are occupied by external input terminals, only input circuits are arranged on two of the four sides. In this case, 2 of the case in Figure 8
This creates twice as much free space and reduces the chip size. That is, by eliminating the empty area in FIG. 7 and 11 as in 13 in FIGS. 8 and 9, the chip size is reduced and the yield is improved.

As explained above, the present invention has an MO8O8 integrated circuit, and arranges only the input circuit on at least one side of the input/output circuit around the chip, and eliminates wasted areas that are not used as transistor areas and wiring areas. Reducing the chip size has the effect of improving yield.

[Brief explanation of the drawing]

Figure 1 is a MO8O8 selected integrated circuit layout diagram, Figure 2 is an input/output circuit layout diagram, Figure 3 is an input circuit layout diagram,
Fig. 4 is an output circuit layout diagram, Fig. 5 is a diagram showing a conventional input/output circuit group, Fig. 6 is a chip layout diagram of the present invention, Fig. 7 is a conventional chip layout diagram, and Fig. 8 is a diagram according to the present invention. FIG. 9 is a chip layout diagram in which input circuits are laid out on one side, and FIG. 9 is a chip layout diagram in which input circuits are laid out on two sides according to the present invention. 1 Internal logic section, 2 Peripheral section (input/output circuit group)
, 3 input and output buffer block including pad and protection circuit, 4 pad, 5 protection circuit, 6 human power and output buffer 7 input circuit (including protection circuit) + pad,
8 Output circuit (including protection circuit) + pad. Figure 1 Figure 2 Figure 3 Figure 4 Figure 2 Figure 6 Figure 8 Figure ? figure

Claims (1)

[Claims] What is claimed is: 1. An MO8 type integrated circuit having a plurality of input buffer circuits and output buffer circuits on four sides of a chip periphery, characterized in that only an input buffer circuit is disposed on at least one of the four sides.