JPH04171844A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH04171844A
JPH04171844A JP2299529A JP29952990A JPH04171844A JP H04171844 A JPH04171844 A JP H04171844A JP 2299529 A JP2299529 A JP 2299529A JP 29952990 A JP29952990 A JP 29952990A JP H04171844 A JPH04171844 A JP H04171844A
Authority
JP
Japan
Prior art keywords
region
input
parts
pad
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2299529A
Other languages
Japanese (ja)
Inventor
Akihito Ono
明史 小野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2299529A priority Critical patent/JPH04171844A/en
Publication of JPH04171844A publication Critical patent/JPH04171844A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To arrange input/output electrode pad parts freely, optimally and at desired positions at a pad region and to make it possible to connect freely each input/output circuit part with each input/output electrode pad part via each wiring region part within the pad region by a method wherein a conventional external region is made independent into an input/output circuit part region and the pad region. CONSTITUTION:An LSI chip 100 is constituted of logical circuit blocks 130, a RAM block 132 and a ROM block 133, which are provided on the central part of a chip region, an internal region 120 consisting of internal wiring regions 140 provided on the peripheries of these blocks, an input/output circuit part region 110 provided on the outer periphery of the region 120 and a pad region 150. Moreover, the region 150 is constituted comprising input/output electrode pad parts 160 arranged in a plurality of rows, circuit parts 170 and wiring 180, via which the parts 170 and the parts 160 are connected to each other. Here, the arrangement of the pad parts 160 and the arrangement of the wirings 180, via which the parts 170 and 160 are connected to each other, at the region 150 are all set automatically by a computer.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路に間し、特にスタンダードセル
方式の半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to standard cell type semiconductor integrated circuits.

〔従来の技術〕[Conventional technology]

最近、スタンダードセルは計算機を利用する事により、
フルカスタムＬＳＩよりも短納期、低開発費であり、且
つ、ゲートアレイよりも設計の自由度が大きく、チップ
を無駄なく構成できることから、通信、パソコンなど広
い分野で用いられるようになり、さらに、レイアウトの
精密さと高い集積度が要求されている。Recently, standard cells have been made using calculators.
It has a shorter delivery time and lower development cost than a full custom LSI, has a greater degree of freedom in design than a gate array, and allows chips to be configured without waste, so it has come to be used in a wide range of fields such as communications and personal computers. Precise layout and high degree of integration are required.

第２図は従来の半導体集積回路の一例を示すレイアウト
図である。FIG. 2 is a layout diagram showing an example of a conventional semiconductor integrated circuit.

第２図に示すように、チップ領域の中央部に設けた論理
回路ブロック１３０．ＲＡＭブロック１３２、ＲＯＭブ
ロック１３３とこれらのブロックの周囲に設けた内部配
線領域１４０からなる内部領域１２０と、内部領域の外
周に設けた入出力回路部２１２と入出力電極パッド２１
３を有する入出力バッファブロック２１１からなる外部
領域２１０と、チップ領域の４隅に設けた空き領域２５
０を有してＬＳＩチップ２００が構成される。As shown in FIG. 2, a logic circuit block 130. An internal area 120 consisting of a RAM block 132, a ROM block 133, and an internal wiring area 140 provided around these blocks, an input/output circuit section 212 and an input/output electrode pad 21 provided on the outer periphery of the internal area.
an external area 210 consisting of an input/output buffer block 211 with
0, the LSI chip 200 is configured.

〔発明が解決しよ、うとする課題〕[Problem that the invention attempts to solve]

従来の半導体集積回路装置は、入出力回路部と入出力電
極パッド部から形成される人出力バッファブロックが外
部領域に配置されていたため、入出力電極パッド部を自
由に所望の位置に設定できず、計算機によるレイアウト
後、入出力電極パッド部の位置の問題からワイヤーボン
ディングが行なえないため製品として組み立てることが
できないので、レイアウトマシンにより入出力電極パッ
ドの位置を修正しなければならないという問題があった
。In conventional semiconductor integrated circuit devices, the human output buffer block formed by the input/output circuit section and the input/output electrode pad section was placed in an external area, making it impossible to freely set the input/output electrode pad section at the desired position. After the layout was done using a computer, wire bonding could not be performed due to the position of the input/output electrode pads, so the product could not be assembled, so the position of the input/output electrode pads had to be corrected using a layout machine. .

さらに、近年１つのＩＣパッケージを１つのリードフレ
ームだけでなくＤＩＰやＰＬＣＣといった様々な型のリ
ードフレームに搭載できることが要求されている。その
なめには計算機によるレイアウトの段階で入出力電極パ
ッドを自在に最適な、かつ、所望の位置に配置できる様
な構成にしなければならないという問題点がある。Furthermore, in recent years, it has become necessary to be able to mount one IC package not only on one lead frame but also on various types of lead frames such as DIP and PLCC. The problem lies in the fact that the input/output electrode pads must be arranged in optimal and desired positions at the layout stage using a computer.

琥な、空き領域は有効利用できず、高集積化のさまたげ
となっているという問題点がある。However, there is a problem in that the free space cannot be used effectively, which hinders higher integration.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、半導体チップの中央部に設
けた機能ブロック及び前記機能ブロックの周囲に設けた
内部配線領域を有する内部領域と、前記内部領域の外周
に設けた入出力回路領域と、前記入出力回路領域の外周
に設けて任意の位置に配置し且つ入出力回路と接続する
複数列の入出力電極パッドとを有する。The semiconductor integrated circuit of the present invention includes: an internal region having a functional block provided in the center of a semiconductor chip and an internal wiring region provided around the functional block; and an input/output circuit region provided on the outer periphery of the internal region. It has a plurality of rows of input/output electrode pads provided on the outer periphery of the input/output circuit area, arranged at arbitrary positions, and connected to the input/output circuits.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図（ａ＞、（ｂ）は本発明の一実施例を示すレイア
ウト図及びＡ部拡大図である。FIGS. 1(a) and 1(b) are a layout diagram and an enlarged view of part A showing an embodiment of the present invention.

第１図（ａ）、（ｂ）に示すように、チップ領域の中央
部に設けた論理回路ブロック１３０゜ＲＡＭブロック１
３２．ＲＯＭブロック１３３と、これらのブロックの周
囲に設けた内部配線領域１４０からなる内部領域１２０
と、内部領域の外周に設けた入出力回路部領域１１０お
よびパッド領域１５０を有してＬＳＩチップ１００が構
成される。As shown in FIGS. 1(a) and 1(b), a logic circuit block 130° RAM block 1 provided in the center of the chip area
32. An internal region 120 consisting of a ROM block 133 and an internal wiring region 140 provided around these blocks.
The LSI chip 100 has an input/output circuit region 110 and a pad region 150 provided on the outer periphery of the internal region.

さらに、パッド領域１５０は複数列に配置した入出力電
極パッド部１６０と、回路部１７０と、入出力電極パッ
ド部１６０を接続する配線１８０とを含んで構成される
。Further, the pad region 150 includes input/output electrode pad sections 160 arranged in a plurality of rows, a circuit section 170, and wiring 180 connecting the input/output electrode pad sections 160.

ここで、パッド領域１５０での各入出力電極パッド部１
６０の配置および入出力回路部１７０と入出力電極パッ
ド部１６０を接続する配線１８０の配置はすべて計算機
によって自動的に設定される。Here, each input/output electrode pad section 1 in the pad region 150
60 and the wiring 180 connecting the input/output circuit section 170 and the input/output electrode pad section 160 are all automatically set by a computer.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は従来の外部領域を入出力回
路部領域とパッド領域に独立させたので、パッド領域で
は入出力電極パッド部を自在に最適かつ、所望の位置に
配置でき、かつパッド領域内の配線領域部により各入出
力回路部と各入出力電極パッド部を自在に接続できると
いう効果を有する。As explained above, the present invention separates the conventional external area into the input/output circuit area and the pad area, so that the input/output electrode pad area can be freely and optimally placed in the desired position in the pad area. This has the effect that each input/output circuit section and each input/output electrode pad section can be freely connected by the wiring area section within the area.

また４隅における空きスペースも活用することからＬＳ
Ｉチップとして集積度が向上するという効果がある。Also, since the empty space in the four corners is utilized, the LS
This has the effect of improving the degree of integration as an I-chip.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）は本発明の一実施例を示すレイア
ウト図及びＡ部拡大図、第２図は従来の半導体集積回路
の一例を示すレイアウト図である。 １００．２００−−−ＬＳＩｆッ７．１１０−入出力回
路部領域、１２０・・・内部領域、１３０・・・論理回
路ブロック、１３２・・・ＲＡＭブロック、１３３・・
・ＲＯＭブロック、１４０・・・内部配線領域、１５０
・・・パッド領域、２５０・・・空き領域、１６０・・
・入出力電極パッド部、１７０・・・入出力回路部、１
８０・・・配線、２１０・・・外部領域、２１１・・・
入出力バッファブロック、２１２・・・入出力回路部、
２１３・・・入出力電極パッド部、２５０・・・空き領
域。FIGS. 1(a) and 1(b) are a layout diagram and an enlarged view of part A showing an embodiment of the present invention, and FIG. 2 is a layout diagram showing an example of a conventional semiconductor integrated circuit. 100.200---LSIF7.110-I/O circuit area, 120... Internal area, 130... Logic circuit block, 132... RAM block, 133...
・ROM block, 140...internal wiring area, 150
...Pad area, 250...Empty area, 160...
- Input/output electrode pad section, 170... Input/output circuit section, 1
80... Wiring, 210... External area, 211...
Input/output buffer block, 212...input/output circuit section,
213... Input/output electrode pad portion, 250... Free area.

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップの中央部に設けた機能ブロック及び前記
機能ブロックの周囲に設けた内部配線領域を有する内部
領域と、前記内部領域の外周に設けた入出力回路領域と
、前記入出力回路領域の外周に設けて任意の位置に配置
し且つ入出力回路と接続する複数列の入出力電極パッド
とを有することを特徴とする半導体集積回路。an internal area having a functional block provided in the center of the semiconductor chip and an internal wiring area provided around the functional block; an input/output circuit area provided on the outer periphery of the internal area; and an input/output circuit area provided on the outer periphery of the input/output circuit area. 1. A semiconductor integrated circuit comprising a plurality of rows of input/output electrode pads arranged at arbitrary positions and connected to input/output circuits.
JP2299529A 1990-11-05 1990-11-05 Semiconductor integrated circuit Pending JPH04171844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2299529A JPH04171844A (en) 1990-11-05 1990-11-05 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2299529A JPH04171844A (en) 1990-11-05 1990-11-05 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH04171844A true JPH04171844A (en) 1992-06-19

Family

ID=17873783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2299529A Pending JPH04171844A (en) 1990-11-05 1990-11-05 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH04171844A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130485A (en) * 1997-12-15 2000-10-10 Nec Corporation Semiconductor integrated circuit and layout method thereof
JP2010117962A (en) * 2008-11-14 2010-05-27 Fujitsu Microelectronics Ltd Layout design method and semiconductor integrated circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130485A (en) * 1997-12-15 2000-10-10 Nec Corporation Semiconductor integrated circuit and layout method thereof
JP2010117962A (en) * 2008-11-14 2010-05-27 Fujitsu Microelectronics Ltd Layout design method and semiconductor integrated circuit
US8637387B2 (en) 2008-11-14 2014-01-28 Fujitsu Semiconductor Limited Layout design method and semiconductor integrated circuit

Similar Documents

Publication Publication Date Title
EP0257437B1 (en) Master slice type integrated circuit
JPH0689962A (en) Semiconductor device
JP2560805B2 (en) Semiconductor device
JPH02152254A (en) Semiconductor integrated circuit device
JPH04171844A (en) Semiconductor integrated circuit
JPH0194636A (en) Semiconductor device
JP2780355B2 (en) Semiconductor integrated circuit device
JPS62285443A (en) Master-slice integrated circuit device
JPS6156441A (en) Semiconductor device
JP2002270779A (en) Semiconductor device
JP2004179184A (en) Semiconductor integrated circuit
JP2561005B2 (en) Semiconductor device
JPH06232328A (en) Loc semiconductor device
JPS63273332A (en) Manufacture of semiconductor integrated circuit device
JPH02306650A (en) Semiconductor device
JPS59145542A (en) Large-scale integrated circuit
JPH01168042A (en) Semiconductor integrated circuit device
JPH02192144A (en) Gate array type semiconductor device
JPH0194637A (en) Semiconductor integrated circuit
JPH08264673A (en) Integrated circuit device
JPH11330371A (en) Semiconductor device
JPH0563165A (en) Semiconductor device
JPS61187249A (en) Semiconductor integrated circuit device
JPH04186749A (en) Semiconductor integrated circuit device
JPH0821625B2 (en) Semiconductor integrated circuit device