JPS61187249A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase driving capacity without lowering the degree of integration, and to prevent the deterioration of performance resulting from the deformation of a bonding-wire by mutually connecting external interface circuits and connecting the external interface circuits and a bonding-pad in a wiring region. CONSTITUTION:External interface circuit forming regions 6a-6d in which a plurality of interface circuits containing no bonding-pad, input-output cells CI/O, are aligned and formed are disposed around an internal circuit forming region 2 through first wiring regions 3. A second wiring region 7 having width in which wirings such as three ones can be arranged is shaped on the outside of the regions 6a-6d, and bonding-pads BP are disposed to a region surrounding the second wiring region 7 on the outside of the region 7, the whole peripheral section of a chip 1, at pitches such as uniform ones. In the gate array-chip, the bonding-pads BP arranged at the corner sections of the chip 1 and the desired input-output cells CI/O are connected by film wirings LA through a master slice method by using the second wiring region 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a mask slicing type semiconductor integrated circuit device, and particularly relates to a semiconductor integrated circuit device using a mask slicing method, and particularly to an external interface region L-J to a complementary MO,S (CMO3) gate array. Regarding structure.

In mask slicing type semiconductor integrated circuit devices, in which an internal circuit with a desired function is constructed from a group of aligned basic elements, as the circuit scale increases, power consumption is reduced and the degree of integration is improved. From an environmental perspective, there is a desire to replace the bipolar elements that conventionally constitute the semiconductor integrated circuit device with complementary field effect (CMO3) elements.

However, in a mask slicing type semiconductor integrated circuit device using CMO3 elements, that is, a CMOS gate array, the CMO3 element has a small current driving ability due to its structure, so it can obtain a current driving ability to the outside comparable to that of a bipolar element. However, it is necessary to make the transistor width extremely large, which significantly expands the width of the area where the external interface circuit is formed, which hinders one of the goals of increasing the degree of integration. There is a need for a structure that prevents expansion of the interface area with the outside.

[Conventional technology]

FIG. 5 is a plan view schematically showing a conventional CMOS gate array. In the figure, 1 is a semiconductor chip, 2 is an internal circuit forming area in which a plurality of hesioxels ClIC are arranged in a grid pattern, and 3 is a plan view schematically showing a conventional CMOS gate array. The wiring areas 4a, 4b, 4c, and 4d are a plurality of input/output cells C1zo including bonding pads BP.
represents the external interface area arranged in a row.

As shown in the figure, in the conventional CMO'S gate array, the circuits are arranged around the internal circuit forming area 2 for logic, etc., in correspondence with the number of internal wirings of the semiconductor pancake on which the gate array chip is mounted. Each of the provided interface circuits, ie, input/output cells Cl10, had a structure in which one bonding bat 'BP connected to each input/output cell Cl10 was provided.

[Problem that the invention seeks to solve]

In such a conventional external interface area structure, adjacent input/output cells CI/. Unless the input/output cells CI/Q are vacant, it is not possible to increase the current driving capacity by connecting the input/output cells CI/Q in parallel, so generally the width of the transistor is expanded within the input/output cell area to increase the current driving capacity. The input/output cell CI/ is configured by arranging the transistors together and configuring an input/output circuit using the transistors. The aim was to increase the current drive capability of the

However, in gate arrays, there is a desire to increase the number of input/output circuits as much as possible, and if this is to be achieved, input/output cells (CI/I/O) must be added. Since the width W of the shape is limited to a predetermined value, the height of the input/output cell can be increased by arranging a transistor with increased current drive capacity within the input/output cell area as described above. performance,
In order to increase the number of functions, the length l of the input/output cell Cl10
will have no choice but to significantly increase.

and for this the interface areas 4a, 4b, 4c
, 4d increases, and wide empty areas are formed at the four corners of the chip where input/output cells cannot be placed.
The degree of integration of gate arrays decreases.

In addition to this, as shown in FIG. 6, which shows the state of wire bonding, the internal wiring of the semiconductor pancake. are also provided in areas facing the four corners of the chip,
A bonding wire BW connecting the internal wiring I, 8ゎ of the region and the bonding band BP of the semiconductor chip 1
Il is significantly longer than the bonding wire BWA at other locations, and this longer bonding wire BWll may hang down and come into contact with the adjacent bonding wire BWB, especially in the case of resin molding type F, etc. There was a problem in that the performance deteriorated due to contact with the end surface of the semiconductor chip 1. (5 is the chip stage) The problem that the present invention aims to solve is that the integration density that occurs with the improvement of the current drive ability is This is a short-circuit failure of the bonding wire.

[Means for solving problems]

゛ The above problem is caused by an internal circuit forming area, an external interface circuit forming area arranged around the internal circuit forming area and in which a plurality of interface circuits between the internal circuit and the outside are formed, and It has a wiring area provided around the interface circuit forming area and a plurality of bonding pads placed around the entire periphery of the wiring area, and in the wiring area, connections between external interface circuits and external The problem is solved by a semiconductor integrated circuit device according to the present invention, in which a connection is made between an interface circuit and a bonding pad.

[Effect]

That is, in the semiconductor integrated circuit device of the present invention, the external interface circuit and the bonding pad are separated,
A wiring area is provided between the external interface circuit forming area surrounding the internal circuit forming area and the bonding pad placement area in which bonding pads are distributed over the entire periphery of the semiconductor chip constituting the semiconductor integrated circuit device. The wiring area is used to make connections between interface circuits and arbitrary connections between interface circuits and bonding pads.

By doing so, it becomes possible to increase the current driving capability of the semiconductor integrated circuit device by connecting a plurality of interface circuits located at distant locations in parallel using the wiring area, and it is possible to increase the current driving capability of the semiconductor integrated circuit device. Since there is no need to provide transistors and the area thereof is reduced, a decrease in the degree of integration is prevented when the current drive capability is increased.

Also, since the interface circuit and the bonding pad are connected using the wiring area, the internal lead and the connection are made at the four corners of the chip facing the internal lead of the semiconductor package in which the semiconductor integrated circuit device is mounted. This makes it possible to arrange a bonding pad that is connected to the semiconductor chip, and the length of the bonding wire in this area can be shortened, thereby preventing performance deterioration due to contact between the bonding wire and an adjacent bonding wire or the end face of the semiconductor chip. Prevented.

〔Example〕

The present invention will be specifically described below with reference to illustrated embodiments.

FIG. 1 is a schematic plan view showing the main parts of a CMOS gate array chip according to the present invention, FIG. 2 is a schematic plan view showing the state of connection between the interface circuit and the bonding butt, and FIG.・Schematic plan view showing the state of wire connection between the band and the internal leads of the package, No. 4
The figure is a schematic plan view (a) showing a state of parallel connection of interface circuits.

A block circuit diagram (bl) and an equivalent circuit diagram (C1) of an example of an interface circuit.

Identical objects are indicated by the same reference numerals throughout the figures.

The CMOS gate array chip according to the present invention is, for example, as shown in FIG.
A first circuit is formed around an internal circuit formation region 2 in which basic cells CNC each consisting of a gate circuit or the like including transistors or MO3I-transistors are arranged in a lattice pattern.
External interface circuit forming area 6a, (
ib.

6c and 6d are arranged, and the second arrangement has a width that allows, for example, three wires to be arranged side by side.
An i eM region 7 is provided, and bonding pads BP are arranged in a uniform pinch pattern in the region surrounding the second wiring region 7 outside the region, that is, in the entire periphery of the chip 1 .

In the gate array chip having the above structure, as shown in FIG. They are connected by the film wiring LA using the mask slicing method.

As described above, in the mask slicing semiconductor integrated circuit device according to the present invention, bonding bands are also provided at the four corners of the chip.

Therefore, as shown in FIG. 3, the length of the bonding wire BWH connecting the internal lead L in of the package facing the corner part of the chip 1 and the bonding pad BP is set to 1" I-i within the other area. , and the bonding wire lung connecting the bonding pad BP can be shortened to almost the same length, and the strength of the bonding wire BW can be increased. (5 is the chip stage ) Therefore, deformation of the bonding wire BW during, for example, a resin molding process is reduced, and performance deterioration due to contact between the bonding wires or between the bonding wires and the chip is prevented.

In addition, in the gate array chip described above, as shown in FIG. 4, the drive capability is increased by using the film wiring LI1 formed by the mask slicing method using the wiring regions 3 and 7 to connect the input/output cells Cl10- a, Cl10-B,
Cl10-C% or Cl10-+, Cl10-E
, CI/. This can be achieved by connecting I+Cl10-G, etc. in parallel.

FIG. 4 (Al is a block circuit diagram of the driving ability increasing means, ``■'' is the case where the driving ability is 1, ``■'' is the case where the driving ability is 2, and ``■'' is the case where the driving ability is 3.

In the figure, G indicates an output gate and BP indicates a bonding pad.

Also, in FIG. 4 (bl shows a CMOS inverter which is an example of an output gate, and T in the figure shows an n-channel Mo
s+ transistor, Tp p channel MOS transistor, VCC is power supply, GND is ground, IN is input terminal, 0
IIT represents an output terminal.

As described above, in the gate array according to the present invention, it is possible to increase the driving capacity by using vacant input/output cells without expanding the input/output cells. A decrease in the degree of integration of the integrated circuit device is prevented.

〔Effect of the invention〕

As explained below, according to the present invention, it is possible to increase the driving capacity of a mask slicing semiconductor integrated circuit device without reducing the degree of integration, and to improve the performance caused by the deformation of the bonding wire. Deterioration is prevented.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view showing the main parts of a CMOS gate array chip according to the present invention, FIG. Figure 4 is a schematic plan view showing the state of wire connection between the bonding path l- and the internal leads of the package; Figure 4 is a schematic plan view showing the state of parallel connection of the interface circuit; An equivalent circuit diagram fcl of an example of a face circuit, Fig. 5 is a conventional C
Figure 6 is a plan view schematically showing a MOS gate array.
FIG. 3 is a schematic plan view showing the state of wire connection between the band and the internal leads of the package. In the figure, 2 is a semiconductor chip, 2 is an internal circuit formation area, 3 is a first wiring area, 6a, 6b, 6c, and 6d are external interface circuit formation areas, 7 is a second wiring area, CEC is a hexoxel, CIlo, Cl10-A, CIlo-B, Cl1
0-C. Cl1O-11, Cl1O-EI Cl10-F, C
110-G is an input/output cell, BP is a bonding band, LA, I-8 are film wirings, Li, , are internal leads of the package, and BW, , BW, are bonding wires. Thing 4 Threshold--C>-" 1-cho-1111ρr No. 6 Shout-Lin BWA

Claims (1)

[Claims] an internal circuit forming area; an external interface circuit forming area disposed around the internal circuit forming area in which a plurality of interface circuits between the internal circuit and the outside are formed; It has a wiring area provided at the periphery and a plurality of bonding pads arranged around the entire periphery of the wiring area, and in the wiring area, connections between external interface circuits and bonding between external interface circuits and the external interface circuits are made. A semiconductor integrated circuit device characterized in that a connection is made between a pad and a pad.