JPS5844741A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enhance the using efficiency of an internal cell region in a master and slice type gate array LSI by forming part of the logic circuit of an internal cell in an I/O cell. CONSTITUTION:Since an internal cell 1 is formed at a high speed and is highly integrated, it is disposed at the center of a chip in a small size, an I/O cell 3 has a high load drive capacity in a relatively large size at the outside. Accordingly, when the power wirings 6 become thick due to the high integration of the gate array LSI, the unused vacant region of the I/O cell region 4 is increased. Accordingly, the logic function of the stationary structure formed by utilizing the conventional internal cell is incorporated in the I/O cell which increases in the exclusive area as the power source wirings increases in thickness. In other words, the logic function of the original stationary structure is incorporated in the I/O cell 3 which is nearly fixed with low degree of freedom of wiring, and the logic function required for the further degree of freedom is formed in the internal cell region 2. According to this structure, the unused region of the region 4 can be activated, thereby improving the using efficiency of the internal cell region.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a custom semiconductor integrated circuit (IC) in which circuit elements prepared in advance according to a user's purpose are connected by metal sputtering or the like during a semiconductor manufacturing process.
Regarding.

For example, a master slice r-dore array LSI has a large number of basic cells arranged in an array and has a maximum resistance of 900 nm, and uses combinations of wiring layer designs to connect within and between these basic cells. This is an IC that can automatically perform this process to configure a wide variety of products in one type of bulk.

Figure 11 shows the f-) play LSI constructed one size above the other, and Figure 1 (03) shows an enlarged corner portion of the LSI. This f-) array LSI is composed of an array 1-1 of internal cells 1 and a rounded inter-cell automatic wiring area (channel area) 2-1 for automatically wiring the internal cells 1 to each other, and an internal area forming a logic circuit. The cell area 2 and the internal cell 1 provided outside the internal cell area 2 and the IC chip! l7t) cell area 4 consisting of I/l) cell 3 for l10 (input/output) nototsufa for the purpose of electrical interface with the outside
and a VCC power supply at the chip periphery formed in a planar shape on the upper surface of the I10 cell region 4, as well as a ground twin 6-1 and an internal cell region 2, which are provided vertically in the figure.
A power supply wiring @6 and power source consisting of a linear ground line (a type of power supply) 6-2 and a horizontally laid linear VCC power line 6-3, draw 4, and I10 cell. In the parable of the eccentric code connected to 3, it becomes do 5 and p. In the eleventh prisoner, the peripheral portion 6-1 of the power supply wiring 6, the ground line 6-2, and the Vcc power supply twin 6-3 are omitted from illustration for clarity of the drawing.

In general, a dirt array consists of a first wiring layer that mainly forms wiring in the X direction, a 1li2 wiring layer that mainly forms wiring in the Y direction, and internal cells and I/I wiring layers that connect them through holes such as peer holes. ) connects the circuit elements of the cell. The internal cell area is provided in the center of the chip, and the external cell area 4 is provided between the internal cell area 2 and the f. The narrow power supply wiring 6-1 is provided in the second wiring layer on the external cell region 4, and the thin power supply wiring 6-2 and 6-3 from Q) to the internal cell region are provided in the second wiring layer, respectively. ．． It is formed in the first wiring layer. Therefore, the I10 cell region 4 is mainly limited by the shape of the surrounding power supply wiring 6-1.

The internal cell, I10 cell, is a collection of circuit elements such as transistors, diodes, resistors, capacitors, etc., and by connecting these circuit elements within the cell, a basic logic circuit can be constructed. It is something.

These cells are called basic cells.

Connections are made within these cells and between cells by eleventh and second wiring layers. Internal cells are connected using the first and second wiring layers, and the degree of freedom in wiring is large. on the other hand,! The second wiring layer on the Oki cell area 4 is already connected to the power supply wiring 6.
Since it is used as the 0 peripheral part 6-1, the elements of the I/b cell are mainly connected through the first wiring layer. In other words, the degree of freedom in wiring is extremely small compared to in-house cells, and the wiring is almost fixed.

Further, the internal cell 1 is formed as small as possible to satisfy high speed and high integration. On the other hand, the I10 cell 3 has a high load driving capability and is relatively large.

Internal cell 1 is I10 cell 3 because it needs to have low power consumption.
Compared to the power supply voltage, the threshold voltage is lower, this rounding! The Oki cell 3 is required to have a voltage level conversion function to match the maximum voltage between the outside of the chip and the internal cell 1. In this way, since the I10 cell 3 and the internal cell 1 have different functions and cell sizes, they were not treated as the same cell and were not automatically interconnected.

On the other hand, in the case of ■C, the peripheral part of the power supply wiring 60 that supplies power to the cell 1.3 and the I/ll cell region 4 form a multilayer structure. The 40 area of Okishichiru area was almost determined by power lines. In other words, since it is smaller than that of the I10 cell area 4 and the 11th cell line required by I10 cell 3, (*The indicated area had an unused empty area. The empty area has become larger as the gate array LSI becomes more highly integrated and the power supply wiring 6 becomes thicker.

In addition, if the logic circuit in internal cell area 2 requests both positive phase and negative phase for the input signal, I10 cell 3
Since the function for external signals of the above-mentioned I.
Two internal cells 1 had to be connected to the output terminals of the 10 cells 3 to the internal cells 1, and one had to be used for the F function and the other for the inverter function. That is, FIG. 2 shows a circuit diagram of such a conventional example, in which the signal line pad 5 is connected to the input 9 of the buffer 8 of the I/L cell 3, and its output 10 is provided in the internal cell area 2. The inverters l l , /l v are connected to respective inputs 13 , 14 of the edge 12 . Output 1 of Inno-Yu 11
5 is applied to the inputs 18, 19 of the inverter 16.17, and the output 20 of the appetizer 12 is applied to the input 23,24 of the inverter 21,22.

Outputs 25-28 of inverters 16, 17, 21, 22 are connected to inputs 30, 31, 32, 33, 34, 35, 36 and 37 of logic circuit group 29. Chi via pad 5,
The signal input into f is sent to buffer 8 in I10 cell 3.
and is converted to the internal cell lO decoding level in the chip vf. The output of /41778 is applied to the buffer 12 and inverter 11, and a normal phase signal and a negative phase signal are formed with respect to the input signal. These signals are sent to logic circuit group 2.
Inverter 16.17, 21.2 for 90 inputs 30-37
2. Since the logic circuit group 29 requires a positive phase signal and a negative phase signal, the buffer 12, IN/? - Two internal cells 1 of 11 are required for the logic circuit group 290 input section and the buffer 18 section.

This reduces the usage efficiency of the internal cell area 2 where the rounded note internal cell 1 exists.

Also, as mentioned above, 1+? The two internal cells of /F 12 and inverter 11 are connected to the input part of logic circuit group 29 and I
The structure provided between the 10-cell buffers 8 is often used in dirt arrays, and forming such a fixed structure in the internal cell area with a high degree of freedom in wiring increases the efficiency of internal cell usage. It lowers the

The present invention has been made in view of the above-mentioned conventional drawbacks, and its objects are: (1) to improve the efficiency of use of the cassette area and the internal cell area;

An object of the present invention is to provide an I10 cell, which has an increased area as a result of thicker power supply lines, with a logic function of a fixed structure, which has conventionally been constructed using internal cells.

That is, the I10 cell, which has a low degree of freedom in wiring and is almost fixed, is provided with a logic function which originally has a fixed structure, and the internal cell area is configured to have a logic function that requires a greater degree of freedom.

The semiconductor integrated circuit device according to the present invention is characterized in that a plurality of internal cells each having a plurality of circuit elements are arranged in a play shape in the center of the surface of the substrate to form an internal cell area. A plurality of I10 cells each having a plurality of circuit elements are arranged around the surface to form an I/l) cell area. % 1 m The I10 cell area converts the signal level between the internal cell area and the outside of the device. The wiring layer connecting the circuit elements on the substrate is at least the first. It has a second wiring layer, and the circuit elements of the internal cells are connected by at least the first and 20th wiring layers to form a predetermined logic circuit. In a semiconductor integrated circuit device in which a region of the second wiring layer on the Oki cell region is used as a power supply wiring, a part of the logic circuit is connected to the! Each in the Oki Cell area! It is formed within the Oki cell.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows an embodiment of the present invention. A sofa 1 for level conversion is placed in the sand cell 40.

Input signal line pad 5 is connected to input 42 of buffer 41, whose output 43 is the same! Inputs 46.4 of the inverter 44 and buffer 45 arranged in the Oki cell 4o
Connected to 7. The respective outputs 48° and 49 of the inverter 44 and the Δ sofa 45 are output from the I107 circuit 40. Figure 4 shows the figure 3! A reciprocal signal output circuit 5 which includes the Oki cell 40 in one single circuit and has mutual outputs.
FIG. 5 shows a configuration in which the conventional circuit configuration shown in FIG. 2 is implemented using the present invention. Δ, 5 is connected to the input of the reciprocal output circuit 50, and the inverted output 52 of the reciprocal output circuit 50 is connected to the inverter 16.17, and the positive phase output 5 is connected to the input of the reciprocal output circuit 50.
3 is connected to the inverter 2'1°22. Inverters 16, 17° 21.22 and logic circuit group 29
is formed in the internal area of the chip.

As is clear from the embodiments of the present invention shown in FIGS. 3 to #I5, by having a reciprocal output function in the I107 cell 40, nine reciprocal functions that were conventionally performed in the internal cell area 2 can be used. That is, internal cells for buffers and inverters are not required. As shown in Figure 3! The inverter 44 and buffer 45 installed in the Oki cell 40 have a multilayer structure with the power line, and the part corresponding to the power line! Free space in Oki cell area 4 can be used. Therefore, the chip to which the present invention is applied has the same area as the conventional chip, and the inside of the internal cell region 2 can be used more effectively than the conventional chip. Furthermore, it is clear that current branches within the internal cell region 2 can also be reduced.

FIG. 6 shows a second embodiment of the present invention. This is an example in which two opposite phase signals are output with respect to the input signal applied to the Oki cell 40. That is, the input signal line /fts P5 is connected to the input 55 of the children's sofa 54. The output 56 of the buffer 54 is connected to the respective input 59 of the inverter 57.88.
．． Added to 60. The respective outputs 61 and 62 of the inverters 57 and 58 are outputted from the cassette 4o. 7th
The diagram is in Figure 6! #! shows a circuit 63 that outputs two anti-phase signals with respect to the input signal with a signal indicating the offset. 8
The diagram is in Figure 6! A circuit 64 which outputs two normal-phase signals in response to an input signal is shown in a singel similar to the cassette.

As mentioned above, having two negative phase outputs or two positive phase outputs can drive, for example, twice as much load as the conventional case of having one output. The same effects as in the embodiment are achieved.

FIG. 9 shows a level conversion buffer 4 in the I10 cell 4o.
3 is a detailed circuit diagram of the embodiment shown in FIG. 3, which is provided with an inverter 44 and a buffer 45.

The dopel converter, that is, the buffer 4◆ is connected to the resistor 8. #Diode Ql, Q・eQl, transistor Q.

It's okay. In-shu-yu 44 has a resistance R,,R,.

R4, diode Qs-Q・, Q・, transistor Q
It's ssQ4. The buffer 45 is a resistor Rv.

R1'sR4', diode Qs' e Q@' a
Qe' is the transistor Qll *Q*s. The input of the level conversion converter 44F is the pace of the transistor Q, and its output is the diode Qm-Q.
is the point 70 where the two are connected. The inputs of the input circuit 44 and the pins and pins 7a 45 are both transistors QlOt-
67, and the respective outputs are connected to diodes Qs and Q
seQi' and Qs' are transistor Q4.

The point 68.73 is connected to Ql. In addition, the ground line 7 is connected to the power supply VCC line 71 of the 1/4 power supply 41.
For example, 5V is applied to the inverter 44,
For example, 2.3V is applied to the power supply Vcc line 72 of the buffer 45, so the buffer 41 performs level conversion of different operating voltages.

As described above, according to the present invention, the power distribution 1II6 lower OI
/l) Because automatic wiring between cells cannot be performed in the empty area of cell area 4, the wiring within the cell is used to connect transformers, transistors, resistors, etc. within one cell to perform logic functions. That is. Conventionally, internal cells were used to obtain, for example, two contradictory output signals, but according to the present invention, for example, buffers and inverters are configured within the I10 cell without using internal cells, so the use of internal cells is simplified. Efficiency is improved and allows for more complex logic configurations in internal cells.

[Brief explanation of drawings]

The 11th prisoner is a block diagram of the semiconductor chip and f, Figure 2) is a partially enlarged diagram, and Figure 2 is a circuit block diagram of a conventional semiconductor integrated circuit.
FIG. 3 is a circuit configuration diagram showing the first embodiment of the present invention;
The figure shows the circuit of Figure 3 in one singel, Figure 5 is a circuit configuration diagram implementing the present invention, and Figure 6 is the R2 of the present invention.
FIG. 7 is a circuit configuration diagram showing an example of the circuit shown in FIG. 6.
8 is a diagram showing a modification of the circuit in FIG. 6 using one singel, and FIG. 9 is a circuit diagram of the embodiment shown in FIG. 3.・Internal cell, 2 ・Internal cell area, 3.40・
... I10 cell, 4...■ Clean cell area, 5. −・・Δ
, Do, 41.45#54.../gusofa, 44,57
, 58... Inno quantity - ta blue 2 figure 1*' 3 figure 0 blue 5 figure chifu

Claims (1)

[Claims] A plurality of internal cells each having a plurality of circuit elements are arranged in an array in the center of the surface of one substrate to form an internal cell area. A plurality of I10 cells having circuit elements are arranged to form an x7o cell area &'
p s t; Ii I10 cell region converts the signal level between the internal cell region and the outside of the device), on the substrate there are at least 11th and 2nd wiring layers connecting the circuit elements. wiring layer, the circuit elements of the internal cells are connected to at least 19 of the first and second wiring layers to form a predetermined logic circuit, and scissors! In a semiconductor integrated circuit device in which a region of a second wiring layer on an Oki cell region is used as a power supply wiring, a part of the logic circuit of the internal cell is connected to the! A semiconductor integrated circuit formed in each I10 cell in an Oki cell region. 2. The semiconductor according to claim 1, wherein the I/'0 cell area is a plurality of I/lJ cells, and each I10 cell has a plurality of outputs in response to input signals outside of integrated circuit,. 3. Check the 1/b cell above! 3. The semiconductor integrated circuit according to claim 2, wherein the plurality of outputs in response to an input signal from the outside are each in a positive phase and/or a negative phase. 46. The semiconductor integrated circuit according to claim 1, wherein the l/l) cell in the I10 cell region forms a part of the logic circuit by intra-cell wiring.