JPS6012751A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain multi-functions with the minimum number of elements by a method wherein an input circuit and an output circuit are prepared for every given input-output terminal, and then input circuits are arranged and connected to terminals, respectively, in the construction of a desired circuit by the connection of either one circuit to the input-output terminal. CONSTITUTION:A logic circuit having desired logic functions is constructed in an Si substrate 1 by a master slicing method, and a plurality of bonding pads P1-P6 are formed by corresponding to those, each of which is then connected to an input-output pin. In this construction, a basic input circuit cell CCi and a basic output circuit cell CCo are put into a pair and connected to the pad P1; thereafter one-pairs of the same construction are connected to respective pads of the pad P2 and the rest. Here, a plurality of transistor elements, resistance elements, and the like are formed in the CCi and the CCo in such a manner that a desired input circuit or output circuit can be constituted, respectively, and accordingly the wiring connection between adjacent input circuits is facilitated.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to circuit technology, and more particularly to a technology that is particularly effective when applied to semiconductor integrated circuits, such as LSI (Large-Scale Integrated Circuit) formed by master slicing method. ]
It is related to effective technology that can be used for.

[Background technology]

The present inventor has developed the following technology for logic master slice type integrated circuits.

In a logic LSI such as a gate array formed by the master slice method (hereinafter referred to as master slice LSI), a basic human circuit cell and a basic output circuit cell are provided for each input/output pin. By allowing any buffer circuit to be configured, the degree of freedom in design can be improved. In this way, when providing a basic human power circuit cell and a basic output circuit cell for each input/output pin, as shown in FIG. In response to ..., the general design method for this technology is to alternately arrange the basic human power circuit cell CCi and the basic output circuit cell CCo and connect either one of the circuits. Conceivable.

However, if the basic human circuit cells CCi and basic output circuit cells CCo are arranged alternately in this way and the number of elements in each circuit cell is kept to a minimum, each input/output circuit has a buffer circuit. The present inventor has clarified that it is possible to provide only a function.

[Purpose of the invention]

An object of the present invention is to provide a circuit technology that provides novel effects. Another object of the present invention is to enable, for example, an input circuit of a semiconductor integrated circuit to have a plurality of logic functions in addition to the function of a buffer circuit.

Still another object of the present invention is to provide a master slice LSI.
The purpose of this invention is to enable each basic input/output circuit cell to have multiple functions using a minimum number of elements when applied to a computer.

The above and other objects and novel features of the present invention include:
It will become clear from the description herein and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the present invention provides, for example, in a logic LSI configured by the mask slicing method, by arranging the input/output circuit provided for each input/output pin in parallel with the input/output circuit of the adjacent input/output pin, The above object is achieved by allowing adjacent input/output circuits to form a two-man power circuit, a power gate circuit, a wired-OR circuit, or the like.

〔Example〕

FIG. 2 shows a schematic configuration when the present invention is applied to a master slice LSI.

In the figure, 1 is a semiconductor substrate such as a silicon substrate, and a master slicing process is performed on this semiconductor substrate 1.
Accordingly, a logic circuit having a desired logic function is constructed. Further, on the periphery of the semiconductor substrate 1, a plurality of bonding pads P are connected to input/output terminals (not shown) as input/output terminals by wire bonding.

PI * PI e... is formed.

In this embodiment, each of the above-mentioned bonding pads P
A set of basic human power circuit cells CCi and basic output circuit cells CC8 are provided corresponding to I t p, l, . . . , respectively. Moreover, the basic human power circuit cell CO and the output circuit cell CC0 are arranged in line with the basic human power circuit cell CC or the basic output circuit cell CC6, which are respectively connected to adjacent bonding pads. In other words, two basic human circuit cells CCi are arranged side by side,
Meanwhile, the basic output circuits SE/L= and CCo are connected to 2 in the same way.
They are arranged one by one.

Note that a plurality of transistor elements and resistor elements are formed in advance in each of the basic human power circuit cells CCi and basic output circuit cells CCo so that desired input circuits or output circuits can be configured, respectively. By appropriately selecting and connecting them during wiring formation using the master slicing method, it is possible to construct an input circuit or an output circuit having desired signal characteristics and driving ability.

According to the master slice LSI of the above embodiment, p! Two connected basic human-powered circuit cells CC1 can be used to construct a two-human logic circuit, one power gate with a large drive capacity, or wiring to take a wired OR of two circuits. Since it is easy to perform, the function of the input circuit can be strengthened. Further, similar effects can also be obtained with respect to the output circuit.

Next, a more specific embodiment of an input circuit in which the present invention is applied to a bipolar gate array composed of bipolar transistors will be described in detail with reference to FIG. 1g3.

Two adjacent bonding pads P, P
, two basic human circuit cells C are provided corresponding to
Only C, □ and CCi are shown.

These two basic human power circuit cells CCN1 and CC12 are formed so that the layout of internal elements is symmetrical with #v.

Moreover, the elements in each of the basic human power circuit cells CCi□ and CCl2 are formed so as to be arranged substantially in a straight line, so that the entire cell forms an elongated rectangle.

Although not particularly limited, a bonding pad PI.

P! Basic human power circuit cells CC, □, and CC are on the side closer to .

A power supply line L for supplying a power supply voltage Vgl is provided so as to pass through the power supply line L, and a resistor RII is connected to the power supply line L.
i, are provided near the boundary between adjacent cells so as to be close to each other. Further, a branch transistor Q is also provided close to this resistor. This transistor Q3 is provided for constant current, and the resistor R is provided as its emitter resistance.

Next, a pair of differential transistors Q, , Q, are arranged in parallel near the transistor Q3, and beyond that, the transistors Q, , ,
Collector resistors C11 and FLCm are arranged in parallel. In addition, the collector resistances Rcm, R of these Q, ,Q,
At both ends of C2, there is a power line L! for supplying the power supply voltage VCC to the circuit so as to pass through the basic human power circuit cells CC, , CC, 2. and L; are provided.

Furthermore, in the vicinity of the collector resistor R6□l RCfl, there is a transistor Q4 +Q for emitter/7 lower,
However, a resistor "LNI" for the emitter follower is also formed in the vicinity thereof, and a power supply line L for supplying the power supply voltage VTT is formed outside of the resistor "LNI".

is arranged so as to penetrate through cells CC1 and CCl2.

Each of the above-mentioned basic human power circuit cells CC11 and CC12 is formed with wiring as shown by the broken line in the figure to connect each element, and a constant voltage ■c is applied to the base of the transistor Qs.
s is applied, and an input signal ■ is applied to the transistor Q.
In's 7. Voltage between high level and low level■. By applying , an ECL (emitter coupled logic) circuit as shown in FIG. 3 is formed. In this case, an OR output can be taken out from the emitter side of the emitter follower transistor Q, and a NOR output can be taken out from the emitter side of the transistor Q.

Moreover, in the circuit of the above embodiment, corresponding elements in the two basic human circuit cells CC11 and CC'i arranged in parallel are arranged close to each other. Therefore,
By connecting the corresponding elements in parallel with wiring, the current is twice as much as when the elements in one cell are connected to form the ECL circuit shown in Figure 3. You can make it flow. As a result, the parasitic capacitance of the inter-gate wiring and the driving capability of the load gate are increased, and a power gate circuit is constructed.

In addition, only one basic human power circuit cell CC11 is connected as shown by the broken line to form an ECL circuit, and the other basic human power circuit cell CCi uses only the input transistor capacitor, which is connected to the inside of cell CC41. input transistor Q
, and the input transistor Q in the cell CC11.

The base of the bonding pad P! is shown by the two-dot chain line A in the figure. By connecting to the E
It becomes possible to configure a CL circuit.

Furthermore, the basic human circuit cell CC, 2 is used as a resistor for the emitter follower. CC11 and tl except for
are connected in the same way to form an ECL circuit, with corresponding resistors RLN and R1 in cell CC11. is connected so that it is shared by two input circuits (ccill CCl2). Then, a wired OR of the two input circuits can be obtained.

In the above embodiment, the basic human circuit cell CC1
Only within 1, connect the emitter and 7 lower resistor to RLN.
In addition to IRLO, a resistor LP is provided, and when a power gate is configured as described above, the emitter follower resistor LNIR in the basic human circuit cell CC12 is provided.
Without using LO, this separately prepared resistor "LP is used to increase the resistance of cell CC11'!LN#"L. It is now possible to connect them in parallel. This makes it extremely easy to design wiring when configuring a power gate.

〔effect〕

By distributing input circuits for multiple input/output terminals side by side with input circuits for adjacent input/output terminals,
By making wiring connections between adjacent input circuits easier, it becomes possible to easily configure a two-person circuit, a power gate circuit, a wired OR, etc. using two input circuits. Furthermore, the function of the input circuit is increased, the logic function is strengthened, and the number of logic gates of the entire LSI is increased.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

[Application field]

In the above description, the invention made by the present inventor was mainly applied to bipolar master slice LSI, which is the field of application in which the invention is based, but the invention is not limited thereto.

Logic LSI with MOS gate array and individual input circuits
Generally applicable. Further, the present invention provides a logic LSI
The present invention is not limited to, but can be widely applied to memory integrated circuits and other signal processing LSIs.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing the layout configuration of the input/output circuit in a master slice LSI developed by the present inventor prior to the present invention, and FIG. 2 is the layout of the input/output circuit when the present invention is applied to the master slice LSI. FIG. 3 is an explanatory diagram showing an example of the structure of the basic human-powered circuit cell; FIG. 4 is a circuit diagram showing an example of an input circuit configured thereby. 1...Semiconductor substrate, P...Ponding pad, C
Ci...Basic human power circuit cell, CCo...Basic output circuit cell, Q,,Q,...Input transistor, Q3.
・・ Constant current transistor, Q, , Q, ・・Emitter/7 lower transistor, Ll , Lt , Lm ・・
・Power line. Figure 1 Figure '2

Claims (1)

[Claims] 1. In the case where an input circuit and an output circuit are prepared for each given input/output terminal, and either one of the circuits is connected to the input/output terminal to configure a desired circuit. . A semiconductor integrated circuit characterized in that input circuits for the plurality of input/output terminals are arranged side by side with input circuits for adjacent input/output terminals. 2. A semiconductor integrated circuit configured into a desired logic circuit using the master slicing method, in which a basic human circuit cell and a basic output circuit cell are provided for each bonding pad connected to the input/output terminal. 2. The semiconductor integrated circuit according to claim 1, wherein the basic input/output circuit cells are arranged side by side with adjacent basic input/output circuit cells.