JPH02275653A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02275653A JPH02275653A JP9791889A JP9791889A JPH02275653A JP H02275653 A JPH02275653 A JP H02275653A JP 9791889 A JP9791889 A JP 9791889A JP 9791889 A JP9791889 A JP 9791889A JP H02275653 A JPH02275653 A JP H02275653A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- cells
- output cells
- fundamental
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 9
- 239000011295 pitch Substances 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に、マスタースライス方
式の半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a master slice type semiconductor device.
従来、この種の半導体装置は1つの入出力パッドに対し
て、1つの入出力セルが対応していた。Conventionally, in this type of semiconductor device, one input/output pad corresponds to one input/output cell.
上述した従来の半導体装置は1つの入出力パッドに対し
て1つの入出力セルが対応しているため、1つのマスタ
ースライスにおいて、とりうるパッドピッチについては
、1つの入出力セルのピッチより大きくなるという欠点
がある。In the conventional semiconductor device described above, one input/output pad corresponds to one input/output cell, so the possible pad pitch in one master slice is larger than the pitch of one input/output cell. There is a drawback.
本発明の半導体装置は入出力セルが従来の入出力セルよ
り小さい、基本人出力セルによって構成され、入出カブ
ロックはこの基本人出力セルを複数個組合わせて構成さ
れる。The semiconductor device of the present invention is constituted by basic human output cells whose input/output cells are smaller than conventional input/output cells, and the input/output block is constructed by combining a plurality of these basic human output cells.
第1図は本発明の第1の実施例のレイアウト図である。 FIG. 1 is a layout diagram of a first embodiment of the present invention.
1は基本人力セル、2は入出力パッド、3は基本人出力
セル上に構成された入出カブロックである。この場合、
1つの入出力パッドに対して4つの基本人出力セルが対
応している。1 is a basic human power cell, 2 is an input/output pad, and 3 is an input/output block configured on the basic human output cell. in this case,
Four basic output cells correspond to one input/output pad.
第2図は本発明の第2の実施例のレイアウト図である。FIG. 2 is a layout diagram of a second embodiment of the present invention.
この実施例においては第1図と同一のマスタースライス
を使用して1つの入出力パッドに対応して3つの基本人
出力セルを対応させている。In this embodiment, the same master slice as in FIG. 1 is used, and three basic output cells are made to correspond to one input/output pad.
以上説明したように本発明は、入出力セルを小さな基本
人出力セルによって構成する事により、入出力パッドの
ピッチを、この基本人出力セルの整数倍にする事で、異
なるパッドピッチを同一マスタースライス上で実現でき
る効果がある。As explained above, in the present invention, by configuring the input/output cells as small basic output cells, and by making the pitch of the input/output pads an integral multiple of the basic output cells, different pad pitches can be controlled by the same master. There are effects that can be achieved on slices.
第1図は本発明の第1の実施例のレイアウト図、第2図
は本発明の第2の実施例のレイアウト図、第3図は従来
の半導体装置のレイアウト図である。
1・・・基本人出力セル、2・・・入出力パッド、3・
・・入出カブロック、4・・・従来の入出力セル、5・
・・従来の入出力セル上に構成された入出カブロック。FIG. 1 is a layout diagram of a first embodiment of the invention, FIG. 2 is a layout diagram of a second embodiment of the invention, and FIG. 3 is a layout diagram of a conventional semiconductor device. 1... Basic human output cell, 2... Input/output pad, 3...
...Input/output block, 4...Conventional input/output cell, 5.
...I/O block configured on conventional I/O cells.
Claims (1)
力パッドに対して、少なくとも2つ以上の入出力セルが
対応している事を特徴とする半導体装置。A master slice semiconductor device characterized in that at least two input/output cells correspond to one input/output pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9791889A JPH02275653A (en) | 1989-04-17 | 1989-04-17 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9791889A JPH02275653A (en) | 1989-04-17 | 1989-04-17 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02275653A true JPH02275653A (en) | 1990-11-09 |
Family
ID=14205082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9791889A Pending JPH02275653A (en) | 1989-04-17 | 1989-04-17 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02275653A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08186176A (en) * | 1994-12-28 | 1996-07-16 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
US5760428A (en) * | 1996-01-25 | 1998-06-02 | Lsi Logic Corporation | Variable width low profile gate array input/output architecture |
US5777354A (en) * | 1994-09-16 | 1998-07-07 | Lsi Logic Corporation | Low profile variable width input/output cells |
US5917207A (en) * | 1993-07-01 | 1999-06-29 | Lsi Logic Corporation | Programmable polysilicon gate array base cell architecture |
US5945696A (en) * | 1998-02-16 | 1999-08-31 | Faraday Technology Corp. | Silicon chip having mixed input/output slot structure |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6012751A (en) * | 1983-07-01 | 1985-01-23 | Hitachi Ltd | Semiconductor integrated circuit |
JPS62285443A (en) * | 1986-06-03 | 1987-12-11 | Fuji Photo Film Co Ltd | Master-slice integrated circuit device |
-
1989
- 1989-04-17 JP JP9791889A patent/JPH02275653A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6012751A (en) * | 1983-07-01 | 1985-01-23 | Hitachi Ltd | Semiconductor integrated circuit |
JPS62285443A (en) * | 1986-06-03 | 1987-12-11 | Fuji Photo Film Co Ltd | Master-slice integrated circuit device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5917207A (en) * | 1993-07-01 | 1999-06-29 | Lsi Logic Corporation | Programmable polysilicon gate array base cell architecture |
US5777354A (en) * | 1994-09-16 | 1998-07-07 | Lsi Logic Corporation | Low profile variable width input/output cells |
JPH08186176A (en) * | 1994-12-28 | 1996-07-16 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit device |
US5760428A (en) * | 1996-01-25 | 1998-06-02 | Lsi Logic Corporation | Variable width low profile gate array input/output architecture |
US5945696A (en) * | 1998-02-16 | 1999-08-31 | Faraday Technology Corp. | Silicon chip having mixed input/output slot structure |
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