JPH04368175A - Master slice lsi - Google Patents

Abstract

PURPOSE:To form the required numbers of electrodes in a desired position on a chip in a master slice LSI. CONSTITUTION:A master slice LSI is formed by forming a circuit element regardless of for an inside circuit and for a buffer circuit almost all over a chip 11, by forming a buffer circuit by wiring a specified circuit element to form the buffer circuit in accordance with the position and the number of electrodes, and by forming an inside circuit by wiring other circuit elements. Therefore, the required numbers of electrodes 13 can be formed at a desired position on the chip 11.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice LSI in which a required number of input/output electrodes can be arranged at desired positions on a chip.

0002

2. Description of the Related Art FIG. 4 is a plan view of a conventional master slice LSI.

As shown in FIG. 4, a plurality of internal cells consisting of circuit elements such as transistors and resistors are formed in an internal circuit area 2 at the center of the chip 1, and buffers around the internal circuit area 2 of the chip 1 are formed. A plurality of peripheral cells are formed in the region 3, and these cells are wired to form internal circuits with desired configurations and a plurality of buffer circuits, and electrodes 4 for input/output are formed corresponding to each buffer circuit. has been done.

At this time, circuit elements for internal circuits and buffer circuits constituting the internal circuit and buffer circuit, respectively, are formed in an array in the internal circuit area 2 and buffer area 3 in the master process, and in the slicing process, these circuit elements are are wired to have a desired circuit configuration to form a master slice LSI.

[0005]

[Problems to be Solved by the Invention] Since the conventional master slice LSI is configured as described above, the number of input/output terminals of the LSI is limited to the so-called number of input/output terminals of the LSI in which the circuit elements constituting the internal circuit and buffer circuit are arranged. Since the number of input/output terminals is limited by the master chip, if the number of input/output terminals is insufficient, a master chip with a large chip size must be used, resulting in a large amount of unused area on the chip. Since the electrodes 4 can only be formed on the periphery of the chip 1, there is a problem in that the range of application cannot be expanded.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to enable a required number of electrodes to be formed at desired positions on a chip in a master slice LSI.

[0007]

[Means for Solving the Problems] A master slice LSI according to the present invention has circuit elements such as transistors and resistors formed on almost the entire surface of the chip, and buffer circuits are formed according to the position and number of electrodes. wiring the circuit elements and wiring the circuit elements to form an internal circuit;
It is characterized in that an internal circuit and a plurality of buffer circuits are formed on the chip, and input/output electrodes are formed corresponding to each of the buffer circuits.

[0008]

[Operation] In this invention, circuit elements are formed on almost the entire surface of the chip, regardless of whether they are for internal circuits or buffer circuits.
Since the buffer circuit is formed by wiring predetermined circuit elements to form a buffer circuit according to the position and number of electrodes, it is possible to form the necessary number of input/output electrodes at desired positions on the chip. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a plan view of an embodiment of a master slice LSI according to the present invention.

As shown in FIG. 1, circuit elements such as transistors and resistors are formed in a spread area 12 covering almost the entire surface of a chip 11, without distinction between internal circuits and buffer circuits. , predetermined circuit elements are wired to form a buffer circuit according to the position and number of electrodes, and predetermined circuit elements are wired to form an internal circuit, so that the internal circuit and a plurality of buffer circuits are connected to the chip 11. Input/output electrodes 13 are formed in a wiring process or an electrode forming process in correspondence to each buffer circuit.

At this time, for example, as shown in FIG. 2, when four LSIs 14 having electrodes around the chip are arranged in a rectangular shape, input/output terminals are placed so as to partially overlap the electrodes 15 of these LSIs 14. When the electrodes 13 are formed in a cross shape, a plurality of buffer circuits are formed by wiring the circuit elements in the cross-shaped area among the circuit elements formed in the spread area 12, and a plurality of buffer circuits are formed corresponding to each buffer circuit. As shown in FIG. 1, input/output electrodes 13 are formed in a cross shape.

Then, the chip 11 on which the cross-shaped input/output electrodes 13 are formed is inserted into four LSIs 1 as shown in FIG.
By connecting a part of the electrode 15 of each LSI 14 to the electrode 13 of the mounted chip 11, it becomes possible to easily obtain a multi-chip module having a desired function. .

Therefore, circuit elements for internal circuits and buffer circuits are formed on almost the entire surface of the chip 11, and predetermined circuit elements are wired to form a buffer circuit according to the position and number of electrodes. By forming a circuit,
The required number of electrodes 13 can be formed at desired positions on the chip 11, and there is no need to use a large chip due to an insufficient number of input/output terminals as in the past, leaving a large amount of unused area on the chip. This eliminates inconveniences such as being unable to expand the range of application due to limitations in electrode position.

As another example, as shown in FIG. 3, among the circuit elements formed in the spread area 12 on almost the entire surface of the chip 11, the central circuit elements are wired to form an internal circuit, Circuit elements are wired to surround this internal circuit to form a double buffer circuit area, and one electrode for input/output corresponds to each buffer circuit in both buffer circuit areas.
6 may be formed, and the electrodes 16 may be arranged in double layers on the chip 11.

[0015] It goes without saying that the positions and number of electrodes are not limited to those in the above embodiments.

[0016]

As described above, according to the master slice LSI of the present invention, circuit elements are formed on almost the entire surface of the chip without distinction between internal circuits and buffer circuits, and buffer circuits are arranged according to the position and number of electrodes. Since a buffer circuit is formed by wiring predetermined circuit elements to form a circuit, it is possible to form the necessary number of input/output electrodes at desired positions on the chip, reducing the number of input/output terminals compared to conventional methods. There is no need to use a large chip size due to a lack of carbon, and it is possible to eliminate inconveniences such as an increase in the unused area of the chip and the inability to expand the range of applications due to restrictions on electrode positions.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of a master slice LSI of the present invention.

FIG. 2 is a perspective view of the application example of FIG. 1;

FIG. 3 is a plan view of another embodiment of the invention.

FIG. 4 is a plan view of a conventional master slice LSI.

[Explanation of symbols]

11 Chip 13, 16 electrode

Claims (1)

[Claims] 1. Circuit elements such as transistors and resistors are formed on almost the entire surface of the chip, and the circuit elements are wired to form a buffer circuit according to the position and number of electrodes, and an internal circuit is formed. Wiring the circuit elements as possible,
A master slice LS characterized in that an internal circuit and a plurality of buffer circuits are formed on the chip, and input/output electrodes are formed corresponding to each of the buffer circuits.
I.