JPH03152956A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve an integrated circuit device in characteristics by a method wherein interface cells corresponding to the first and the second row of bonding pads from the side of an integrated circuit chip are different from each other in constitution for each row of bonding pad. CONSTITUTION:Bonding pads P1-P3 are arranged in a line in a direction parallel with the side of an integrated circuit chip 1. Bonding pads P4-P6 are arranged in a line in a direction parallel with the side of the integrated circuit chip 1 inside the bonding pads P1-P3. The bonding pads P1-P3 and P4-P6 are so arranged that the centers of the bonding pads and the side of the integrated circuit chip do not overlap with each other in a vertical direction. Output buffer circuit transistor and resistor regions T4-T9 and output buffer circuit transistor and resistor regions T1-T3 of the same type with the regions T4-T9 are provided between the bonding pads P1-P3 and interface cells C1-C3 to be added to the interface cells C1-C3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a master slice type semiconductor integrated circuit device having multiple rows of bonding pads.

[Conventional technology]

Conventionally, in semiconductor integrated circuits with a large number of pins, in order to increase the number of bonding pads that can be formed on an integrated circuit chip, bonding pads are placed in multiple rows parallel to the sides of the integrated circuit chip, and overlapping in the vertical direction with the sides of the integrated circuit chip. Some were arranged in such a way that they did not match.

FIG. 2 is a plan view of an example of a conventional semiconductor integrated circuit.

Bonding pads P1 to P3 and bonding pad P
4 to P6 are lined up in two rows. Bonding pad P1
-P3 are arranged in a row on the side 1 side of the integrated circuit chip, and bonding pads P4-P6 are arranged in a row on the inside of the integrated circuit chip. Pairs of interface cells C1 to C6 correspond to bonding pads P1 to P6, respectively.

The interface cells C1 to C6 all had the same structure and shape. Furthermore, the interface cells 01 to C6 are arranged in a line in a direction parallel to side 1- of the integrated circuit chip, keeping a constant distance from side 1 of the integrated circuit chip, regardless of the rows of bonding pads P1 to P6. Ta. Usually, the distance between the bonding pads P4 to P6 and the interface cells 04 to C6 is the minimum necessary distance that does not affect the interface cells during bonding. At this time, the bonding pad array area between the bonding pads P1 to P3 and the corresponding interface cells 01 to C3 is not used at all,
It was wasted.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, the interface cells are arranged in a line at a constant distance from the side of the integrated circuit chip, further inside the bonding pads in the second row from the first side of the integrated circuit chip. Since a wasted area is created between the bonding pad in the first row from the side of the integrated circuit chip and the interface cell, there is a drawback that the integration density of the semiconductor integrated circuit is reduced.

[Means for Solving the Problems] The semiconductor integrated circuit of the present invention has at least one row of bonding pads parallel to one side of the integrated circuit chip, and the centers of the bonding pads overlap in a direction perpendicular to the side of the integrated circuit chip. In a master slice type semiconductor integrated circuit in which the semiconductor integrated circuits are arranged in a master slice manner, the structure of the first type of interface cells corresponding one-to-one to the bonding pads in the first row from the side of the integrated circuit chip is arranged in the second row from the side of the integrated circuit chip. It has a feature that it is different from the structure of the second type of interface cell, which corresponds one-to-one to the bonding ink pad of the eye.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of one embodiment of the present invention.

Bonding pads P1 to P3 of the semiconductor integrated circuit are arranged in a line in a direction parallel to the sides of the integrated circuit chip.

The bonding pads P4 to P6 are arranged inside the integrated circuit chip from the bonding pads P1 to P3 in a direction parallel to the sides of the integrated circuit chip. Bonding pad P1
~P3 and P4 to P6 are arranged so that the sides of the integrated circuit chip and the center of the bonding pad do not overlap in the perpendicular direction.

Bonding pad P in the first row from the side of the integrated circuit chip
1 to P3 and the corresponding interface cell C1 to
The area between C3 is approximately comparable to the area occupied by the transistor and resistor for the output circuit of the interface cell.

Therefore, between the bonding pads P1 to P3 and the interface cells 01 to C3, the same transistors and resistance regions T1 to T3 for the output buffer circuit as the transistors and resistance regions T4 to T for the output buffer circuit are installed, This is added to the ink face cells C] to C3.

As a result, the output buffer circuits of the interface cells C1 to C3 have twice as many output buffer circuit transistors and resistances as the output buffer circuits of the interface cells C4 to C6. The driving ability of cells 01 to C3 can be improved approximately twice as much as that of normal input/output buffer circuit cells C4 to C6.

In this way, it is possible to improve the characteristics of the integrated circuit device by utilizing the area that was previously wasted.

〔Effect of the invention〕

As explained above, the present invention has the following features: (a) The structure of the interface cells corresponding to the bonding pads in the first and second rows from the side of the integrated circuit chip is different for each row of bonding pads. (b) Associating the output buffer with the bonding pad in the first row from the side of the integrated circuit chip, and associating the input buffer with the bonding pad in the second row, thereby creating a connection between the bonding pad and the input/output buffer circuit cell. This has the effect of eliminating wasted area, making effective use of the chip area of the semiconductor integrated circuit device, and improving the integration density.

[Brief explanation of the drawing]

FIG. 1 is a plan view of one embodiment of the present invention, and FIG. 2 is a plan view of an example of a conventional integrated circuit chip. 1...Sides of integrated circuit chip, C1-C6... Ink face cells, P1-P6... Honding pads, T1-T9... Transistors and resistance regions for output buffer circuits.

Claims (1)

[Claims] In a master slice type semiconductor integrated circuit in which bonding pads are arranged in at least two rows parallel to one side of an integrated circuit chip and in a direction perpendicular to the side of the integrated circuit chip without overlapping the centers of the bonding pads, the integrated circuit The configuration of the first type of interface cells corresponds one-to-one to the bonding pads in the first row from the side of the chip, and the configuration of the second type interface cells corresponds one-to-one to the bonding pads in the second row from the side of the integrated circuit chip. A semiconductor integrated circuit characterized by having a structure different from that of an interface cell.