JPH04186749A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a region for performing signal wiring of an internal logic circuit and a peripheral circuit to be reduced, an area utilization efficiency to be increased, and an area of a semiconductor chip to be reduced by performing wiring of placement of the logic circuit and a peripheral cell automatically by an electronic computer using a power supply wiring cell. CONSTITUTION:In a semiconductor integrated circuit device for performing wiring of placement of a peripheral circuit and an internal logic circuit automatically by an electronic computer, where a chip size is determined by the size of the peripheral circuit, wiring of power supplies VDD and VSS passing through the peripheral circuit part are connected to the power supplies VDD and VSS respectively of adjacent horizontal cell rows halfway from a vertical peripheral cell rows. In a semiconductor chip 1, a power supply wiring cell 10 is treated similarly as a peripheral cell 3 and automatic placement wiring is performed by an electronic computer and signal wiring of input and output is performed between a logic circuit 2 and a peripheral circuit part 8 with a less area than a conventional wiring region 4. Use of four power supply wiring cells 10 allows the power supply VDD wire 5 and the power supply VSS wire where a second-layer alumina wire 9 passes through the peripheral circuit 8 to be connected to each of the power supply VDD wire 5 and the power supply VSS wire 6 of adjacent horizontal peripheral cell row halfway from a vertical peripheral cell row, thus enabling an area of a wiring region 4 to be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device in which peripheral circuits and logic circuits inside a semiconductor chip are automatically placed and routed by a computer, and in particular, This is the case when the size of the semiconductor chip is determined by this.

[Prior Art] FIG. 4 is a plan view of a conventional semiconductor integrated circuit device in which peripheral cells and logic circuits are automatically arranged and wired by a computer. In the figure, a semiconductor chip 1 includes a logic circuit 2 and peripheral cells 3 that are composed of a plurality of functional blocks. The peripheral circuit section 8 includes a plurality of peripheral cells 3 and a power VOO wiring 5 and a power VSS wiring 6 generated by automatic placement and wiring using a computer, and input/output signals generated between the logic circuit 2 and the peripheral circuit section 8. are wired within the wiring region 4.

FIG. 5 shows an example of the configuration of the peripheral cell 3 shown in FIG. 4.

Pad 7 used for input/output with the outside of the chip, power supply VOO
It is composed of a wiring 5, a power supply VSS wiring 6, and an input/output circuit area 11 having a signal input/output function for the logic circuit 2.

[Problems to be Solved by the Invention] Conventional semiconductor integrated circuit devices were configured as described above, so when the number of input/output terminals is large, it is determined by the size of the semiconductor chip or the size of the peripheral circuits, and the wiring There was a problem that the area utilization efficiency of the area deteriorated.

This invention was made to solve the above-mentioned problems, and the power supply VDD and V
By connecting SS from the middle of a vertical (horizontal) peripheral cell row to the power supplies VDD and v33 of the adjacent horizontal (vertical) peripheral cell row, signal wiring for internal logic circuits and peripheral circuits is performed better than before. The object of the present invention is to obtain a semiconductor integrated circuit device that reduces the area, increases area utilization efficiency, and reduces the area of a semiconductor chip.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device formed on the same chip, which includes a pad and has a logic circuit composed of a plurality of functional blocks. Peripheral cells with the function of inputting or outputting signals, power supply VO
The power supplies VOO and V in the above peripheral cells are equipped with O and VSS wiring.
A power supply wiring cell for connecting to the SS wiring, the arrangement and wiring of the logic circuit and the peripheral cells are automatically performed by a computer using the power supply wiring cell.

[Function] The semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device in which the chip size is determined by the size of the peripheral circuit, and the layout and wiring of the peripheral circuit and internal logic circuit is automatically performed by a computer. Power supply vDD and V
Since the SS wiring can be connected from the middle of a vertical (horizontal) peripheral cell column to the power supplies vDD and VSS of the adjacent horizontal (vertical) peripheral cell column, the wiring area is reduced compared to conventional semiconductor integrated circuit devices. However, the area of the semiconductor chip can be reduced.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing the overall configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. $, numbers 2 and 5 in the figure
, 6.8 are the same as the conventional one.

In the semiconductor chip 1, the power wiring cells 10 are treated as the same as the peripheral cells 3, and automatic placement and wiring is performed using a computer.

FIG. 2 is a plan view showing an embodiment of the peripheral cell 3 shown in FIG. 1
It is composed of a power supply VOO wiring 5 and a power supply V8S wiring 6 using layered aluminum, and an input/output circuit area 11 having a signal input/output function for the logic circuit 2.

FIG. 3 is a plan view showing an embodiment of the power supply wiring cell lO of FIG. 1, in which the power supply V uses the first layer aluminum wiring 9 and has contacts 12 on which second layer aluminum is placed. D wiring 5 and power supply V
li! ! It is composed of wiring 6.

In FIG. 1, the connections between the power supply wiring cell 10 and the peripheral cell 3, and the power supply vDI) wiring 5 and the power supply VSS wiring 6 between the peripheral cells 3 are performed using the second layer aluminum wiring 9 using the contacts 12. ing.

The semiconductor chip 1 that has been automatically placed and routed by a computer using the power supply wiring cell 10 described above can perform input/output signal wiring between the logic circuit 2 and the peripheral circuit section 8 in a smaller area than the conventional wiring area 4. This is how it was done.

In addition, in this embodiment, four power supply wiring cells 10 are used,
The power VOO wiring 5 and the power VSS wiring 6 passing through the second layer aluminum wiring 9 or the peripheral circuit section 8 are connected to the power V of the adjacent horizontal (vertical) peripheral cell row from the middle of the vertical (horizontal) peripheral cell row. . Wiring 5
and the power supply VSS wiring 6, respectively, and the wiring area 4
Efforts are being made to reduce the area of the

[Effects of the Invention] As described above, according to the present invention, in a semiconductor integrated circuit device in which the chip size is determined by the size of the peripheral circuit and the placement and wiring of the peripheral circuit and internal logic circuit is automatically performed by a computer, the wiring area is As a result, the area used as a chip can be reduced, which reduces the semiconductor chip area and improves the yield of semiconductor integrated circuit devices.
This has the effect of reducing costs.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing the overall configuration of a semiconductor integrated circuit device which is an embodiment of the present invention, and FIG. 2 is a plan view showing the peripheral cells (
3) is a plan view showing the configuration of the power supply wiring cell lO of FIG. 1, FIG. 4 is a plan view showing the overall configuration of a conventional semiconductor integrated circuit device, and FIG. 5 is a plan view showing the configuration of a peripheral cell (3) of the semiconductor integrated circuit device of FIG. 4. FIG. In the figure, 3 is a peripheral cell, 9 is a second layer aluminum wiring, 1
0 indicates a power supply wiring cell, and 12 indicates a contact. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A semiconductor integrated circuit device formed on the same chip, including a peripheral cell that includes a pad and has a function of inputting or outputting a signal to a logic circuit composed of a plurality of functional blocks. , a power supply wiring cell having a first power supply and a second power supply and for connecting to the first power supply and the second power supply in the peripheral cell, the arrangement and wiring of the logic circuit and the peripheral cell; A semiconductor integrated circuit device characterized in that it is automatically performed by a computer using cells.