JPS59145542A - Large-scale integrated circuit - Google Patents

Large-scale integrated circuit

Info

Publication number
JPS59145542A
JPS59145542A JP58020036A JP2003683A JPS59145542A JP S59145542 A JPS59145542 A JP S59145542A JP 58020036 A JP58020036 A JP 58020036A JP 2003683 A JP2003683 A JP 2003683A JP S59145542 A JPS59145542 A JP S59145542A
Authority
JP
Japan
Prior art keywords
input
output
circuit
section
electrode pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58020036A
Other languages
Japanese (ja)
Inventor
Setsuya Kengaku
見学　節哉
Moriyuki Chimura
盛幸 千村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp, Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electronics Corp
Priority to JP58020036A priority Critical patent/JPS59145542A/en
Publication of JPS59145542A publication Critical patent/JPS59145542A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11898—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To enable to freely select connection wirings according to the number of pins and arrangement of a package by a method wherein the input-output circuit part of unit form, an input-output electrode pad part and a wiring part for connection are arranged regularly in large numbers on the circumference of an LSI chip. CONSTITUTION:A number of input-output electrode pad parts 2 are arranged at the outermost part of the LSI chip, and then a region 3 for connecting wiring is provided inside said electrode pad parts 2, and it is used as a wiring part for connection. A number of input-output circuit parts 1 are arranged inside the wiring part 3 for connection. The input-output circuit part 1 is to be designed in such a manner that the circuit is composed of an input circuit and an output circuit or an input-output combination circuit so that it can be coped with the desired internal circuit of the LSI. The input-output circuit part 1 and the input- output electrode pad part 2 are connected by a universal wiring group part 3 for connection.

Description

【発明の詳細な説明】 産業上の利用分！Ｉ！］’　　　　　　　　　　　　。[Detailed description of the invention] Industrial use! I! ]’　　　　　　　　.

１４本発明は大規模集積回路（以下、ＬＳ、Ｉと軸体す
る）、とりわけ、マスク・スライス方式ＬＳＩの入出力
端子部構造に関するものである。14 The present invention relates to large-scale integrated circuits (hereinafter referred to as LS and I), particularly to the input/output terminal structure of a mask slice type LSI.

従来例の構成とその問題点 ＬＳＩ装置では、半導体チップ上に、トランジスタ等か
らなるユニット・セルを１行ｍ列のアレイ状に配置した
り、あるいはＰＬＡ（プロクラマプルロジノクアレイ）
構成の回路を配置したうえで、パッケージの型式、種類
、とくに、そのリードビンの数やコム形状等に対応させ
て、半導体チップ上の入出力端子部構造が決められてい
た。しだがりて、従来のＬＳＩにおけるチップ上の端子
部は、パッケージのリートビン及び配置に対応させて、
入力用、出力用あるいは入出力共用のいずれかに選択さ
れて設けられ、構造的にも、第１図の要部平面図で示さ
れるように、たとえは、入出力共用回路部１、入出力電
極パッド部２および接続用配線部３で構成されていた。Conventional configurations and their problems In LSI devices, unit cells consisting of transistors, etc. are arranged in a 1 row x m array on a semiconductor chip, or a PLA (programmatic array) is arranged.
After arranging the circuits in the semiconductor chip, the structure of the input/output terminals on the semiconductor chip was determined in accordance with the type and type of package, especially the number of lead bins and the shape of the comb. Therefore, the terminals on the chip in conventional LSIs are
It is selectively provided for input, output, or input/output use, and structurally, as shown in the plan view of the main part in FIG. It consisted of an electrode pad section 2 and a connection wiring section 3.

シカし、マスク・スライス方式ＬＳＩでは、同じ半導体
チップをリードビン数の異なるパッケージに組み込むこ
とも必要になり、寸だ、リードビン数が同じであっても
入出力リードビン配置が異なるパッケージに組み込むこ
とも可能なような配置構造が求められる。したがって、
この場合、従来のように、入出力回路部、入出力電極パ
ッド部および接続用配線部が一体的な構成の入出力端子
部構造では不都合を来す。However, in mask-slicing LSIs, it is necessary to incorporate the same semiconductor chip into packages with different numbers of lead bins, and even if the number of lead bins is the same, it is also possible to incorporate them into packages with different input/output lead bin arrangements. A layout structure like this is required. therefore,
In this case, the conventional input/output terminal structure in which the input/output circuit section, the input/output electrode pad section, and the connection wiring section are integrated is inconvenient.

発明の目的 本発明は、マスク・スライス方式ＬＳＩに適しプ（入出
力端子部構成を提供するものである。OBJECTS OF THE INVENTION The present invention provides an input/output terminal configuration suitable for a mask slice type LSI.

発明の構成 本発明は、互いに電気的に隔離されたトフンシヌタ等か
う成るユニット・セルラｎ　行ｍ　列のアレイ状に配置
した構成の回路および／もしくはＰＬＡ構成の回路を独
立あるいは一体に形成するとともに、入出力端子部を構
成する入出力回路部、入出力電極パット部および接続用
配線部の各部がそれぞわに分離され、前記入出力回路部
と前記入出力電極バンド部との接続を選択可能に構成さ
れた大規模集積回路であり、これにより、パッケージの
ビン数や配置に適合させた入出力端子部を構成すること
が可能である。Structure of the Invention The present invention independently or integrally forms circuits having a configuration arranged in an array of n rows and m columns and/or circuits having a PLA configuration, which are electrically isolated from each other, and which are electrically isolated from each other. The input/output circuit section, input/output electrode pad section, and connection wiring section that make up the input/output terminal section are separated, and the connection between the input/output circuit section and the input/output electrode band section can be selected. This is a large-scale integrated circuit configured in a manner that allows the input/output terminal section to be configured to suit the number and arrangement of package bins.

実施例の説明 第２図は本発明実施例の平面図で、構成上の主要部のみ
を示したものである。すなわち、本実施例は、半導体チ
ップの周辺域に設けられる入出力端子部を、入出力回路
部１、入出力電極パット部２および接続用配線部３のそ
れぞれに分離形成したものである。しかして、各部は独
立のセルで構成し、必要に応じて、各部を選択的に組合
わせて配線接続を行なう。さらに詳しくビえは、ＬＳＩ
チップの最外部に入出力電極パッド部２を多数並へて配
置し、次に、その内側に、接続用配線の領域３を設け、
ここを接続用配線部とする。そして、入出力回路部１は
上記接続用配線部３の内側に多数並べて配置する。この
場合、入出力回路部１ば、入力用回路、出力用回路ある
いは入出力兼用回路のいずれかの回路構成となして、Ｌ
ＳＩの所望の内部回路に対応できるように設泪される。DESCRIPTION OF THE EMBODIMENTS FIG. 2 is a plan view of an embodiment of the present invention, showing only the main parts of the structure. That is, in this embodiment, the input/output terminal sections provided in the peripheral area of the semiconductor chip are formed separately into the input/output circuit section 1, the input/output electrode pad section 2, and the connection wiring section 3. Each part is constituted by an independent cell, and each part is selectively combined and wired as necessary. For more details, see LSI
A large number of input/output electrode pads 2 are arranged side by side on the outermost part of the chip, and then a connection wiring area 3 is provided inside thereof.
This is the connection wiring section. A large number of input/output circuit sections 1 are arranged side by side inside the connection wiring section 3. In this case, the input/output circuit section 1 has a circuit configuration of an input circuit, an output circuit, or an input/output circuit.
It is designed to correspond to the desired internal circuit of the SI.

第３図は、前述の第２図の円囲部拡大図であり、入出力
回路部１と入出力電極パッド部２とが自在な接続用配線
群部３によって接続されていることを示している。なお
、入出力回路部１、入出力電極パッド部２および接続用
配線部３のそれぞれをセル構成になすことによって、設
計、組合せの便宜がはかれる。FIG. 3 is an enlarged view of the circled part in FIG. There is. Note that design and combination can be facilitated by forming each of the input/output circuit section 1, the input/output electrode pad section 2, and the connection wiring section 3 into a cell configuration.

捷／ζ、入出力回路部１のセルは、使用する入出力用パ
ッドに合わせて、その近くのものを選択することもでき
るし、あるいは前記ｎ行目列のアレイ状にセルを配置し
た構成の回路およびＰＬＡ構成の回路で作られた内部回
路に近いところのものを選択することも可能である。さ
らに、入出力電極パッド部２は、チップレイアウト上か
らみて、可能な限り密に配置しておくことにより、応用
が広げられる。The cells of the input/output circuit section 1 can be selected from those close to the input/output pads used, or the cells can be arranged in an array in the nth row and column. It is also possible to select a circuit that is close to the internal circuit made of the circuit and the circuit of PLA configuration. Furthermore, applications can be expanded by arranging the input/output electrode pad portions 2 as densely as possible in view of the chip layout.

発明の効果 本発明によれば、単位形状の入出力回路部、入出力電極
パッド部ならびに接続用配線部をＩ、ＳＩチップ周辺に
規則的に多数並べて配置したので、パッケージのビン数
、配列に応じて、その接続配線を自在に選択することが
でき、マスク・スライス方式ＬＳＩの設計、ならびに組
立ての自由度が格段に向」ニする。すなわち、本発明に
よれば、／＜ノケージのビン数や形状に応じて、入出力
端子部のセルの配置を変えたり、あるいは、入出力／く
ラドの配置を移動させるなどの設計変更が不必要になり
、種々のパッケージに対して、それぞれ、最適の入出力
端子部を形成することが可能になり、実用性大である。Effects of the Invention According to the present invention, a large number of unit-shaped input/output circuit sections, input/output electrode pad sections, and connection wiring sections are arranged regularly around the I and SI chips. Accordingly, the connection wiring can be freely selected, and the degree of freedom in designing and assembling a mask-sliced LSI is greatly improved. In other words, according to the present invention, there is no need for design changes such as changing the arrangement of cells in the input/output terminal section or moving the arrangement of the input/output/cladding according to the number and shape of the bins of the /< cage. This makes it possible to form optimal input/output terminal portions for various packages, which is highly practical.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来例のＬＳＩの入出力端子部平面図、第２図
は本発明実施例のＬＳＩ入出力端子部平面図、第３図は
その要部拡大平面図であるＱｌ・・・・入出力回路部、
２・・・・入出力電極パッド部、３・・・・・接続用配
線部。Fig. 1 is a plan view of the input/output terminal section of a conventional LSI, Fig. 2 is a plan view of the input/output terminal section of an LSI according to an embodiment of the present invention, and Fig. 3 is an enlarged plan view of the main part Ql... Input/output circuit section,
2... Input/output electrode pad section, 3... Connection wiring section.

Claims (1)

【特許請求の範囲】[Claims] 互いに電気的に隔離されたトランジスタ等から成ルユニ
ソト・セルを１行ｍ列のアレイ状に配置した構成の回路
および／もしくはＰＬＡ構成の回路を独立あるいは一体
に形成するとともに、入出力端子部を構成する入出力回
路部、入出力電極パッド部および接続用配線部の各部が
それぞれに分離され、前記入出力回路部と前記入出力電
極パッド部との接続を選択可能に構成された大規模集積
回路。A circuit configured by arranging uniform cells made of transistors etc. electrically isolated from each other in a 1 row x m column array and/or a PLA configured circuit is formed independently or integrally, and an input/output terminal section is configured. A large-scale integrated circuit comprising an input/output circuit section, an input/output electrode pad section, and a connection wiring section, each of which is separated, and the connection between the input/output circuit section and the input/output electrode pad section can be selected. .
JP58020036A 1983-02-09 1983-02-09 Large-scale integrated circuit Pending JPS59145542A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58020036A JPS59145542A (en) 1983-02-09 1983-02-09 Large-scale integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58020036A JPS59145542A (en) 1983-02-09 1983-02-09 Large-scale integrated circuit

Publications (1)

Publication Number Publication Date
JPS59145542A true JPS59145542A (en) 1984-08-21

Family

ID=12015834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58020036A Pending JPS59145542A (en) 1983-02-09 1983-02-09 Large-scale integrated circuit

Country Status (1)

Country Link
JP (1) JPS59145542A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112042A (en) * 1984-06-27 1986-01-20 Toshiba Corp Master slice type semiconductor device
JPS6127655A (en) * 1984-07-18 1986-02-07 Kazuyoshi Sone Manufacture of integrated circuit
US5889334A (en) * 1996-06-26 1999-03-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit and fabrication method therefor

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378185A (en) * 1976-12-22 1978-07-11 Fujitsu Ltd Integrated circuit logical element

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5378185A (en) * 1976-12-22 1978-07-11 Fujitsu Ltd Integrated circuit logical element

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6112042A (en) * 1984-06-27 1986-01-20 Toshiba Corp Master slice type semiconductor device
JPS6127655A (en) * 1984-07-18 1986-02-07 Kazuyoshi Sone Manufacture of integrated circuit
US5889334A (en) * 1996-06-26 1999-03-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit and fabrication method therefor
US6127207A (en) * 1996-06-26 2000-10-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit and fabrication method therefor

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