JPH0927603A - Master sliced gate array - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable diversified requirements for a power supply to be met by a method wherein the power supply lines supplying the power to basic cells are divided into individual cells in the case of forming patterns so as to connect these divided power supply lines to specific power supply lines. SOLUTION: Within the power supply lines 1a, 2a, 2c and the grounding lines 1b, 2b, 2d corresponding to respective lines 1a, 2a, 2c, the divided power supply lines 1a, 2a and the grounding lines 1b, 2b of one line are divided at the time of forming wiring patterns so as to form the divided grounding lines while the power supply lines and the grounding lines of the other lines are formed as one power supply line and grounding line in time of the wiring patterns. On the other hand, respective power supply lines 1a, 2a, 2c and the divided grounding lines 1b, 2b, 2d are formed as the first wiring layers to be connected to either one of the power supply 3a or 4a as the second wiring and either one of the corresponding grounding lines 3b or 4b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type gate array, and more particularly to a master slice type gate array capable of supplying a plurality of types of power sources having different potentials on one substrate.

[0002]

2. Description of the Related Art A conventional technique will be described with reference to FIG. FIG. 1 shows an example of a master slice type gate array proposed in Japanese Patent Application Laid-Open No. 5-102441 which enables supply of a plurality of types of power sources having mutually different potentials. Reference numeral 13a denotes a pad region, in which a number of signal pads connected to an interface buffer for interfacing with the outside and a number of power supply pads for supplying power to the gate array are formed. The contact holes 18 from the power supply and ground pads are respectively provided.
a, 18b, 18c and 18d, the main power supply lines 17a and 17c and the main ground lines 17b and 17d
It extends toward the internal gate region 16a. Each main power supply line 17a, 17c and main ground line 17b, 17d
Are both formed as a first aluminum wiring layer, and the first main power supply line 17a and the second main power supply line 17c are set to different first and second potentials, respectively.

In the internal gate region 16a, basic cells 20 are arranged in a matrix, and a power supply line 1 composed of a second wiring layer for supplying power to each basic cell 20 is provided.
4a, 15a and corresponding ground lines 14b, 15b
Are arranged in parallel with each other along the column of each basic cell 20. The power supply line 14a15a and the ground lines 14b, 15b of the second layer
e, 18f, 18g, and 18h are connected to the first-layer main power supply lines 17a and 17c and the main ground lines 17b and 17d. With this configuration, a suitable power supply voltage is supplied to each basic cell in the internal gate region and the buffer circuits arranged in the surrounding region.

[0004]

The types of the master slice type gate array have been diversified, and the power supply voltage supplied to each basic cell has also been diversified. For example,
Attempts have also been made to reduce power consumption of the entire semiconductor device by supplying low-voltage power to some circuits. Here, in the proposed master slice type gate array, there is a problem that a certain restriction is imposed on the power supplied to each basic cell depending on the extending direction of each power supply line and the corresponding ground line.

In view of the above, an object of the present invention is to provide a master slice type gate array which can improve the power supply line of the master slice type gate array and can respond to diversified demands of power supply.

[0006]

In order to achieve the above object, the present invention provides a master slice type gate array having an internal gate region in which a plurality of basic cells are arranged in a matrix. A plurality of power supply lines arranged in parallel along the first wiring layer, and at least one of the power supply lines is divided into two or more in the extension direction according to the arrangement of the basic cells, and the divided power supply lines And each of the divided power supply lines is connected to one of at least two power supply lines formed in the second wiring layer.

Here, the power supply line according to the present invention,
The material of the power supply line, the main power supply line and the like is not particularly limited, and any material conventionally used for this kind of purpose can be used.

The first wiring layer and the second wiring layer do not represent the meaning of the wiring first layer and the wiring second layer, respectively, in the order in which they are formed at the time of manufacturing, and only one wiring layer is used. 3 illustrates a wiring layer and another wiring layer. Therefore, either the first wiring layer or the second wiring layer may be an upper layer or a lower layer.

[0009] The basic cell in the present invention is preferably
The back gate diffusion region is electrically isolated for each basic cell or basic cell group.

[0010]

In a preferred embodiment of the master slice type gate array of the present invention, a plurality of main power supply lines and a main ground line which can be provided between the internal cell region and the input / output circuit and which can supply mutually different potentials are provided. For example, it is provided as a first wiring layer, and these are configured as a circulating power supply wiring and a circulating ground wiring around the periphery of the chip. One of a power supply line and a corresponding ground line, which are configured as a second wiring layer and extend in, for example, the column direction of the basic cells, are arranged, for example, every two columns of the basic cells. A power supply line for directly supplying power to each basic cell and a corresponding ground line are formed as a first wiring layer, and extend in the row direction orthogonal to the power lines extending in the column direction. , One power supply line and a corresponding ground line are provided for each row of the basic cells.

At least one of the power supply lines extending in the row direction and the corresponding ground line is divided in the row direction for each of an arbitrary number of basic cells in accordance with a function required for the gate array. Construct a supply line and a split ground line. Each of the divided power supply line and the divided ground line, and the undivided power supply line and the ground line are respectively connected to the power supply line of the wiring second layer and the corresponding ground line via the corresponding contact hole. . The back gate diffusion regions of the basic cells arranged in the internal cell region are electrically separated from each other in advance for each basic cell or for each basic cell group, and can be divided into arbitrary divisions of a power supply line and a corresponding ground line. Yes, it is.

Here, instead of the above configuration in which a plurality of ground lines are provided corresponding to each power supply line, a common ground line can be provided for each power supply line.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The master slice type gate array of the present invention will be described in more detail with reference to FIGS. 1 and 2 showing an embodiment of the present invention. FIG. 2 is a plan view schematically showing an arrangement of the master slice type gate array on a chip. FIG. 1 is a plan view showing a part of FIG. 2, and shows the connection of power supply lines and the arrangement of internal gate regions. It is a top view which illustrates an example.

In FIG. 2, the semiconductor chip 10a includes:
A pad region 11a forming a peripheral region is arranged on the outer peripheral portion of the chip, and an internal gate region 5c is arranged inside the pad region 11a.
Between the pad region 11a and the internal gate region 5c, two types of main power supply lines 3c, 4c forming a first wiring layer and main ground lines 3d, 4d corresponding to the two types are formed as peripheral wirings. They are sequentially arranged as a circulating power supply wiring and a circulating ground wiring. Between one of the circulating power lines 3c and the corresponding circulating ground line 3d, for example,
A voltage of 5V is applied, and the other circulating power supply line 4c,
A voltage of, for example, 3.3 V is applied between the corresponding peripheral ground line 4d.

In FIG. 1, each power supply line 3c, 4
c and the corresponding peripheral ground lines 3d and 4d, and the power supply lines 3a and 4a and the corresponding ground lines 3b and 4b, which form the second wiring layer disposed in the internal gate region, are formed as aluminum wiring layers. I have. Each power supply line 3a, 4a and each ground line 3b, 4b in the internal gate region
One power supply line or ground line is alternately arranged for every two rows of basic cells 20. The power supply lines 3a, 4a and the corresponding ground lines 3b, 4b are respectively connected to the upper peripheral power supply lines 3c, 4c and the peripheral ground lines 3d, 4d via the corresponding contact holes 19a, 19c, 19b, 19d. It is connected.

For each row of the basic cells 20 in the internal gate region, one power supply line and a corresponding ground line extend in the row direction in pairs with each other. In the illustrated example, the power supply lines 1a, 2a, 2c and the corresponding ground lines 1b, 2b, 2d are divided power supply lines 1a, 2a and the ground lines 1b, 2b of one row.
Are divided at the time of forming the wiring pattern to form a divided power supply line and a divided ground line, and the power supply line and the ground line of another row are formed as one power supply line and the ground line at the time of forming the wiring pattern. You.

Each of the power supply lines 1a, 2a, and 2c and the divided ground lines 1b, 2b, and 2d are formed as a first layer of aluminum wiring, and each of the power supply lines 3a or 4a forming the second layer of wiring is formed. And a corresponding ground line 3b,
4b and contact holes 6a, 7a, 6 respectively.
b, 7b.

In the illustrated example, the basic cell is composed of one basic cell group 5a and the other basic cell group 5b, and each basic cell 20 of one basic cell group 5a
The divided power supply line 1a and the corresponding divided ground line 1b are connected via a and 8b, and the
Power line 3a and a corresponding ground line 3b. Also, each basic cell 20 of the other basic cell group 5b
Are divided power supply lines and corresponding divided ground lines 2a, 2b, 2c through contact holes 9a, 9b.
2d, and the second power supply line 4
a and the corresponding ground line 4b.

With the above configuration, for example, a power of 5 V is supplied to each of the basic cells 20 in the basic cell group 5a, and a power of, for example, 3.3 V is supplied to each of the basic cells 20 in the basic cell group 5b. You. The back gate diffusion regions of the basic cell pairs 5a and 5b composed of two basic cells 20 are electrically separated from the back gate diffusion regions of the adjacent basic cell pairs. Thereby, even if an arbitrary power supply connection having a different potential for each basic cell pair is performed, consideration is given in advance so that power supply does not touch between adjacent basic cell pairs. The unit of the electrical separation can be set to one or more arbitrary numbers in consideration of the pattern of the power supply supplied to each basic cell.

Each division position of the divided power supply line corresponds to a boundary position of a basic cell pair. The actual position of division is determined when designing the wiring pattern according to the application of the master slice type gate array. Therefore,
For example, even if the basic cells operating at 5V and the basic cells operating at 3.3V are arranged in any pattern, a gate array corresponding to this can be formed by patterning.

The present invention can be applied to a master slice type gate array receiving clock signals from two clock lines having different frequencies. For example, low-voltage power is supplied to a basic clock group controlled by one clock line having a high frequency, and high-voltage power is supplied to a basic clock group controlled by the other clock line having a low frequency. As a result, power consumption in a basic clock group controlled at a high frequency is reduced. in this case,
Regardless of how the power supply type is divided in a complicated manner, which power supply is supplied to the basic cell at a certain position can be determined by selecting a power supply line dividing position and designing the divided power supply when designing the wiring pattern. It is easily determined by the selection of the power supply line connecting the lines.

FIG. 3 is a partial plan view showing a configuration of a master slice type gate array according to a second embodiment of the present invention.
In FIG. 3, portions other than the internal gate region are not shown, but the omitted portion is the same as the configuration in FIG. The configuration of the semiconductor chip is the same as that shown in FIG.

In the master slice type gate array of this embodiment, as in the previous embodiment, a plurality of power supply lines and a corresponding ground line forming the second layer of wiring extend along the column direction, while the first line of wiring Layered power supply lines and corresponding ground lines extend along the row direction. Each of the power supply lines and the corresponding ground line is divided into basic cell pairs for each basic cell structure, and the divided portions are corrected on a mask as necessary when designing an actual wiring pattern. .

For example, consider the case where the part 5e shown in the figure is used as one basic cell group and a power source different from that of the other basic cell group 5d is supplied thereto. In this case, the divided power supply line 1
2a is extended leftward in the figure, and extends to a lower portion of the first power supply line 3d. At the same time, the power supply line 3d of the second wiring layer and the extended divided power supply line 12a of the first wiring layer are connected by a contact hole connecting the first wiring layer and the second wiring layer. Similarly, the corresponding divided ground line 12g is extended rightward in the figure and connected to the ground line 3e.

A common power supply is supplied to the other basic cell groups 5d. In this case, the basic cell group 5d to which a common power is supplied by patterning using a mask pattern
Divided power supply lines 12b, 12c, 12d, 12
e, 12f and corresponding ground lines 12h, 12i, 1
2j, 12k and 121 are respectively extended in the row direction and connected to the adjacent divided power supply lines and the corresponding ground lines, respectively. At the same time, the divided power supply lines and the corresponding ground lines interconnected by the contact holes connecting the first and second wiring layers are connected to the power supply line 4d.
And the ground line 4e. This connection may be made at any one position, or may be made to all corresponding power supply lines and ground lines.

The final configuration of this embodiment is the same as that shown in FIG. One power supply wiring 3d is shown in FIG.
Similarly, the power supply wiring 3c is connected, and the other power supply wiring 4d is similarly connected to the power supply wiring 4c.
In FIG. 2, the peripheral power supply lines 3c and 4c are supplied with different power supply voltages via the power supply pads in the pad region 11a. Thus, the power supply lines 3d and 4d are set to different power supply voltages. Also, the ground lines 3e and 4e are similarly connected to the surrounding ground wirings 3d and 4d, respectively.

In each of the first and second embodiments, the example in which the ground wiring is separately provided in correspondence with the first power supply line and the second power supply line has been described. It is also possible to provide a common ground line for the lines.
In that case, one of the ground wirings 3d and 4d shown in FIG. 2 can be deleted and integrated. Accordingly, the ground wiring does not need to be divided for each basic cell in accordance with the power supply type of the divided power supply line.

In the first and second embodiments, the case where two different power supply voltages are supplied has been described as an example. However, the number of circuit power supply lines and corresponding power supply lines, and the number of divided power supply lines , It is possible to supply two or more types of arbitrary power sources.

Although the present invention has been described based on the preferred embodiment, the master slice type gate array of the present invention is not limited to the configuration of the above embodiment.
Various modifications and changes from the configuration of the above embodiment are also included in the master slice type gate array of the present invention.

[0030]

The master slice type gate array of the present invention has a structure in which a power supply line for directly supplying power to the basic cells can be divided into basic cells or basic cell groups when forming a wiring pattern. Since the divided power supply lines can be connected to desired power supply lines, the degree of freedom in supplying power to each basic cell is increased, and the present invention makes it particularly easy to supply a semiconductor device with low power consumption. A remarkable effect is provided by providing a simple master slice type gate array.

[Brief description of drawings]

FIG. 1 is a plan view showing a main structure of a master slice type gate array according to a first embodiment of the present invention.

FIG. 2 is a plan view of a chip of a master slice type gate array according to first and second embodiments of the present invention.

FIG. 3 is a plan view showing a main structure of a master slice type gate array according to a second embodiment of the present invention.

FIG. 4 is a plan view of a main part of a conventional master slice type gate array.

[Explanation of symbols]

1a, 2a, 2c, 12a to 12f Divided power supply line 1b, 2b, 2d, 12g to 12l Ground line 3a, 3d, 4a, 4d, 14a, 14b Power line 3b, 3e, 4b, 4e, 15a, 15b Ground line 5a, 5b, 5d Basic cell group 6a, 6b, 7a, 7b, 8a, 8b Contact hole 9a, 9b Contact hole 3c, 4c Circular power supply wiring (main power supply wiring) 3d, 4d Circular ground wiring (main power supply wiring) 5c Inside Gate region 10a Semiconductor chip 11a Pad region 20 Basic cell

Claims (3)

[Claims] 1. A master slice type gate array having an internal gate region in which a plurality of basic cells are arranged in a matrix, wherein a plurality of power supply lines are arranged in parallel with each other along the arrangement of the basic cells. In one wiring layer, at least one power supply line is divided into two or more in the extension direction according to the arrangement of the basic cells to form a divided power supply line, and each of the divided power supply lines is A master slice type gate array, which is connected to any one of at least two power supply lines formed in two wiring layers. 2. An input / output circuit region arranged in the peripheral portion of the internal gate region, and is formed between the input / output circuit region and the internal gate region and formed corresponding to each of the power supply lines. The master slice type gate array according to claim 1, further comprising a plurality of main power supply lines, each of the main power supply lines being connected to the corresponding power supply line. 3. The master slice type gate array according to claim 1, wherein the back gate diffusion region of each basic cell is electrically isolated for each basic cell or basic cell group.