JPS6329826B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit design method, and more particularly to a master slice semiconductor integrated circuit in which only wiring portions are individually designed.

Generally, in a master slice type integrated circuit, the basic elements constituting the logic element are basic logic circuit cells (hereinafter referred to as cells), and the cells are fixedly arranged, and only wiring is required to realize any logical function. By making this variable, this method standardizes integrated circuit manufacturing prior to wiring and enables high-mix, low-volume production.

In this specification, a logic circuit cell is referred to as a cell, and a plurality of cells arranged in an array (array) is referred to as a cell array.

In general, for wiring between each cell,
It is necessary to prepare wiring in the Y direction and a contact hole for connecting both wirings.

In order to realize this wiring, bipolar type requires two layers of metal wiring and contact holes.
In the MOS type, it is common to use a diffusion layer or a polysilicon layer constituting the cell, one layer of metal wiring, and a contact hole. However, in the MOS type master slice method, a diffusion layer or a polysilicon layer is required to configure the cell, so it is impossible to individually design only the wiring, which is a feature of the master slice method. Since it is not possible to manufacture the MOS type master slice method using this method, a MOS type integrated circuit using the master slice method is not put into practical use. Of course, we use the master slicing method with two layers of metal wiring and contact holes.
Although it is possible to apply it to MOS type integrated circuits,
In this case, the drawback was that it was expensive and the features of MOS could not be taken advantage of.

This invention improves the conventional master slice type integrated circuit, which requires two-layer wiring and contact holes that can be arbitrarily routed, and provides a method that can be realized using fixed wiring, arbitrary one-layer wiring, and its contact holes. The purpose of this is to make it possible to realize master slice type MOS integrated circuits using conventional manufacturing, while also making it possible to realize bipolar type MOS integrated circuits using two layers of wiring and one layer of contact holes to realize arbitrary logic functions. The present invention provides a semiconductor integrated circuit whose cost can be reduced by using a contact hole.

In order to explain the structure and operation of the present invention, an embodiment will be explained below using a MOS type integrated circuit.

Fig. 1 is a circuit diagram using a known MOS transistor when the cell is a two-input NOR circuit in order to realize a master slice integrated circuit, where 1 is an output, 2 and 3 are input terminals, 4 is a power supply terminal, and 5 represents the ground terminal, transistors marked with a star are depletion type transistors, and transistors without a mark represent enhancement type transistors.

Figure 2 shows the overall layout of an integrated circuit in which these cells are arranged in an array. 14 is a plurality of these cells arranged, 12 and 13 are power and ground lines, and 11 is a line for taking out signals to the outside. These are the buffer circuit and pad area. The area between each cell array is a wiring area, and the master slice method is characterized in that even the parts where wiring is not performed are made common, and only the wiring is designed individually according to the logical function.

Figure 3 shows the second wiring after wiring using the conventional method.
It is a partially enlarged view of the figure, and terminals 21, 22, 23
constitutes one cell terminal, 21 is an output terminal of a 2-input NOR circuit as a logic circuit cell, 22, 2
3 represents an input terminal, 29 a depletion type transistor, and 30 an enhancement type transistor. Reference numerals 27 and 28 are power supply and ground wiring, which are common to all integrated circuits. Here, the logic circuit cells are formed in a matrix, and the following description will be made assuming that the rows of the matrix are in the horizontal direction and the columns are in the vertical direction.

In FIG. 3, in order to construct a logic circuit, it is necessary to connect each cell terminal, and the state of this wiring is shown by wirings 24, 25 and contact holes 26. In FIG. 3, 24 is a vertical wiring, 25 is a horizontal wiring, 26 is a vertical wiring,
This is a contact hole for connecting horizontal wiring.
In general, in the case of MOS type integrated circuits, the power supply and ground wiring and either the vertical or horizontal wiring are metal wiring, and the other wiring is wired using polysilicon or diffusion, but in the case of wiring using polysilicon or diffusion, As shown in FIG. 3, the wiring cannot be fixed and must be done arbitrarily, so in this method, as already mentioned, it is impossible to realize a MOS type integrated circuit using the master slice method.

The present invention eliminates these drawbacks and provides a semiconductor integrated circuit that enables a master slice method in which polysilicon or diffused wiring is fixed. An embodiment of the present invention is shown in FIG.
The cell structure in Figure 4 is the same as that in Figure 3, but the terminal positions of the upper and lower cell arrays are arranged alternately so as to be shifted by one wiring section from each other, and vertical wiring is prepared for each input/output terminal. By fixing the wiring as shown by the broken line in FIG. 4 and using polysilicon or diffusion, it is possible to realize a MOS type integrated circuit using the master slice method. In the example of FIG. 4, 34 is a fixed diffusion layer, 35 is a metal wiring, and 36 is a fixed diffusion layer.
is the contact hole. Diffusion layer 34 and metal wiring 35 are connected through contact hole 36 . Further, the connection between the cell terminal and the fixed diffusion layer 34 is made by a metal wiring 35 and a contact hole 36. In this case, since the diffusion layer 34 is provided for each terminal, it is possible to connect the terminals directly, but in order to avoid adding extra stray capacitance to unused terminals, only the necessary portions are connected through contact holes. I am taking a method. in this way,
By arranging the cells and fixed wiring shown in FIG. 4 and making this part common, any wiring can be formed using only metal wiring and contact holes, and therefore any logic can be realized. Moreover, this makes wiring design easy, and it is also possible to easily automate wiring design. In FIG. 4, the same reference numerals as in FIG. 3 indicate the same or corresponding parts.

This invention has devised a method for designing integrated circuits using the master slice method, and although this invention is particularly effective for MOS type integrated circuits, it is also possible to apply this method to bipolar type integrated circuits.

As described above, since the semiconductor integrated circuit according to the present invention can configure any logic using only one wiring layer and contact holes, it is possible to apply the master slice method to MOS type semiconductor integrated circuits and design and manufacture them. This shortens the period and makes it possible to efficiently develop and manufacture a wide variety of semiconductor integrated circuits in small quantities.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of a 2-input NOR circuit of a cell of a MOS type integrated circuit which is an embodiment of the present invention, and Fig. 2 is a circuit diagram of a 2-input NOR circuit of a cell of a MOS type integrated circuit which is an embodiment of the present invention.
Figure 3 is a diagram showing the overall layout of a chip using the MOS type master slice method. Figure 3 is a partial enlargement of Figure 2 and is a pattern layout diagram when wiring between cells is routed using the future method. Figure 4 is a diagram showing the implementation of this invention. FIG. 4 is a pattern layout diagram for explaining cell arrangement and wiring method when using fixed wiring according to an example. In the figure, 21 to 23 are cell input/output terminals, 27 is a power supply wiring, 28 is a ground wiring, 29 and 30 are transistors, 34 is a fixed diffusion layer as an alternately formed wiring, 35 is a metal layer, and 36 is a This is a contact hole. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] 1 Logic circuit cells having input/output terminals form a cell array or cell array group arranged in an array on the same semiconductor substrate, and input/output terminals and signal lines for connecting between the logic circuit cells and to external circuits. In an integrated circuit that has a wiring area provided for wiring power lines, ground lines, etc., two cell arrays are provided facing each other in parallel across the wiring area, and the logic circuit cells constituting these cell arrays are Input/output terminals are designed so that the fixed wiring that extends in a straight line from each input/output terminal to the point where it does not touch the opposing logic circuit cell does not touch the fixed wiring from the input/output terminal of each logic circuit cell. A semiconductor integrated circuit characterized in that the terminals are shifted in a direction perpendicular to the axis of the fixed wiring by half the distance between the terminals.