JPH01243541A - Semiconductor device - Google Patents

Abstract

PURPOSE:To effectively prevent a short circuit between power-supply lines by a method wherein one side of a power-supply trunk line for power-supply voltage use and a power-supply trunk line for ground voltage use of a semiconductor device whose logic block is to be arranged and wired by using a building block system is divided and formed. CONSTITUTION:Each power-supply trunk line 6 is composed of a power-supply trunk lines 6a for power-supply voltage use and a power-supply trunk line 6b for ground voltage use. The trunk lines 6a are divided into two and arranged on both sides of the trunk line 6b by sandwiching this trunk line. Out of power- supply lines 7 which connect feed point pairs 2a of logic blocks 2 arranged at the upper part and lower part of the trunk line 6 to the trunk line 6, the power-supply lines 7 connected to the trunk line 6a are connected to the trunk line 6a on this side of the blocks 2. Then, the power-supply lines 7 which are extended from the feed point pairs 2a of the blocks 2 to the trunk line 6 do not stride over one side of the trunk line 6. By this setup, it is possible to effectively prevent a short circuit between the power-supply lines 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to power supply wiring technology for semiconductor devices, and relates to a technology that is particularly effective when applied to automatic design of semi-custom LSIs.

[Conventional technology]

For information on automatic design waves and techniques for semi-custom LSIs, see, for example, "Nikkei Microdevices December issue", published by Nikkei McGraw-Hill, December 1, 1986, P90-P95.
It is described in , and includes standard cells, gate arrays, etc.
Trends in automatic design technology for semiconductor devices, which represent semi-custom LSIs, are explained.

Conventionally, the polycell method was used to create the standard cells mentioned above, but as the development period of semi-custom LSfs has become shorter and more functional, the design of the logical hierarchy,
A so-called building block method, which is suitable for mounting macro cells such as RAMSROM, is now being used.

The standard cell power supply wiring process using this building block method is generally as follows.

First, logic blocks and macrocells are formed in the circuit formation area of a semiconductor pellet (hereinafter referred to as pellet), and at this time, a power supply is placed at the periphery of each logic block or macrocell, and a pair of power supply points is placed at the end. .

Next, a power main line consisting of a power main line for Vdd (power supply voltage) and a power main line for Vss (ground voltage) is placed between the logic blocks and macro cells.

Finally, by forming a power line between the power supply main line and the above-mentioned power supply point pair, and connecting one of the power supply point pair to the Vdd power supply main line and the other to the Vss power supply main line, all form a power supply network that supplies power to the elements.

[Problem to be solved by the invention]

However, when creating a standard cell using the above building block method, depending on the relative position of the logic blocks (or macro cells) placed across the power supply main line, the power supply for connecting the power supply point pair and the power supply main line may be Wires may be shorted together.

To explain this with reference to FIG. 3, from each feed point pair 21a, 22a of a pair of logic blocks 21 and 22 sandwiching the power main line 20, a power main line 20a for VdC1 and a power main line 20 for Vss are connected.
When extending the power lines 23 and 24 from the power supply line 21a of the logic block 21 to the Vss power supply main line 20b, for example, the power supply line 23 extending from the power supply point pair 21a of the logic block 21 must cross the Vdd power supply main line 20a, and , the other logical block 2
Since the power line 24 extending from the second feed point pair 22a to the Vdd power main line 20a must cross the Vss power main line 20b, depending on the relative positions of the logic blocks 21 and 22, the power line 23 and the power line 24 may may get close to you and cause you to swerve.

In such a case, it is necessary to re-arrange the logic blocks and macrocells, but such design changes require extremely sophisticated judgment, so currently computers and
It is difficult to make design changes using automatic design technology such as AD.

Therefore, the current situation is that design changes are unavoidably carried out manually, which takes a long time, and this is a major hindrance in shortening the development period for standard cells.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technology that can achieve design automation of semiconductor devices created using the building block method.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problem] A brief overview of typical inventions disclosed in this application is as follows.

In other words, the Vd of a semiconductor device in which logic blocks and macro cells are placed and wired using the building block method.
At least one of the d power supply trunk line and the Vss power supply trunk line is formed separately.

[Effect]

According to the above-mentioned means, when the power supply lines are extended from the feed point pair of logic blocks (or macro cells) facing each other across the power supply main lines Vdd and Vss to the power supply main lines Vdd and Vss, each power supply line is connected to the power supply main lines Vdd and Vss. Since there is no straddling, it is possible to effectively prevent the power lines from crossing each other.

〔Example〕

FIG. 1 is a second diagram showing a semiconductor device which is an embodiment of the present invention.
FIG. 2 is an enlarged plan view of the main part of the figure and a schematic plan view of this semiconductor device.

The semiconductor device of this embodiment is a standard cell manufactured by a building block method, and as shown in FIG. 3
are arranged at predetermined intervals.

Inside each logic block 2, a large number of cell columns (not shown) and a power supply for supplying power to each cell are formed, and a pair of feeding points 2a is formed at the end of the power supply.

Similarly, inside each macro cell 3, there are formed a large number of cell rows consisting of memory cells such as RAM and ROM, and a power source that supplies power to each cell. is formed.

In the remaining area of the logic block 2 and the macro cell 3, two main power supply wirings 5 connected to the human output buffer circuit 4 are provided.
A large number of power supply trunk lines 6 orthogonal to this main power supply wiring 5 are arranged in a ladder shape, and the power supply point pair 2a of each logic block 2 and the power supply point pair 3a of each macro cell 3 are connected to the power supply trunk line 7 via a power supply line 7. 6.

Here, the main power supply wiring 5 is connected to the main power supply wiring 5a for Vdd and the Vdd main power supply wiring 5a.
ss main power supply wiring 5b, for example, Vdd
= 5 V, Vss = OV theal.

A large number of bonding bands 8 are formed on the peripheral edge of the pellet 1, and wires are bonded to the leads when the pellet 1 is sealed in a package.

Next, in this embodiment, each power supply trunk line 6 is composed of a Vdd power supply trunk line 6a and a VSS power supply trunk line 6b, as shown in FIG. It is divided into two parts and placed on both sides of the Vss power main line 6b.

Logic blocks 2 placed above and below the power main line 6
(or macrocell 3) feed point pair 2a (or 3a
) and the power supply main line 6, the power supply line 7 connected to the VDD power supply main line 6a is connected to the VDD power supply main line 6a on the front side of each logic block 2 (or macro cell 3). It is now possible to do so.

Note that the power supply trunk line 6 and the power supply line 7 have a hierarchical structure. For example, when the first layer Aβ wiring or the third layer A1 wiring is used as the power supply trunk line 6, the second layer Al wiring is the power supply line 7. Therefore, the power main line 6 and the power line 7 are connected through the contact hole 9.

In this way, the Vcld power supply main line 6a is divided into two, and the Vcld
When placed on both sides of the power supply main line 6b for s, unlike the conventional standard cell, the power supply line 7 extending from the power supply point pair 2a (or 3a) of the logic block 2 (or macro cell 3) to the power supply main line 6 is the power source. Since it does not cross one side of the main line 6, the logic blocks 2 facing each other across the power supply main line 6
Even if the relative positions of the macrocells 3 (or macrocells 3) are close to each other, short circuits between the power supply lines 7, 7 can be effectively prevented.

As a result, the design change process, which previously took a long time to perform manually, is no longer necessary, and standard cell design is fully automated, making it possible to significantly shorten the standard cell development period. Become.

Further, since the relative positions of the logic block 2 and the macro cell 3 can be made closer to each other, the degree of integration of the standard cells can be further improved.

As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say.

For example, in the embodiment, the power main line for Vdd is divided into two and
It was installed on both sides of the ss power supply main line, but on the contrary, V
, s Even if the ss power supply main line is divided into two and placed on both sides of the Vdd power supply main line, the same effects as in the embodiment can be obtained.

Furthermore, when both the Vdd power supply trunk line and the Vss power supply trunk line are divided into two, short circuits between the power supply lines can be more reliably prevented.

In the above explanation, the invention made by the present inventor was mainly applied to standard cells, which is the field of application that formed the background of the invention. However, the present invention is not limited to this, and for example, The present invention can also be applied to other semiconductor devices manufactured using the building block method.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the Vd of a semiconductor device in which logic blocks and macro cells are placed and wired using the building block method.
By dividing at least one of the power supply main line for d and the power supply main line for Vss, it is possible to effectively prevent interference between the power supply lines extending from the power supply point pair of logic blocks (or macro cells) facing each other across the power supply main line to the power supply main line. Therefore, automation of the design of semiconductor devices can be achieved, which in turn promotes shortening of the development period.

[Brief explanation of the drawing]

1 is an enlarged plan view of main parts of FIG. 2 showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic plan view of this semiconductor device, and FIG. 3 is a plan view of a conventional semiconductor device. FIG. 3 is an enlarged plan view of main parts showing the power supply wiring structure. 1... Semiconductor pellet, 2.21.22... Logic block, 2a, 3a, 21a, 22a... Feeding point pair,
3... Macro cell, 4... Human output buffer circuit, 5
... Main power supply wiring, 5a... Main power supply wiring for power supply voltage (Vdd), 5b... Main power supply wiring for ground voltage (Vss), 6.20... Main power supply line, 6a, 20a... Main power supply line for power supply voltage (Vdd), 6b, 20b... Main power supply line for ground voltage (Vss), ? , 23.24...
Power line, 8... bonding pad, 9... contact hole. Figure 2

Claims (1)

[Claims] 1. A semiconductor device in which logic blocks and macro cells are arranged and wired using a building block method, which includes a main power supply line for power supply voltage and a power supply for ground voltage that supply power to the logic blocks and macro cells. A semiconductor device characterized in that at least one of the main lines is formed in sections. 2. Claim 1 characterized in that it is a standard cell.
The semiconductor device described.