JPH04151868A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten the time necessary for layout and wiring, by dispersing and arranging reserve basic cells, in which wirings are not formed, in the arrangement of many basic cells constituting a gate array, in which cells wirings are previously formed. CONSTITUTION:A logic circuit part 3 constituted of gate arrays is formed in an inner region surrounded by contact pads 2. A plurality of ROM parts 4 and RAM parts 5 are formed so as to surround the logic circuit part 3, which is constituted as follows; reserve basic cells 6, in which wirings are not formed, are dispersed and arranged in the arrangement of many basic cells in which wirings are previously formed. As a result, even when correction accompanied by addition of new library cells is required, layout and wiring having no influence upon correction can be preserved in the suitable state of layout and wiring before correction, by using the reserve basic cells 6. Thereby the time of layout and wiring can be shortened.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is an arrangement of a large number of basic cells formed by interconnecting a large number of transistors formed in a semiconductor chip using pre-formed wiring. The present invention relates to a gate array type semiconductor integrated circuit device.

(Prior Art) The gate array type semiconductor integrated circuit device as described above is known, in which all regions of transistors are formed in advance and a minimum amount of wiring is provided, and the required circuits are then assembled. Since it is only necessary to perform automatic placement and wiring using CAD according to the requirements, circuit design becomes easy, and there is an advantage that the time TAT (Turn Around Time) until product completion is shortened.

(Problem to be Solved by the Invention) In a conventional gate array type semiconductor integrated circuit device, when a modification that involves adding a library cell occurs during debugging or the like, the previously determined layout and
The drawback is that the wiring must be discarded and all layout and wiring for the entire integrated circuit must be redone.

Normally, this placement and wiring is a task that takes an extremely long time, such as several weeks, so the task of re-determining the placement and wiring significantly impairs the inherent advantage of gate arrays, which is the short TAT.

In particular, in recent years, gate arrays have become more sophisticated, and devices with ROM and RAM in addition to logic gates on the same semiconductor chip have been developed. The time required for wiring becomes even longer, and discarding the proper placement and routing determined up to that point and re-determining a new placement and routing in order to make modifications that require the addition of library cells takes longer TAT. It has the disadvantage of being long.

An object of the present invention is to eliminate the drawbacks of the conventional gate array type semiconductor integrated circuit device described above, and even when a modification involving the addition of a library cell occurs during debugging, the proper placement and wiring determined up to that point can be maintained. It is an object of the present invention to provide a gate array type semiconductor integrated circuit device that can be used as is and is configured so that the time for placement and wiring can be significantly shortened.

(Means and Effects for Solving the Problems) The present invention provides a gate array type semiconductor integrated circuit device in which a plurality of basic cells each consisting of a plurality of transistors connected to each other are arranged in a semiconductor chip. It is characterized by the fact that the basic cells for connection are arranged in a distributed manner.

In such a semiconductor integrated circuit device according to the present invention, when performing placement and wiring, if it becomes necessary to make a modification that involves adding a library cell due to debugging, it can be done by using unconnected basic cells. This can be easily dealt with, and therefore the appropriate layout and wiring state determined up to that point can be preserved. As a result, the time for placement and wiring can be shortened, and the inherent advantage of gate arrays, such as short TAT, can be utilized to the maximum extent possible.

(Embodiment) FIG. 1 is a diagrammatic plan view showing the configuration of an embodiment of a gate array type semiconductor integrated circuit device according to the present invention. In this embodiment, in addition to a logic circuit section, a ROM section and a RAM section are It was formed. That is, a large number of contact pads 2 are formed around a semiconductor chip 1, a logic circuit section 3 consisting of a gate array is formed in an internal area surrounded by these contact pads, and a plurality of ROMs are arranged to surround this logic circuit section. A portion 4 and a RAM portion 5 are formed. In FIG. 1, the basic cell rows and wiring areas that make up the logic circuit section 3 are not shown, but as usual, many basic cells are arranged vertically and horizontally, and these basic cells are It is wired. In the present invention, spare basic cells that are not wired are distributed and formed in these basic cells that have been wired in advance. In FIG. 1, only spare basic cells 6 to which wiring has not been applied and which are distributed in the logic circuit portion 3 are shown, and basic cells to which wiring has been applied in advance are not shown.

In the present invention, as described above, the unwired spare basic cells 6 are distributed and placed in the array of a large number of prewired basic cells, so that when debugging automatic placement and wiring, Even if it is necessary to make a modification that involves the addition of a new library cell, by using the spare basic cell, you can maintain the proper placement and wiring state before the modification so that the layout and wiring will not be affected by the modification. This makes debugging easier, and as a result, placement and wiring time can be significantly shortened and TAT can be improved.

Note that the present invention is not limited to the embodiments described above, and many modifications are possible. For example, in the embodiments described above, a ROM portion and a RAM portion are formed within the semiconductor chip, but these memory portions do not necessarily need to be formed.

(Effects of the Invention) As described above, in the semiconductor integrated circuit device of the present invention, a spare basic cell that is not wired is included in the array of a large number of basic cells that are wired in advance and constitutes a gate array. When debugging automatic placement and routing using distributed placement, even if it becomes necessary to make a modification that involves adding a new library cell, the placement and routing decided to be modified can be made by using spare basic cells. Ignore and place new
There is no need to redo the wiring, and the appropriate placement and wiring before modification can be used as is, and the time required for placement and wiring can therefore be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a plan view diagrammatically showing the structure of an embodiment of a semiconductor integrated circuit device according to the present invention.

Claims (1)

[Claims] 1. In a gate array semiconductor integrated circuit device formed by arranging basic cells each consisting of a plurality of transistors interconnected using pre-formed wiring within a semiconductor chip, A semiconductor integrated circuit device characterized in that spare basic cells are distributed in a distributed manner.