JPH04132253A - Output circuit - Google Patents

Abstract

PURPOSE:To reduce the influence of the finished variations of the finished gate electrode itself and to enhance anti-electrostatic destruction power by specifying each channel width of MOS transistors constituting an output circuit. CONSTITUTION:Two MOS transistor blocks 20A and 20B are laid adjacent to each other that are prepared using adjacent source domain 21 and drain domain 22, and gate electrodes 23 placed between them is made less than 30mum, and a drain wiring 28 and gate wiring 26 that are on the side where the MOS transistor blocks 20A and 20B are in contact with each other use one common wire.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and more particularly to a pressure circuit of a semiconductor integrated circuit including MOS transistors formed by arranging alternating source and drain regions.

[Conventional technology]

Figures 3 (a) to (c) regarding conventional output circuits of this type.
Explain with reference to.

FIG. 3(a) is an equivalent circuit diagram showing an example of a conventional output circuit, which is an 0MO8 type inverter.

FIG. 3(b) shows the arrangement of this output circuit on the board 1,
An output terminal 4 is formed between MOS transistors 2A and 3.

Figure 3 (C) shows the MOS transistor 2A of this output circuit.
FIG.

Next, the internal structure of this MOS transistor 2A will be explained.

This MOS transistor 2A includes source regions 21A and drain regions 22A which are alternately arranged in sequence at predetermined intervals.
and each adjacent source region 21A.

A plurality of gate electrodes 23A are formed between each drain region 22A, and a plurality of source electrodes 24A are connected to each source region 21A through a contact hole 29.
, a plurality of drain electrodes 25A each connected to each drain region 22A through a contact hole 29, a gate wiring 26A commonly connected to each gate electrode 23A, and a plurality of drain electrodes 26A commonly connected to each source electrode 24A and connected to each source region 21A and drain region 21B. A source wiring 27A formed in an outer region of the array, and a drain wiring 28A formed in an outer region commonly connected to each drain electrode 25A and facing the source wiring 27A of the array of source regions 21A and drain regions 22A. It is formed. Note that the MOS transistor 3 also has a similar internal structure.

Usually, adjacent source region 21A and drain region 2
The width of each channel formed by the gate electrode 2A and the gate electrode 23A is 50 to 150 μm, and the total dimension of these channel widths is 200 μm or more. In this example, the channel width is 100 μm, and the total channel width is 600 μm.
It becomes.

In this way, the length of one gate electrode 23A (equal to the channel width) -! The reason why x===J is small is that the area of the entire output circuit including the output terminal 4 is made small, and the arrangement with the internal circuit pattern is taken into consideration. 0 again
This is because the pattern was determined in consideration of measures against latch-up of MO3 type semiconductor integrated circuit devices. In particular, the size of the MOS transistor in the output circuit of a large-capacity semiconductor memory device is large, and the mask pattern of this MOS transistor is subject to layout restrictions.

Note that the gate length of the MOS transistor forming the output circuit is made larger than the gate length of the MOS transistor forming the internal circuit in order to prevent terminal leakage.

Therefore, the channel width also increases.

[Problem to be solved by the invention]

In the conventional output circuit described above, the internal structure of the MOS transistor has source regions 21A and drain regions 22A arranged alternately in a line, and the width of each channel is increased due to the arrangement with other internal circuits. In an environment where miniaturization progresses, each channel length becomes shorter and each gate electrode 23A becomes thinner. occurs,
This phenomenon occurs more easily as the gate electrode becomes longer, resulting in the following problems.

(1) Output terminal leaks occur more frequently.

(2) The variation in withstand capacity due to electrostatic damage of the output terminal increases.

(3) Deterioration due to hot carriers increases locally, resulting in margin failure for output.

Furthermore, even if lithography and etching techniques are improved to eliminate such problems with gate electrodes and a uniform gate electrode can be formed, the following problems remain.

Generally, the ESD (electrostatic breakdown) resistance of an output terminal is determined by the layout pattern and structure of the MOS transistors forming the output circuit. As shown in Fig. 3(c), in a pattern where the gate electrode is long, when an ESD pulse is applied, there is distance from the source wiring or drain wiring, so -
Emission from the source and drain of the gate electrode is not uniform over the entire area of the gate electrode, but the emission is concentrated in a specific area. For this reason, energy consumption per unit area increases, that is, more heat is generated, making it easier to break down.

[Means to solve the problem]

The output circuit of the present invention includes source regions and drain regions alternately arranged in sequence at predetermined intervals, a plurality of gate electrodes formed between adjacent source regions and drain regions, and a plurality of gate electrodes formed between each of the source regions and the drain regions. a plurality of source electrodes connected to each other; a plurality of drain electrodes connected to each of the drain regions; a gate wiring commonly connected to each of the gate electrodes; A source wire formed in an outer region of the array, and a drain wire commonly connected to each of the drain electrodes and formed in an outer region facing the source wire of the array of the source region and drain region. In an output circuit including at least a transistor, the source region and the drain region adjacent to each other,
The source region, the drain region, and the gate electrode are formed such that the width of each channel formed by the gate electrode disposed between them is smaller than 30 μm.

In addition, the total dimension of each channel width is 200 μm.
The source region, drain region, and gate electrode are formed in such a number that the number of the source region, drain region, and gate electrode becomes larger.

Further, each of the plurality of source regions, drain regions, gate electrodes, source electrodes, drain electrodes, gate wiring, source wiring, and drain wiring are formed in the M
Each of the MO
The gate wiring, source wiring, and train wiring of eight transistor blocks are connected to each other to form one MOS transistor.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a plan view of a main part of a semiconductor chip showing an embodiment of the present invention, and a MO of this embodiment, respectively.
S) It is a layout diagram showing the internal tank of Runcista.

The MOS transistor 2 of this embodiment has source regions 21 and drain regions 2 arranged alternately and sequentially at predetermined intervals.
2, a plurality of gate electrodes 23 formed between adjacent source regions 21 and drain regions 22, a plurality of source electrodes 24 connected to each source region 21 through a contact hole 29, and each drain region 22. A plurality of drain electrodes 25 are connected to each other through contact holes 29, a gate wiring 26 is commonly connected to each gate electrode 23, and a gate wiring 26 is commonly connected to each source electrode 24 and is formed in an outer region of the array of source regions 21 and drain regions 22. a drain wiring 28 formed in an outer region facing the source wiring 27 in the arrangement of the source region 21 and the drain region 21 and commonly connected to each drain electrode;
a source region 21 and a drain region 22 adjacent to each other, and a gate electrode 2 disposed between them.
The width of each channel formed by 3 and 3 is 30 μm each.
Two MOs in which each source region 21, each drain region 22, and each gate electrode 23 are formed to be smaller than m.
S transistor block 20A.

20B are arranged and formed adjacent to each other, and the drain wiring 28 and gate wiring 26 on the sides of these MOS transistor blocks 20A and 20B that are in contact with each other are shared by one wire. Further, the total dimension of each channel width is 600 μm in this embodiment, similar to the conventional example.

Next, the effects of this embodiment will be explained.

First, by reducing the width of each channel, it is possible to reduce variations in the width between the ends and the center of each gate electrode 23, and also to suppress the occurrence of minute defects.

Therefore, the occurrence of pressure terminal leakage can be suppressed, variations in withstand capacity due to electrostatic discharge damage of the output terminal 4 can be reduced, and margin defects with respect to output due to hot carriers can be prevented from occurring.

Moreover, since each channel width is reduced, the difference in distance between the source wiring 27 or the drain wiring 28 is reduced, and the local concentration of charges emitted from the source or drain is reduced, and the ESD resistance is improved. FIG. 2 shows the results of a sample test conducted to confirm this improvement in ESD resistance.

This sample test had a total channel width of 200 μm;
ESD by changing the length of the gate electrode (channel width) and the number of source regions, drain regions, and gate electrodes.
As can be seen from FIG. 2, the ESD failure rate can be reduced by reducing the width of each channel to 30 μml or less.

In this example, the case where there are two MOS transistor blocks is shown, but depending on the external shape of the MOS transistors and the layout relationship with other circuits, an even number of MOS transistor blocks such as four or six may be used. A MOS transistor can also be formed by this method.

Furthermore, in this embodiment, the MOS transistor 2A
Although the present invention is applied only to the MOS transistor 3, it can be similarly applied to the MOS transistor 3 and transistors of other circuits.

〔Effect of the invention〕

As explained above, the present invention is based on the MOS that constitutes the output circuit.
By creating a structure in which the width of each channel of the transistor is 30 μm or less, it is possible to reduce the influence of variations in the finish of the gate electrode itself, and the difference in distance between the source electrode and the train electrode is reduced, so the source, The charge emitted from the drain becomes uniform in each part of each channel, which has the effect of improving ESD (electrostatic discharge) resistance.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are a plan view of a main part of a semiconductor chip showing an embodiment of the present invention, and a MO of this embodiment, respectively.
Layout diagram showing the internal structure of the S transistor, Figure 2 is the first
Figure 3 (a) is a characteristic diagram showing the results of sample tests to explain the effects of the embodiment shown in Figures (a) and (b).
) to (c) are an equivalent circuit diagram of an example of a conventional output circuit, a plan view of a main part of a semiconductor chip, and a layout diagram showing the internal structure of a MOS transistor, respectively. 1... Board, 2.2A, 3...M
OS transistor, 4...Output terminal, 20A,
2011...MOS transistor block, 2
1, 21A... Source area, 22, 22A...
...Drain region, 23,23A...Gate electrode, 24.24A...Mountain/source electrode, 25°25
A...Drain KL 26.26A/Old...
Kate wiring, 27.27A... Source wiring, 2
8.28A...Train distribution L29...
contact hole. Channel width per gate electrode [μm] Number of gate electrodes [pieces] Figure 2

Claims (1)

[Claims] 1. Source regions and drain regions alternately arranged in sequence at predetermined intervals, a plurality of gate electrodes formed between adjacent source regions and drain regions, and each source region. a plurality of source electrodes each connected to the
A plurality of drain electrodes each connected to each of the drain regions, a gate wiring commonly connected to each of the gate electrodes, and a source commonly connected to each of the source electrodes and formed in an area outside the array of the source and drain regions. an output circuit including at least a transistor formed with a wiring and a drain wiring commonly connected to each of the drain electrodes and formed in an outer region facing the source wiring of the array of the source region and the drain region. The source region, the drain region, and the gate electrode are arranged such that the width of each channel formed by the source region and drain region and the gate electrode disposed therebetween is smaller than 30 μm. An output circuit characterized in that: 2. A source region, a drain region, and a drain region in such a number that the total dimension of each channel width is larger than 200 μm.
The output circuit according to claim 1, further comprising a gate electrode and a gate electrode. 3. An even number of MOS transistor blocks each having a plurality of source regions, drain regions, gate electrodes, source electrodes, drain electrodes, gate wiring, source wiring, and drain wiring formed therein are arranged adjacent to each other and are in contact with each other. A single MOS transistor is formed by connecting the gate wiring, source wiring, and drain wiring of each MOS transistor block by sharing the gate wiring, source wiring, and drain wiring arranged on the side. The output circuit according to item 1 or 2.