JP2001056486A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an IC drive circuit and the connection of the IC drive circuit to a transparent substrate side by fonning the contact layers of the source regions and drain regions of high-voltage resistance MIS transistors(TRs) by offsetting the same form element separation regions. SOLUTION: Gate electrodes 19 are formed on the surfaces of well layers 12 in the forming regions of the high-voltage resistance MOS TRs so as to run on the central parts. Low-concentration diffusion layers of p-type are formed between the gate electrodes 19 and peripheral LOCOS layers 13 with the gate electrodes 19 in-between, by which the source regions 20 and the drain regions 21 are formed. The contact layers 22 and 23 are formed by the high- concentration diffraction layers of p-type in the respectively source regions 20 and the drain regions 21. The respective contact layers 22 and 23 are formed in part of the source regions 20 and the drain regions 21 in the same manner as in the case of standard MOS transistors and are formed apart (offset) a specified distance particularly from the peripheral LOCOS layers 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, for example, to an active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art This type of liquid crystal display device extends in the x direction and is juxtaposed in the y direction on a liquid crystal side surface of one of the transparent substrates disposed opposite to each other with a liquid crystal interposed therebetween. A gate signal line and a drain signal line which is insulated from the gate signal line, extends in the y direction, and is juxtaposed in the x direction are formed.

A region surrounded by each of these signal lines is defined as a pixel region, and a thin film transistor driven by supplying a scanning signal to a gate signal line in this pixel region, and a signal from a drain signal line via the thin film transistor. A pixel electrode to which a video signal is supplied.

The supply of a scanning signal to a gate signal line and the supply of a video signal to a drain signal line are controlled by I
This is performed by a vertical scanning circuit and a video signal driving circuit composed of a C driving circuit, each of which is connected to each signal line and mounted on one of the transparent substrates.

[0005]

However, in the liquid crystal display device configured as described above, a high-voltage MOS transistor and a standard MOS transistor other than the high-voltage MOS transistor are formed in the IC driving circuit. It has been pointed out that the well layer must be formed with different impurity concentrations, resulting in an increase in the number of manufacturing steps.

[0006] With the recent increase in the definition of the device,
Not only the interval between each signal line is narrowed, but also the pitch of the bumps of the IC drive circuit is narrowed. In this case, inconveniences such as poor connection between the bumps and the terminals on the transparent substrate side are pointed out. I was

The present invention has been made in view of such circumstances, and an object thereof is to provide an IC driving circuit and a liquid crystal display device in which the connection of the IC driving circuit to the transparent substrate is improved. It is in.

[0008]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

Means 1. What is claimed is: 1. A liquid crystal display device comprising an IC drive circuit for supplying a signal to a signal line, wherein the IC drive circuit includes a plurality of MIS transistors separated from each other. The high-breakdown-voltage MIS transistor and the other MIS transistors are formed in well layers having the same concentration, respectively, and the contact layer of the source region and the drain region of the high-breakdown-voltage MIS transistor is an element isolation region. Is formed so as to be offset from.

In the IC drive circuit thus configured, the contact layers of the source region and the drain region are offset from the element isolation region, so that the adjacent MI drive circuit has the same structure.
Since a current due to a break hardly flows between the transistor and the S transistor, a high breakdown voltage transistor can be obtained.

Therefore, the concentration of the well layer in which the high breakdown voltage MIS transistor is formed does not need to be particularly low, and the concentration can be made equal to the concentration of the well layer in which the standard MIS transistor is formed. I can plan.

Means 2. What is claimed is: 1. A liquid crystal display device comprising: an IC drive circuit for supplying a signal to a signal line, wherein the IC drive circuit has respective pads arranged in parallel in an x direction, and odd-numbered pad groups correspond to even-numbered pad groups The diode is slightly displaced in the y-direction, and a diode formed under one pad and another diode adjacent to the diode and juxtaposed with the other pad. A current prevention circuit is configured, and
Each diode is defined by an element isolation layer, and each pad is formed in a region surrounded by the element isolation layer.

In the IC drive circuit thus configured, since the pads are arranged in a zigzag pattern, the pitch between them can be reduced.

Since the area of the diode formed under each pad and the other diodes constituting the overcurrent protection circuit can be reduced, the pad can be formed sufficiently large so as not to cause a connection failure. become.

Further, by forming each pad in a region surrounded by the element isolation layer, the heights thereof can be made uniform.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the liquid crystal display device according to the present invention will be described below with reference to the drawings.

<< Schematic Configuration of Liquid Crystal Display >> FIG. 2 is a schematic configuration diagram showing one embodiment of a liquid crystal display device according to the present invention.
Although the figure is shown by an equivalent circuit, it is drawn corresponding to an actual geometrical arrangement.

In FIG. 1, a gate signal line 2 extending in the x direction and juxtaposed in the y direction is formed on a liquid crystal side surface of one of a pair of transparent substrates 1 opposed to each other via a liquid crystal.
And x extending in the y direction while being insulated by the gate signal line 2
And drain signal lines 3 arranged side by side in the direction.

A rectangular area surrounded by each signal line is a pixel area. Each pixel area includes a thin film transistor TFT driven by the supply of a scanning signal from the gate signal line 2 and a thin film transistor TFT via the thin film transistor TFT. A pixel electrode (transparent electrode) PX to which a video signal from the drain signal line 3 is supplied is provided.

It is to be noted that the pixel electrode P of the video signal is provided between the pixel electrode PX and another adjacent gate signal line 2 which is different from the gate signal line 2 for driving the thin film transistor TFT.
A capacitive element Cadd for accumulating data in X is formed.

The pixel electrode PX generates an electric field between a common electrode (transparent electrode) formed in common for each pixel on the liquid crystal side surface of the other transparent substrate 4 disposed via a liquid crystal,
The light transmittance of the liquid crystal is controlled.

One end of each gate signal line 2 extends beyond one of the transparent substrates 1 beyond the liquid crystal sealing area with the other transparent substrate 4.
And connected to output bumps of a vertical scanning circuit 5 mounted face-down on the transparent substrate 1.

In this case, the vertical scanning circuit 5 is composed of a plurality of IC driving circuits, and one IC driving circuit is applied to each gate signal line 2 in which adjacent gates are grouped. It has become.

The vertical scanning circuit 5 forms a scanning signal by a signal from the input bump side, and sequentially supplies the scanning signal to each gate signal line 2.

Further, one end of each drain signal line 3 also extends to an end of one of the transparent substrates 1 beyond the liquid crystal sealing region with the other transparent substrate 4 and faces down to the transparent substrate 1 by face-down. It is connected to the output bump of the mounted video signal drive circuit 6.

In this case, the video signal driving circuit 6 also includes a plurality of I
One IC drive circuit is constituted by a C drive circuit, and is applied to each drain signal line in which adjacent gates are grouped.

The video signal drive circuit 6 forms a video signal by the signal from the input bump side, and supplies this video signal to each drain signal line 3 in accordance with the timing of the scanning signal from the vertical scanning circuit 5. It has become.

<< Embodiment of IC Driving Circuit >> FIG. 1 is a diagram showing a cross section of a partial area of an IC driving circuit comprising, for example, the video driving circuit 6.

The IC drive circuit shown in FIG. 1 incorporates a standard MOS transistor forming a logic circuit and a high voltage MOS transistor forming an amplifier or an output circuit, and these are shown side by side. .

First, there is a semiconductor substrate 11, and, for example, an n-type well layer 12 is formed on the surface of the semiconductor substrate 11.

In this embodiment, the well layer 12 has a region where a standard MOS transistor is formed and a high breakdown voltage M
In the regions where the OS transistors are formed, all have the same concentration without any difference in concentration.

The surface of each well layer 12 has
Define each MOS transistor (hence the standard MOS
LOCOS layer 1 made of an oxide film having a relatively large thickness (even between a transistor and a high breakdown voltage MOS transistor)
3 are formed, so that isolation (element isolation) of each MOS transistor can be achieved.

On the surface of the well layer 12 in the formation region of the standard MOS transistor, a gate electrode 14 is formed so as to run in the center thereof.
Between the gate electrode 14 and the surrounding LOCOS layer 1
3, a p-type low concentration diffusion layer is formed, and a source region 14 and a drain region 15 are formed.

Each of the source region 14 and the drain region 15 has a contact layer 16, 1 for making contact with the source electrode and the drain electrode.
7 is formed of a p-type high concentration diffusion layer.

In this case, each of the contact layers 16 and 17 is formed in a part of the source region 14 and the drain region 15 and is formed in contact with the peripheral LOCOS layer 13.

A gate electrode 19 is also formed on the surface of the well layer 12 in the region where the high breakdown voltage MOS transistor is formed so as to run in the center thereof.
Between the gate electrode 19 and the peripheral LOCOS layer 13, a p-type low concentration diffusion layer is formed, and a source region 20 and a drain region 21 are formed.

Each of the source region 20 and the drain region 21 has a contact layer 22 for making contact with the source electrode and the drain electrode.
23 is formed of a p-type high concentration diffusion layer.

Here, each of these contact layers 22 and 23
Are formed in a part of the source region 20 and the drain region 21 as in the case of the standard MOS transistor, but are formed at a certain distance (offset) from the peripheral LOCOS layer 13. This has a structural difference.

With such a structure, the contact layer formed in contact with the LOCOS layer breaks as in the related art, and the side of the adjacent MOS transistor is interposed via the channel stopper layer formed below the LOCOS layer. Can be avoided.

In other words, in the formation region of the high breakdown voltage MOS transistor, the concentration of the well layer does not need to be particularly low as in this embodiment (in other words, the standard MOS transistor).
In accordance with the concentration of the well layer on the transistor side), a MOS transistor having a sufficient withstand voltage can be formed.

From this, in this embodiment, the LOCOS formed around the high breakdown voltage MOS transistor is used.
N formed under the layer 13 to improve the breakdown voltage
The structure is such that a channel stopper layer of a high concentration is not particularly formed.

<< Manufacturing Method >> FIG. 3 shows each MO shown in FIG.
This shows a method of manufacturing a high breakdown voltage MOS transistor (left side in the figure) among S transistors in comparison with a method of manufacturing a conventional structure (right side in the figure).

The steps will be described below in the order of the steps.

Step 1. As shown in FIG. 1A, a semiconductor substrate 11 is prepared, and an n-type well layer 1 is formed over the entire surface thereof.
Form 2 The well layer 12 has the same concentration as the well layer in the standard MOS transistor and is set to have a relatively high concentration.

Then, a MOS is formed on the surface of the well layer 12.
The LOCS layer 1 is formed so as to define each transistor forming region.
Form 3

Further, a gate electrode 19 is formed in each of the regions surrounded by the LOCOS layer 13, and a p-type impurity is diffused using the gate electrode 19 and the LOCOS layer 13 as a mask to form a source region 20 and a drain region 21. To form

In the conventional case, before the LOCOS layer 13 is formed, the channel stopper layer 30 is formed in a region where the LOCOS layer 13 is formed.
Is formed, but this embodiment eliminates the need for this step.

Step 2. As shown in FIG. 1B, a photoresist film 31 is formed over the entire surface of the semiconductor substrate, and the photoresist film 31 is selectively exposed through a photomask.

In this case, the photosensitive region of the photoresist film corresponds to the formation region of each contact layer of the source region and the drain region.
It is necessary to make the portion slightly separated from the OS layer 13.

In the conventional case, this photosensitive area is LOCOS
It extended to the area on the layer.

Step 3. Exposed photoresist film 31
Is developed to form a hole in the photoresist film 13.

In this case, the hole is formed so that a part of the source region and the drain region is exposed.
The position is offset from the LOCOS layer 13.

Then, the contact layers 22 and 23 are formed by ion-implanting a p-type impurity through the photoresist film thus perforated.

The contact layers 22, 23 are LOCOS
It will be formed at a position offset from the layer 13.

In the conventional case, the contact layer is formed so as to be connected to the LOCOS layer.

Step 4. After the photoresist film 31 is completely removed and an insulating film is formed on the entire surface, holes for exposing the contact layers 22 and 23 are provided in the insulating film, and a metal wiring ( A source electrode and a drain electrode) are formed over the insulating film.

According to the above-described manufacturing method, the step of forming a well layer having a high concentration on the side of the high breakdown voltage MOS transistor with respect to the well layer on the side of the standard MOS transistor;
The step of forming a channel stopper layer below the COS layer can be reduced.

<< Another Embodiment of IC Driving Circuit >> FIG. 4 is a sectional view showing another embodiment of an IC driving circuit composed of, for example, a video driving circuit.

FIG. 11 is a cross-sectional view showing the structure of a standard MOS transistor in an IC drive circuit.

In the figure, a LOCOS layer 13 is formed so as to surround a formation region of a standard MOS transistor on a surface of a well layer 12 on an upper surface of a semiconductor substrate 11.

Then, a gate electrode 14 made of polycrystalline silicon is formed so as to divide the region surrounded by the LOCOS layer 13 into two.

The gate electrode 14 has a structure in which the gate electrode 14 is covered with a laminated insulating film and an insulating film formed as a side wall.

Using the insulating film covering the gate electrode 14 and the LOCOS layer 13 as a mask, a P-type impurity (As) is diffused to form a source region 14 and a drain region 15.

Since the source region 14 and the drain region 15 are formed using the insulating film covering the gate electrode 14 as a mask, the source region 14 and the drain region 15 are formed at positions separated from the gate electrode 14 (offset).

The standard MOS transistor having such a structure is different from the standard MOS transistor shown in FIG.
Since 5 is composed of a single ion, the effect of improving the electrostatic breakdown voltage is achieved.

That is, in the standard MOS transistor shown in FIG. 1, the source region 14 and the drain region 15 have a two-layer structure of phosphorus (P) and arsenic (As). There is an inconvenience that heat is destroyed by the heat generated by the resistance portion due to the difference in density.

<< Manufacturing Method >> FIG. 5 shows the standard M shown in FIG.
The method of manufacturing the OS transistor (left side in the figure) is shown in comparison with the method of manufacturing the conventional structure (right side in the figure).

Hereinafter, description will be made in the order of steps.

Step 1. As shown in FIG. 5A, a well layer 12 is formed on an upper surface of a semiconductor substrate 11, and a LOCOS layer 13 is formed in the well layer 12 so as to surround a formation region of each MOS transistor.

Further, a gate electrode 14 is formed on the upper surface of the well layer 13 surrounded by the LOCOS layer so as to bisect the well layer.

Then, a photoresist film 4 is formed on the entire surface.
0 is formed. This photoresist film serves as a mask for preventing the impurities from entering when forming, for example, a source region and a drain region of a high voltage MOS transistor (not shown).

In the conventional case, the source region 14 and the drain region 15 are formed by exposing the well layer 13 from the photoresist film and implanting phosphorus (P) using the LOCOS layer 13 and the gate electrode 14 as a mask. .

Step 2. As shown in FIG. 5B, the photoresist film 40 is removed, and an insulating film to be deposited on the gate electrode 14 and an insulating film to be a sidewall are formed.

The same applies to the conventional case.

Step 3. As shown in FIG. 5C, a photoresist film 41 is formed over the entire surface, and holes are formed in the photoresist film 41 to expose a region surrounded by the LOCOS layer.

By implanting arsenic (As) through this hole, a source region 16 and a drain region 17 are formed.

In this case, the source region 16 and the drain region 17 are formed by the side wall of the gate electrode 14 and the LO region.
It is formed using the COS layer as a mask.

In the conventional case, arsenic (As) is similarly implanted. In this case, the source region and the drain region have a two-layer structure with different concentrations, together with the phosphorus (P) implanted layer in the step shown in FIG.

Therefore, in order to make the concentrations in the source region and the drain region uniform, a phosphorus (P) implantation step is required in the next step (FIG. 5D). This is because, as described above, when a large current flows, there is a disadvantage that heat is generated in the resistance portion due to the concentration difference of the two-layer structure and the heat is destroyed.

In this embodiment, since the source region 16 and the drain region 17 formed in the step of FIG. 5C have a single-layer structure, the step shown in FIG.

Step 4. After the photoresist film 41 is completely removed and an insulating film is formed on the entire surface, holes for exposing the source region 16 and the drain region 17 are provided in the insulating film, and metal holes connected to the respective regions are formed through the holes. A wiring (including a source electrode and a drain electrode) is formed over the insulating film.

According to the method of manufacturing an IC drive circuit described above, the number of manufacturing steps can be reduced.

<< Connection of IC Drive Circuit to Substrate >> FIG. 6
FIG. 3 is a plan view showing a part of each input-side bump of the IC drive circuit, for example.

The bumps 50 are arranged in a staggered pattern, that is, the bumps 50 are arranged side by side in the x direction, and the odd-numbered bump groups are slightly displaced in the y direction with respect to the even-numbered bump groups. .

Each of these bumps 50 is provided with an overcurrent prevention circuit due to static electricity or the like.

For example, as shown in FIG. 6C, the odd-numbered bumps 50A are connected to the P-type diffusion layer 42 formed in the n-type well layer 12 to form pads 50a made of, for example, aluminum. It is configured. That is, a diode having a junction between the n-type well layer 12 and the p-type diffusion layer 42 is connected in series to the pad 50a.

In this case, the P-type diffusion layer is a LOCOS layer 13
The pad 50a is formed by the LOCOS
It is formed so as to overlap the P-type diffusion layer 42 without overlapping the layer 13.

The diode formed immediately below the pad 50a is adjacent to the diode and another diode arranged in parallel with the even-numbered bump 50B constitutes an overcurrent prevention circuit.

That is, another diode 51B is formed by forming an N-type diffusion layer in a P-type well layer.

The diode formed immediately below the pad 50a and another diode adjacent thereto are shown in FIG.
The connection is made as shown in the equivalent circuit of FIG. 2B, thereby constituting an antistatic circuit.

The area of the n-type diffusion layer is smaller than that of the p-type diffusion layer 42 under the pad, whereby the even-numbered bumps 50A are close to each other, in other words, the pitch is reduced. It will be possible to arrange it.

Each diode of the pair constituting the overcurrent protection circuit has a different characteristic, but there is no particular problem in the properties of the circuit.

The even-numbered bumps 50B are each formed by forming a pad 50b made of aluminum by being connected to an n-type diffusion layer formed in a p-type well layer. The p-type well layer and n
The diodes having the junctions of the diffusion layers are connected in series.

Also in this case, the n-type diffusion layer is formed so as to be surrounded by the LOCOS layer, and the pad 50a is formed on the n-type diffusion layer without overlapping the LOCOS layer.

The diode formed immediately below the pad 50b is adjacent to the diode and another diode arranged in parallel with the odd-numbered bump 50A constitutes an overcurrent prevention circuit.

That is, another diode is formed by forming a p-type diffusion layer in an n-type well layer.

The area of the p-type diffusion layer is smaller than that of the n-type diffusion layer under the pad 50b, so that the odd-numbered pads are close to each other, in other words, the pitch is reduced. Can be arranged.

Also in this case, the diode formed immediately below the pad 50b and another diode 51A adjacent thereto are connected as shown in the equivalent circuit of FIG. 6B, thereby forming the antistatic circuit. Configuration.

The pair of diodes constituting the overcurrent protection circuit are formed with different characteristics, respectively.
As described above, there is no particular problem in the nature of the circuit.

In the above embodiment, the configuration on the input bump side is shown, but the configuration on the output bump side is also the same.

In the IC driving circuit having the bumps according to this embodiment, the pitch of the bumps can be reduced, and the bumps are formed in the region surrounded by the LOCOS layer 13. Has the effect of being able to align the values with high accuracy.

[0102]

As is apparent from the above description,
ADVANTAGE OF THE INVENTION According to the liquid crystal display device by this invention, what improved the IC drive circuit and the connection of this IC drive circuit to the transparent substrate side can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of an IC driving circuit provided in a liquid crystal display device according to the present invention.

FIG. 2 is a partially broken plan view showing one embodiment of the liquid crystal display device according to the present invention.

FIG. 3 is a process chart showing one embodiment of a method of manufacturing the IC drive circuit shown in FIG. 1;

FIG. 4 is a sectional view showing another embodiment of an IC driving circuit provided in the liquid crystal display device according to the present invention.

FIG. 5 is a process chart showing one embodiment of a method of manufacturing the IC drive circuit shown in FIG.

FIG. 6 is a configuration diagram showing one embodiment of a bump of an IC driving circuit provided in the liquid crystal display device according to the present invention.

[Explanation of symbols]

5 vertical scanning circuit (IC driving circuit), 6 video signal driving circuit (IC driving circuit), 11 semiconductor substrate, 12 well layer, 13 LOCOS layer, 14, 19 gate electrode,
14, 20 ... source region, 15, 21 ... drain region,
16, 17, 22, 23 ... contact layer.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeru Ito 3300 Hayano, Mobara-shi, Chiba Prefecture Within Hitachi, Ltd.Display Group (72) Inventor Akira Ogura 3681-Hayano, Mobara-shi, Chiba Prefecture Within Hitachi Device Engineering Co., Ltd. (72 ) Inventor Noboru Kataoka 3300 Hayano, Mobara-shi, Chiba Prefecture Within Hitachi Display Group, Ltd. AA02 AA05 AA09 AB07 AB10 AC01 AC06 AC10 BA01 BC01 BC06 BC18 BE01 BE03 BG12 CC06 DA25

Claims (5)

[Claims] 1. A liquid crystal display device comprising an IC drive circuit for supplying a signal to a signal line, wherein the IC drive circuit includes a plurality of MIS transistors separated from each other.
The transistor is composed of a high-breakdown-voltage MIS transistor and another MIS transistor. The high-breakdown-voltage MIS transistor and the other MIS transistors are formed in well layers having the same concentration, respectively. A liquid crystal display device wherein the contact layer in the region is formed offset from the element isolation region. 2. The liquid crystal display device according to claim 1, wherein no channel stopper layer is formed below the element isolation layer surrounding the high breakdown voltage MIS transistor. 3. A liquid crystal display device comprising an IC drive circuit for supplying a signal to a signal line, wherein the IC drive circuit includes a plurality of MIS transistors separated from each other.
The transistor comprises a high-breakdown-voltage MIS transistor and other standard MIS transistors, and the standard MIS transistor has a single-layer structure in which a source region and a drain region are formed offset from a gate electrode. Liquid crystal display. 4. A liquid crystal display device comprising an IC drive circuit for supplying a signal to a signal line, wherein each pad of the IC drive circuit is arranged in the x direction.
The odd-numbered pad group is slightly displaced in the y-direction from the even-numbered pad group, and the diode formed under one pad and the diode adjacent to the diode and the other An overcurrent prevention circuit is constituted by another diode provided in parallel with the pad, and each diode is defined by an element isolation layer, and each pad is a region surrounded by the element isolation layer. A liquid crystal display device formed on a liquid crystal display. 5. The liquid crystal display according to claim 4, wherein an area of a diffusion layer of another diode forming an overcurrent prevention circuit together with the diode is smaller than that of a diffusion layer forming a diode below the pad. apparatus.