KR100521256B1 - Thin film transistor substrate for liquid crystal display device applying pair thin film transistor - Google Patents

Abstract

In the thin film transistor for a liquid crystal display device, two thin film transistors are formed in pairs so as to have mutual mirror symmetry for each pixel. That is, the first and second gate electrodes, which are branches of the gate lines, are formed side by side, the gate insulating films are stacked, the first and second semiconductor pieces are formed on the gate insulating films on the first and second gate electrodes, and the data lines are branched. The phosphorus source electrode is formed to contact the first and second semiconductor pieces. The protective film is formed by forming the first and second drain electrodes on the first and second semiconductor pieces so as to have mutual mirror symmetry, laminating a protective film, and forming a contact hole exposing the first and second drain electrodes on the protective film. The pixel electrode formed thereon is connected to the first and second drain electrodes. In this way, stitch defects due to pattern misalignment can be reduced, pixel electrodes can be sufficiently charged even with a short gate pulse time, and pixel defects due to thin film transistor defects can be reduced.

Description

Thin film transistor substrate for liquid crystal display device applying pair thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate for a liquid crystal display device and a manufacturing method thereof, and more particularly, to a thin film transistor substrate for a liquid crystal display device employing a dual thin film transistor and a manufacturing method thereof.

Now, a thin film transistor substrate for a liquid crystal display according to the related art will be described with reference to the drawings.

1 is an equivalent circuit diagram of a thin film transistor substrate for a liquid crystal display device according to the related art.

One thin film transistor is formed in each pixel area where the gate line 200 and the data line 700 cross each other. The gate electrode 210 of the thin film transistor is connected to the gate line 200, the source electrode 730 is connected to the data line 700, and the drain electrode 710 is connected to the pixel electrode 900. have. The liquid crystal capacitor C _LC is formed between the pixel electrode 900 connected to the drain electrode 710 of the thin film transistor and the common electrode at the common potential, and is formed at the pixel electrode 900 and the storage capacitor potential V _ST . The storage capacitor C _ST is formed between the storage capacitor electrodes 310. At this time, the storage capacitor potential V _ST and the common potential may be equipotential. Parasitic capacitance C _GD is formed between the gate electrode 210 and the drain electrode 710 of the thin film transistor.

As described above, the liquid crystal display driving one pixel electrode with one thin film transistor has the following problems.

First, as the liquid crystal display becomes larger, the panel size becomes larger than the mask used in the photolithography process during the thin film transistor and pixel electrode formation. Therefore, one panel is divided into several zones and the mask is moved several times while moving the mask. If a misalignment of the mask occurs in this process, it causes a stitch defect that causes a difference in luminance between the respective exposure zones. do. The main cause of the stitch failure is a difference in kickback voltage due to the difference in parasitic capacitance C _GD between the gate electrode 210 and the drain electrode 710. The reason why the parasitic capacitance between the gate electrode 210 and the drain electrode 710 is different for each of the exposure areas is that the degree of mask misalignment during the formation of the gate electrode 210 and the formation of the drain electrode 710 is different in each exposure area. Because it is very different.

In addition, as the liquid crystal display becomes larger, the gate pulse time becomes shorter, so that charging time to the pixel electrode 900 decreases, thereby preventing sufficient charging.

In the conventional thin film transistor substrate for liquid crystal display devices, one thin film transistor is formed for each pixel, and if the thin film transistor does not operate in a bad state, the pixel completely loses its function.

An object of the present invention is to reduce the stitch failure caused by mask misalignment in the liquid crystal display device.

Another object of the present invention is to provide sufficient charge to the pixel electrode of the liquid crystal display even when a short gate pulse is applied.

Another object of the present invention is to reduce the pixel defects caused by the failure of the thin film transistor of the liquid crystal display device.

In order to solve the above problems, in the present invention, two thin film transistors are formed in pairs so as to have mutual mirror symmetry for each pixel.

That is, the first and second gate electrodes, which are branches of the gate lines, are formed side by side, the gate insulating films are stacked, the first and second semiconductor pieces are formed on the gate insulating films on the first and second gate electrodes, and the branch of the data lines is formed. The phosphorus source electrode is formed to contact the first and second semiconductor pieces. The protective film is formed by forming the first and second drain electrodes on the first and second semiconductor pieces so as to have mutual mirror symmetry, laminating a protective film, and forming a contact hole exposing the first and second drain electrodes on the protective film. The pixel electrode formed thereon is connected to the first and second drain electrodes.

Here, the storage capacitor line may be formed parallel to the gate line, the data line may be formed in the shape of a square wave, and the pixel region may be delta-arranged. The semiconductor layer may further include a doped amorphous silicon layer between the semiconductor piece and the source and drain electrodes. Alternatively, the semiconductor pieces may be formed of polycrystalline silicon.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 3 is a cross-sectional view taken along line III-III 'of FIG. 2, and a vertical dotted line of FIG. 3 is III- of FIG. 2. 4 is an equivalent circuit diagram of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

The storage capacitor line 30 and the gate line 20 are formed on the insulating substrate 10 such as glass and extend horizontally, and the two gate electrodes 21 and 22, which are vertical branches of the gate line 20, are held. Two storage capacitor electrodes 31, which are branches in the longitudinal direction of the capacitor line 30, are formed. The gate insulating film 40 is laminated on these, and the semiconductor pieces 51 and 52 which consist of amorphous silicon, polycrystalline silicon, etc. are formed on the gate insulating film 40 on the gate electrodes 21 and 22, and a semiconductor piece A high concentration of doped amorphous silicon pieces 61, 62, and 63 are formed on the 51 and 52 to form drain electrodes 71 and 72 formed on the doped amorphous silicon pieces 61, 62 and 63, and The contact resistance between the source electrode 73 and the semiconductor pieces 51 and 52 is reduced. At this time, the doped amorphous silicon pieces 61, 62, 63 are not necessarily formed. Further, on the gate insulating film 40, the data line 70 extends vertically in the shape of a square wave, and the source electrode 73, which is a branch of the data line 70, crosses the two semiconductor pieces 51, 52. It is formed on the amorphous silicon piece 63 doped so as to cross it, and the two drain electrodes 71 and 72 are formed to have mutual mirror image symmetry. At this time, the data line 70 may not be a square wave shape but may be straight, and the drain electrodes 71 and 72 extend from above the doped amorphous silicon pieces 61 and 62 to the gate insulating film 40 and partially. The parasitic capacitors C _GD1 and C _GD2 are generated between the gate electrodes 21 and the gate electrodes 21 and 22 and the drain electrodes 71 and 72. A passivation layer 80 is stacked on the data line 70, the source electrode 73, and the drain electrodes 71 and 72, and the passivation layer 80 is disposed on the drain electrodes 71 and 72. Contact holes 81 and 82 exposing 72 are formed. The pixel electrode 90 made of indium tin oxide (ITO) or the like, which is connected to the drain electrodes 71 and 72 through the contact holes 81 and 82, is formed on the passivation layer 80.

In FIG. 2, the pixel areas are arranged in a row in the horizontal direction, but are arranged so as to cross in the vertical direction. Such an arrangement is called a delta array. Delta arrays are more advantageous than checkered arrays to represent circles, curves, and so on.

In this thin film transistor substrate for liquid crystal display devices, as shown in FIG. 4, two thin film transistors are formed in each pixel region. The gate electrodes 21 and 22 of the two thin film transistors are connected to the gate line 20, the source electrode 73 is connected to the data line 70, and the drain electrodes 71 and 72 are pixel electrodes 90. ) The liquid crystal capacitor C _LC is formed between the pixel electrode 90 connected to the drain electrodes 71 and 72 of the two thin film transistors and the common electrode at the common potential, and the pixel electrode 90 and the storage capacitor potential V are formed. a storage capacitor (C _ST) between the storage capacitor electrode 31 in the _ST) is formed. At this time, the storage capacitor potential V _ST and the common potential may be equipotential. In addition, parasitic capacitances C _GD1 and C _GD2 are formed between the gate electrodes 21 and 22 and the drain electrodes 71 and 72 of the two thin film transistors, respectively.

In this case, even if misalignment occurs in the patterning process of each layer, the total area where the gate electrodes 21 and 22 and the drain electrodes 71 and 72 overlap is constant. For example, when the misalignment occurs when the drain electrodes 71 and 72 are formed and the first drain electrode 71 is biased to the right as compared with the case where misalignment does not occur, the first gate electrode 21 and the first drain electrode The overlapping area of 71 is reduced so that the parasitic capacitance C _GD1 between them is reduced. However, when the first drain electrode 71 is misaligned to the right, the second drain electrode 72 patterned at the same time as the first drain electrode 71 is also skewed to the right. In this case, the second gate electrode 22 The overlapping area of the second drain electrode 72 is increased to increase the parasitic capacitance C _GD2 therebetween. That is, the total parasitic capacitance C _GD1 + C _GD2 between the gate electrodes 21 and 22 and the drain electrodes 71 and 72 for each pixel is almost the same as when no misalignment occurs. As a result, the kickback voltage due to the parasitic capacitance C _GD1 + C _GD2 between the gate electrodes 21 and 22 and the drain electrodes 71 and 72 can be made constant throughout the panel regardless of whether misalignment occurs. Can prevent the stitch defect

In addition, since two channels for transferring charge to the pixel electrode 90 increase, sufficient charging may be achieved even if the charging time is short.

In addition, since two thin film transistors are formed for each pixel, even if one of the two thin film transistors does not operate, if the other one operates, the pixel may function to some extent, thereby reducing pixel defects.

When two thin film transistors having mirror symmetry are formed in pairs for each pixel as in the present invention, stitch defects due to pattern misalignment can be reduced, and pixel electrodes can be sufficiently charged even with a short gate pulse time. Pixel defects due to defects can be reduced.

1 is an equivalent circuit diagram of a thin film transistor substrate for a liquid crystal display device according to the prior art,

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a cross-sectional view taken along the line III-III 'of FIG. 2,

4 is an equivalent circuit diagram of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

Claims (6)

Insulation board, A gate line extending horizontally on the insulating substrate, First and second gate electrodes branched from the gate line and formed in parallel with each other; A gate insulating film stacked on the gate line and the gate electrode; First and second semiconductor pieces formed on the gate insulating layer on the first and second gate electrodes, A data line extending vertically over the gate insulating film; A source electrode which is a branch of the data line and is in contact with the first and second semiconductor pieces; A first drain electrode formed on the first semiconductor piece, A second drain electrode formed on the second semiconductor piece, the second drain electrode being mirror-symmetric to the first drain electrode, A protective film stacked on the date line, the source electrode and the drain electrode, and having a contact hole for exposing the first and second drain electrodes; and A pixel electrode formed on the passivation layer and connected to the first and second drain electrodes through the contact hole; Thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, And a storage capacitor line formed on the substrate in parallel with the gate line. In claim 2, And the array of pixel regions defined by the two adjacent data lines and the two adjacent gate lines is a delta array. The method according to any one of claims 1 to 3, And a doped amorphous silicon layer formed between the first and second semiconductor pieces and the source electrode and the first and second drain electrodes. The method according to any one of claims 1 to 3, The thin film transistor substrate for a liquid crystal display device of which the first and second semiconductor pieces are made of polycrystalline silicon. The method according to any one of claims 1 to 3, The first and second gate electrodes are vertical branches of the gate line, the source electrode crosses the first and second semiconductor pieces, and the first and second drain electrodes are respectively the first and second A thin film transistor substrate for liquid crystal display, wherein a portion of the gate electrode overlaps.