JP2884723B2 - Thin film semiconductor device and method of manufacturing the same - Google Patents
Thin film semiconductor device and method of manufacturing the sameInfo
- Publication number
- JP2884723B2 JP2884723B2 JP2160672A JP16067290A JP2884723B2 JP 2884723 B2 JP2884723 B2 JP 2884723B2 JP 2160672 A JP2160672 A JP 2160672A JP 16067290 A JP16067290 A JP 16067290A JP 2884723 B2 JP2884723 B2 JP 2884723B2
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- Japan
- Prior art keywords
- semiconductor layer
- film
- conductivity type
- control electrode
- gate insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Thin Film Transistor (AREA)
- Liquid Crystal Display Device Control (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
〔概要〕 薄膜半導体装置およびその製造方法に関し、 Ｐチャネル型またはＮチャネル型に使い分けできる半
導体素子および相補型半導体素子を低コストで提供する
ことを目的とし、 一導電型半導体層と電極金属膜と逆導電型半導体層を
積層した構造の二つの被制御電極の、前記一導電型半導
体層同士および逆導電型半導体層同士を略真性半導体層
を介して接続し、且つ、前記略真性半導体層の上下に二
つの制御電極を対向配置した構成を具備してなることを
特徴とし、また、絶縁性基板上に第１の制御電極を形成
し、その上を被覆する第１のゲート絶縁膜を形成した
後、該第１のゲート絶縁膜の上に略真性半導体層を形成
し、該略真性半導体層上に前記第１の制御電極を両側か
ら挟むように一導電型半導体層と電極金属膜と逆導電半
導体層との積層膜からなる被制御電極を形成し、これら
被制御電極を含む基板上に再び略真性半導体層をを形成
し、前記第１の制御電極形成領域において該上層の真性
半導体層と先に形成した下層の略真性半導体層との積層
構造を形成し、該上層の略真性半導体層上に第２のゲー
ト絶縁膜を形成した後、その上の前記第１の制御電極の
真上部に第２の制御電極を形成する工程を含む構成とす
る。 〔産業上の利用分野〕 本発明は、Ｐチャネル型とＮチャネル型半導体素子の
双方が、同一基板上に混在する薄膜半導体装置およびそ
の製造方法に関する。 薄膜半導体装置例えば薄膜トランジスタは、アクティ
ブマトリクス型液晶表示装置やイメージセンサの駆動用
素子、あるいはSOI基板を用いた集積回路や三次元集積
回路などに、その用途は広がりつつある。 特に近年アクティブマトリクス型液晶表示装置では表
示容量の増大と高精細化が要求されており、周辺駆動回
路およびその接続部のコスト低減とコンパクト化を図る
ために、薄膜トランジスタによる周辺駆動回路をアクテ
ィブマトリクス回路と同一基板上に形成する駆動回路一
体型の表示装置の開発が進められており、Ｐチャネル
型,Nチャネル型のトランジスタならびに両方の特性のト
ランジスタを用いた、いわゆる相補型トランジスタも不
可欠となっている。 〔従来の技術〕 従来同一基板上にＰチャネル型,Nチャネル型および相
補型トランジスタが混在する複雑な半導体装置や回路基
板、例えば相補型（Ｃ−MOS）半導体装置を製造するた
めには、数回のマスク工程が必要である。 ここでＣ−MOSの構造および製造方法を第５図により
説明する。 まず、Ｎ型のSi基板51を熱酸化し、拡散のマスクとし
て使用するSiO2膜52を形成する。このSiO2膜52を、フォ
トマスクを用いて形成したレジスト膜（図示せず）をマ
スクとして上記SiO2膜のエッチングを行ない、Ｐ型不純
物拡散用の窓53をあける〔第５図（ａ）参照〕。 次いで、Ｐ型の不純物として例えばボロン（Ｂ）のデ
ポジション或いはイオン注入を行なった後、熱処理を施
してSi基板51表面に導入したボロンを拡散させ、Ｐ型領
域71を形成するとともに、Si基板51表面を酸化する〔同
図（ｂ）参照〕。なお、このＰ型領域71はＰウエルと呼
ばれ、Ｎチャネル素子の領域を画定する。 次いで、上記SiO2膜52に２番目のフォトマスクを用い
てＰチャネル素子のソースおよびドレイン領域形成用の
窓54を開口する〔同図（ｃ）参照〕。 次いで、ボロンのようなＰ型の不純物のデポジション
を行ない、熱拡散によりこれを拡散させてＰ型領域72を
形成し、同時にSi基板51表面の酸化を行なう〔同図
（ｄ）参照〕。 次いで、上記SiO2膜52に３番目のフォトマスクを用い
てＮチャネル素子のソースおよびドレイン領域形成用の
窓55をSiO2膜52に開口する〔同図（ｅ）参照〕。 次いで上記窓55を介してリン（Ｐ）のデポジションを
行ない、続いて熱処理をしてリンを拡散させてＮ型領域
73を形成し、同時にSi基板51表面を酸化する〔同図
（ｆ）参照〕。 次いで、４番目のフォトマスクを用いてゲート絶縁層
の膜厚制御のための窓56をSiO2膜52に開口する〔同図
（ｇ）参照〕。 次いで、熱処理によりゲート絶縁膜となるSiO2膜57を
形成する。その後ソース・ドレイン領域にコンタクトを
取るための窓58を、５番目のフォトマスクを用いて形成
する〔同図（ｈ）参照〕。 次いで、ゲート，ソース，ドレイン電極となる金属膜
として、アルミニウム（Al）を蒸着してAl膜を形成し、
６番目のフォトマスクを用いてこれの不要部を除去し、
ゲート電極G,ソース電極Ｓおよびドレイン電極Ｄを形成
する〔同図（ｉ）参照〕。 以上の工程を経てＣ−MOSが完成する。 〔発明が解決しようとする課題〕 このように従来の相補型の半導体装置の製造方法で
は、フォトマスクを使用してレジスト膜を形成する工程
が少なくとも６回必要であり、製造工程が非常に複雑で
あり、そのため、製造歩留りの向上および製造原価の低
減が困難であった。 このような複雑な製造工程を必要とするので、相補型
半導体装置はコスト高になることを免れ得ない。 本発明は、相補型半導体装置のように、Ｐチャネル型
およびＮチャネル型半導体素子の双方が同一基板上に存
在する、簡単な構造の薄膜半導体装置とその製造方法を
提供することを目的とする。 〔課題を解決するための手段〕 第１図は、本発明の半導体装置の構成例とその原理を
説明するための図である。 本発明は第１図に示すように、一導電型半導体層３と
電極金属膜４と逆導電型半導体層５を積層した構造の二
つの被制御電極P1,P2の、前記一導電型半導体層同士お
よび逆導電型半導体層同士を略真性半導体層７を介して
接続し、且つ、前記略真性半導体層の上下に二つの制御
電極G1,G2を対向配置した構成を具備してなることを特
徴とする。 上記一導電型半導体層３は例えばＮ型半導体層、逆導
電型半導体層５は例えばＰ型半導体層とする。 同図には、上記一導電型半導体層３同士および逆導電
型半導体層５同士が、一体化された略真性半導体層７に
より共通に接続された例を示す。 上記隣接する二つの被制御電極P1,P2は、動作時には
一方がソース電極，他方がドレイン電極として働く。 また本発明は第４図に示す如く、構造的に決定された
相補型半導体装置を構成することができる。 即ち、前記一導電型半導体層３と逆導電型半導体層５
との間に電極金属膜４を挟んだ構造の三つの被制御電極
P1,P2,P3のそれぞれの間を略真性半導体層７を介して接
続し、且つ、前記一方の略真性半導体層７の下側に第１
制御電極G1、他方の略真性半導体層７の上側に第２の制
御電極G2を設けてなる。 〔作用〕 上記の如く、一導電型をＮ型，逆導電型をＰ型とした
構成とし、第１のゲート電極G1および第２のゲート電極
G2に、それぞれ＋10V,0Vを印加した場合には、第１図
（ａ）に示す如く、略真性半導体層７の第１のゲート絶
縁膜２側に電子が蓄積（アキュムレート）され、チャネ
ルが形成される。従って、第１の被制御電極Ｐを接地
し、第２の被制御電極P2に正電圧を印加すると、被制御
電極P1から被制御電極P2に向かって電子が流れる。即
ち、Ｎチャネル型薄膜トランジスタとして動作する。 第１のゲート電極G1および第２のゲート電極G2に、そ
れぞれ0V,−10Vを印加した場合には、第１図（ｂ）に示
す如く、略真性半導体層７の第２のゲート絶縁膜６側に
ホールが蓄積（アキュムレート）され、チャネルが形成
される。従って、第１の被制御電極P1を接地し、第２の
被制御電極P2に正電圧を印加することにより、第２の被
制御電極P2から第１の被制御電極P1に向かってホールが
流れる。即ち、Ｐチャネル型薄膜トランジスタとして動
作する。また、第1,第２のゲート電極G1,G2のいずれも0
Vに設定した時は、略真性半導体層７には電子もホール
も蓄積されず、オフ状態を保つ。 このように本発明は第１図の構成とすることにより、
２つのゲート電極に印加する電圧を制御することによっ
て、Ｎチャネル型,Pチャネル型のいずれの動作も可能な
半導体装置が得られる。 また、三つの被制御電極を間に略真性半導体層を介し
て接続するとともに、各略真性半導体層の上側または下
側に相対的に１つずつ制御電極を設けることによって、
Ｎチャネル型とＰチャネル型半導体層とのペアからなる
相補型半導体装置を得ることができる。 また本発明では、Ｎチャネル型、Ｐチャネル型何れの
半導体素子も、同一の工程により形成されるため、フォ
トマスクの枚数および工程数を減らすことができ、従っ
て製造歩留りが向上し、また安価に製造が可能となる。 〔実施例〕 以下本発明の実施例を図面を参照して詳細に説明す
る。[Summary] A thin-film semiconductor device and a method of manufacturing the same are provided with a view to providing, at low cost, a semiconductor element and a complementary semiconductor element that can be selectively used as a P-channel type or an N-channel type. Of the two controlled electrodes having a structure in which the opposite conductivity type semiconductor layers are stacked, the one conductivity type semiconductor layers and the opposite conductivity type semiconductor layers are connected to each other via a substantially intrinsic semiconductor layer, and A first control electrode is formed on an insulating substrate, and a first gate insulating film covering the first control electrode is formed on the insulating substrate. After that, a substantially intrinsic semiconductor layer is formed on the first gate insulating film, and the one conductivity type semiconductor layer and the electrode metal film are formed on the substantially intrinsic semiconductor layer so as to sandwich the first control electrode from both sides. Reverse conductive semiconductor layer And a substantially intrinsic semiconductor layer is formed again on the substrate including the controlled electrodes, and is formed first with the upper intrinsic semiconductor layer in the first control electrode formation region. Forming a laminated structure with the lower substantially intrinsic semiconductor layer, forming a second gate insulating film on the upper substantially intrinsic semiconductor layer, and forming a second gate insulating film directly above the first control electrode thereon. Is formed. [Industrial Application Field] The present invention relates to a thin-film semiconductor device in which both a P-channel type and an N-channel type semiconductor element are mixed on the same substrate, and a method of manufacturing the same. The use of thin film semiconductor devices, for example, thin film transistors, is expanding to active matrix liquid crystal display devices, driving elements of image sensors, integrated circuits using SOI substrates, and three-dimensional integrated circuits. In particular, in recent years, an active matrix type liquid crystal display device has been required to have a higher display capacity and higher definition. The development of a display device integrated with a drive circuit formed on the same substrate as the above is underway, and so-called complementary transistors using P-channel and N-channel transistors and transistors with both characteristics have become indispensable. I have. 2. Description of the Related Art Conventionally, a complicated semiconductor device or a circuit substrate on which a P-channel type, an N-channel type and a complementary transistor are mixed on the same substrate, for example, a complementary (C-MOS) semiconductor device, requires a number of steps. Two mask steps are required. Here, the structure and manufacturing method of the C-MOS will be described with reference to FIG. First, an N-type Si substrate 51 is thermally oxidized to form an SiO 2 film 52 used as a diffusion mask. The SiO 2 film 52, etching is performed for the SiO 2 film resist film formed by using a photomask (not shown) as a mask, open the window 53 of the P-type impurity diffusion Fifth diagram (a) reference〕. Next, for example, boron (B) is deposited or ion-implanted as a P-type impurity, and then heat treatment is performed to diffuse the boron introduced into the surface of the Si substrate 51 to form a P-type region 71 and form the Si substrate. The surface 51 is oxidized [see FIG. The P-type region 71 is called a P-well and defines an N-channel device region. Next, a window 54 for forming the source and drain regions of the P-channel element is opened in the SiO 2 film 52 by using a second photomask [see FIG. Next, a P-type impurity such as boron is deposited and diffused by thermal diffusion to form a P-type region 72, and at the same time, the surface of the Si substrate 51 is oxidized (see FIG. 3D). Then, to open the window 55 for the source and drain regions formed of N-channel device in the SiO 2 film 52 by using the third photomask to the SiO 2 film 52 [Fig. (E) refer to Fig. Next, phosphorus (P) is deposited through the window 55, and then heat treatment is performed to diffuse phosphorus to form an N-type region.
73 is formed, and at the same time, the surface of the Si substrate 51 is oxidized [see FIG. Next, a window 56 for controlling the thickness of the gate insulating layer is opened in the SiO 2 film 52 using a fourth photomask [see FIG. Next, an SiO 2 film 57 to be a gate insulating film is formed by heat treatment. Thereafter, a window 58 for making contact with the source / drain region is formed using a fifth photomask [see FIG. Next, aluminum (Al) is deposited as a metal film to be the gate, source, and drain electrodes to form an Al film,
Use a sixth photomask to remove this unnecessary part,
A gate electrode G, a source electrode S, and a drain electrode D are formed [see FIG. Through the above steps, the C-MOS is completed. [Problems to be Solved by the Invention] As described above, in the conventional method of manufacturing a complementary semiconductor device, the step of forming a resist film using a photomask is required at least six times, which is extremely complicated. Therefore, it has been difficult to improve the production yield and reduce the production cost. Since such a complicated manufacturing process is required, the cost of the complementary semiconductor device cannot be avoided. An object of the present invention is to provide a thin-film semiconductor device having a simple structure in which both a P-channel type and an N-channel type semiconductor element are present on the same substrate as a complementary semiconductor device, and a method of manufacturing the same. . [Means for Solving the Problems] FIG. 1 is a diagram for explaining a configuration example of a semiconductor device of the present invention and its principle. As shown in FIG. 1, the present invention relates to the one-conductivity-type semiconductor layer of two controlled electrodes P1 and P2 having a structure in which one-conductivity-type semiconductor layer 3, electrode metal film 4, and opposite-conductivity-type semiconductor layer 5 are laminated. And the opposite conductivity type semiconductor layers are connected to each other through the substantially intrinsic semiconductor layer 7, and two control electrodes G1 and G2 are opposed to each other above and below the substantially intrinsic semiconductor layer. And The one conductivity type semiconductor layer 3 is, for example, an N-type semiconductor layer, and the opposite conductivity type semiconductor layer 5 is, for example, a P-type semiconductor layer. FIG. 1 shows an example in which the one-conductivity-type semiconductor layers 3 and the opposite-conductivity-type semiconductor layers 5 are commonly connected by an integrated substantially intrinsic semiconductor layer 7. One of the two adjacent controlled electrodes P1 and P2 functions as a source electrode and the other as a drain electrode during operation. Further, as shown in FIG. 4, the present invention can constitute a structurally determined complementary semiconductor device. That is, the one conductivity type semiconductor layer 3 and the opposite conductivity type semiconductor layer 5
Three controlled electrodes having a structure in which an electrode metal film 4 is sandwiched between
Each of P1, P2, and P3 is connected through a substantially intrinsic semiconductor layer 7, and a first underneath the one substantially intrinsic semiconductor layer 7.
A second control electrode G2 is provided above the control electrode G1 and the other substantially intrinsic semiconductor layer 7. [Operation] As described above, one conductivity type is N-type and the opposite conductivity type is P-type, and the first gate electrode G1 and the second gate electrode
When +10 V and 0 V are applied to G2, respectively, as shown in FIG. 1A, electrons are accumulated (accumulated) on the first gate insulating film 2 side of the substantially intrinsic semiconductor layer 7 and the channel is formed. It is formed. Therefore, when the first controlled electrode P is grounded and a positive voltage is applied to the second controlled electrode P2, electrons flow from the controlled electrode P1 toward the controlled electrode P2. That is, it operates as an N-channel thin film transistor. When 0V and -10V are applied to the first gate electrode G1 and the second gate electrode G2, respectively, as shown in FIG. 1B, the second gate insulating film 6 of the substantially intrinsic semiconductor layer 7 is formed. Holes accumulate (accumulate) on the side, forming a channel. Accordingly, by grounding the first controlled electrode P1 and applying a positive voltage to the second controlled electrode P2, a hole flows from the second controlled electrode P2 toward the first controlled electrode P1. . That is, it operates as a P-channel thin film transistor. Further, both the first and second gate electrodes G1 and G2 are set to 0.
When the voltage is set to V, neither electrons nor holes are accumulated in the substantially intrinsic semiconductor layer 7 and the off state is maintained. As described above, the present invention has the configuration shown in FIG.
By controlling the voltages applied to the two gate electrodes, a semiconductor device capable of operating in either an N-channel type or a P-channel type is obtained. In addition, by connecting the three controlled electrodes through a substantially intrinsic semiconductor layer therebetween, and providing one control electrode relatively above or below each substantially intrinsic semiconductor layer,
A complementary semiconductor device including a pair of N-channel and P-channel semiconductor layers can be obtained. In the present invention, both the N-channel type and the P-channel type semiconductor elements are formed in the same step, so that the number of photomasks and the number of steps can be reduced, so that the manufacturing yield is improved and the cost is reduced. Manufacturing becomes possible. Embodiment An embodiment of the present invention will be described below in detail with reference to the drawings.
【本発明の第１の実施例の説明】 まず、第２図により、Ｐチャネル型とＮチャネル型に
使い分けできる薄膜トランジスタの構成を、その製造方
法とともに説明する。DESCRIPTION OF THE FIRST EXAMPLE OF THE PRESENT INVENTION First, referring to FIG. 2, a structure of a thin film transistor that can be selectively used for a P-channel type and an N-channel type will be described together with a manufacturing method thereof.
【第２図（ａ）参照】 石英基板のような絶縁性基板１上に、例えば高濃度に
リン（Ｐ）をドープしたN+型のポリシリコンを、例えば
LPCVD法により100nmの厚さに成膜し、これの不要部を第
１のレジスト膜（図示せず）をマスクとして除去し、第
１のゲート電極G1を形成する。[See FIG. 2 (a)] On an insulating substrate 1 such as a quartz substrate, for example, N + type polysilicon doped with a high concentration of phosphorus (P) is formed, for example.
A film is formed to a thickness of 100 nm by the LPCVD method, and unnecessary portions thereof are removed using a first resist film (not shown) as a mask to form a first gate electrode G1.
次いで、例えばLPCVD法により、SiO2膜のような第１
のゲート絶縁膜２を約300nmの厚さに、ノンドープのポ
リシリコンからなる下層の略真性半導体層（図のＩ型半
導体層）71を約100nmの厚さに、不純物としてリン
（Ｐ）をドープしたＮ型ポリシリコンからなるＮ型半導
体層３を約50nmの厚さに、続いて例えばスパッタ法を用
いて例えばタングステンシリサイド（SWi）からなる電
極金属膜４を約50nmの厚さに、不純物としてボロン
（Ｂ）をドープしたポリシリコンからなるＰ型半導体層
５を約50nmの厚さに連続形成する。 次いで、約２のレジスト膜（図示せず）をマスクとし
て、上記Ｐ型半導体層5,電極金属膜4,N型半導体層３の
不要部を除去し、所定の形状にパターニングされた第１
および第２の被制御電極P1,P2を形成する。Next, a first film such as a SiO 2 film is formed by, eg, LPCVD.
The gate insulating film 2 has a thickness of about 300 nm, the lower substantially intrinsic semiconductor layer (I-type semiconductor layer) 71 of non-doped polysilicon has a thickness of about 100 nm, and phosphorus (P) is doped as an impurity. The N-type semiconductor layer 3 made of N-type polysilicon thus formed has a thickness of about 50 nm, and the electrode metal film 4 made of, for example, tungsten silicide (SWi) is then formed to a thickness of about 50 nm by using, for example, a sputtering method. A P-type semiconductor layer 5 made of polysilicon doped with boron (B) is continuously formed to a thickness of about 50 nm. Then, using about two resist films (not shown) as masks, unnecessary portions of the P-type semiconductor layer 5, the electrode metal film 4, and the N-type semiconductor layer 3 are removed, and the first part patterned into a predetermined shape is formed.
And the second controlled electrodes P1 and P2 are formed.
次いで、LPCVD法でノンドープのポリシリコンからな
る上層の略真性半導体層72を約100nmの厚さに、SiO2膜
のような絶縁膜からなる第２のゲート絶縁膜６を約300n
mの厚さに、続いて、例えばLPCVD法を用いて高濃度にリ
ンをドープした、Ｎ型のポリシリコンからなる第２のゲ
ート電極G2を約100nmの厚さに形成する。 上記第２のゲート電極G2は、第３のレジスト膜（図示
せず）をマスクとして所定の形状にパターニングする。Next, the upper substantially intrinsic semiconductor layer 72 made of non-doped polysilicon is made to have a thickness of about 100 nm by LPCVD, and the second gate insulating film 6 made of an insulating film such as a SiO 2 film is made about 300 nm thick.
Subsequently, a second gate electrode G2 made of N-type polysilicon doped with phosphorus at a high concentration by using, for example, the LPCVD method to a thickness of about 100 nm is formed. The second gate electrode G2 is patterned into a predetermined shape using a third resist film (not shown) as a mask.
以上述べた如く本実施例ではレジスト膜を使用する工
程は３回のみで全工程を終了し、Ｎチャネル型,Pチャネ
ル型いずれの動作も可能な半導体装置が構成される。 なお、上記上層，下層の略真性半導体層71および72は
一体化されて、略真性半導体層７を形成し、そのうち、
梨地で示した領域がチャネルを形成する領域である。こ
の領域と第１のゲート絶縁膜２または第２のゲート絶縁
膜６との界面に、外部から印加した第１および第２のゲ
ート電極の電圧によって電子またはホールが蓄積（アキ
ュムレート）され、チャネルが形成される。 なお、上下に対向するＰ型半導体層５とＮ型半導体層
３とを、上記実施例とは逆関係、即ち、下側をＰ型半導
体層，上側をＮ型半導体層とすることも可能である。As described above, in this embodiment, the process using the resist film is completed only three times, and the entire process is completed, and a semiconductor device capable of operating in either the N-channel type or the P-channel type is configured. The upper and lower substantially intrinsic semiconductor layers 71 and 72 are integrated to form a substantially intrinsic semiconductor layer 7, of which
The region indicated by satin is a region where a channel is formed. Electrons or holes are accumulated (accumulated) by an externally applied voltage of the first and second gate electrodes at the interface between this region and the first gate insulating film 2 or the second gate insulating film 6, and the channel Is formed. Note that the P-type semiconductor layer 5 and the N-type semiconductor layer 3 that are vertically opposed to each other may be in an inverse relationship to the above-described embodiment, that is, the lower side may be a P-type semiconductor layer and the upper side may be an N-type semiconductor layer. is there.
【本発明の第２の実施例の説明】 次に第３図により、同じくＰチャネル型,Nチャネル型
に使い分けできる薄膜トランジスタの変形構造を、その
製造方法とともに説明する。Description of Second Embodiment of the Present Invention Next, referring to FIG. 3, a description will be given of a modified structure of a thin film transistor which can be selectively used for a P-channel type and an N-channel type, together with a manufacturing method thereof.
【第３図（ａ）参照】 石英基板のような絶縁性基板１上に、例えば高濃度に
リン（Ｐ）をドープしたN+型のポリシリコンを、例えば
LPCVD法により約100nmの厚さに形成し、第１のレジスト
膜（図示せず）をマスクとして所定の形状にパターニン
グを行い、第１のゲート電極G1を形成する。[See FIG. 3 (a)] On an insulating substrate 1 such as a quartz substrate, for example, N + -type polysilicon doped with a high concentration of phosphorus (P) is formed, for example.
It is formed to a thickness of about 100 nm by the LPCVD method, and is patterned into a predetermined shape using a first resist film (not shown) as a mask to form a first gate electrode G1.
次いで、例えばLPCVD法によりSiO2膜のような絶縁膜
からなる第１のゲート絶縁膜２を約300nmの厚さに、そ
の上に不純物としてリン（Ｐ）をドープしたＮ型のポリ
シリコンからなるＮ型半導体層３を約90nmの厚さに形成
する。 続いて例えばスパッタ法を用いてタングステンシリサ
イド（SWi）のような電極金属膜４を約100nmの厚さに形
成し、これを第２のレジスト膜（図示せず）をマスクと
して所定の形状にパターニングを行い、第1,第２の被制
御電極P1,P2を形成する。Next, for example, the first gate insulating film 2 made of an insulating film such as a SiO 2 film is formed to a thickness of about 300 nm by LPCVD and made of N-type polysilicon doped with phosphorus (P) as an impurity thereon. An N-type semiconductor layer 3 is formed to a thickness of about 90 nm. Subsequently, an electrode metal film 4 such as tungsten silicide (SWi) is formed to a thickness of about 100 nm by using, for example, a sputtering method, and is patterned into a predetermined shape using a second resist film (not shown) as a mask. To form first and second controlled electrodes P1 and P2.
次いで、例えばLPCVD法で不純物としてボロン（Ｂ）
をドープしたポリシリコンからなるＰ型半導体層５を約
90nmの厚さに、その上に、SiO2のような絶縁膜からなる
第２のゲート絶縁膜６を約300nmの厚さに形成する。続
いて例えばLPCVD法を用いて高濃度にリン（Ｐ）をドー
プしたポリシリコンからなるN+型半導体層を約100nmの
厚さに成膜し、これを第３のレジスト膜（図示せず）を
マスクとして所定の形状にパターニングを行い、第２の
ゲート電極G2を形成する。Then, for example, boron (B) is used as an impurity by LPCVD.
P-type semiconductor layer 5 made of polysilicon doped with
A second gate insulating film 6 made of an insulating film such as SiO 2 is formed to a thickness of about 300 nm on the thickness of 90 nm. Subsequently, an N + type semiconductor layer made of polysilicon doped with phosphorus (P) at a high concentration is formed to a thickness of about 100 nm by using, for example, an LPCVD method, and this is formed as a third resist film (not shown). Is used as a mask to pattern into a predetermined shape to form a second gate electrode G2.
次いで、約900℃で１時間アニールを行なって、リン
（Ｐ）およびボロン（Ｂ）を熱拡散することにより、上
記Ｎ型半導体層３とＰ型半導体層５の互いに接触する領
域（図に梨地で示す）の不純物が相互に補償しあい、略
真性半導体層７を形成する。 この領域以外では、電極金属膜４と、その下層のＮ型
半導体層３および上層のＰ型半導体層５により、第１お
よび第２の被制御電極P1,P2を形成する。 本実施例においても、同一導電型半導体層同士は、略
真性半導体層７によって接続されている。但し、Ｎ型半
導体層３同士,P型半導体層５同士を接続する略真性半導
体層７が一体化されたものである点は、前記一実施例と
同様である。 また本実施例においても、レジスト膜を３回用いるの
みで全ての工程を終了し、Ｎチャネル型,Pチャネル型の
いずれの動作も可能な半導体装置が得られる。 なお、本実施例ではＮ型半導体層３とＰ型半導体層５
に含まれる不純物を、熱拡散により相互に拡散させて略
真性半導体層７を形成したが、Ｎ型およびＰ型半導体層
3,5の不純物濃度および厚さを選択することにより、内
部の不純物を相互拡散させなくても、Ｎ型領域とＰ型領
域が接触することにより空乏層が形成されるのを利用し
て、実効的に略真性半導体層を構成することも可能であ
る。 上記一実施例および他の実施例では、素子を１個のみ
図示したが、絶縁性基板１上全面に、ゲート電極形成領
域と被制御電極形成領域を交互に配置して、多数の素子
を連続的に形成しておき、電極間の配線と各電極に印加
する電圧の極性を選択することにより、種々の回路を構
成できることは特に説明するまでもない。 その場合、略真性半導体層を挾んで上下に対向配置し
た２つのゲート電極と、このゲート電極を真ん中に挟む
位置にある２つの被制御電極とを組にするとともに、そ
れら電極に印加する電圧を選択することによって、Ｎチ
ャネル型またはＰチャネル型半導体素子を同一基板上に
複数個混在させることができる。 なお、同一基板上に形成した多数の素子を、隣接する
２つの素子をペアとし、その一方をＮチャネル型，他方
をＰチャネル型として動作させた場合には、相補型薄膜
半導体装置（Ｃ−MOS）として動作させることがてき
る。Then, annealing is performed at about 900 ° C. for 1 hour, and phosphorus (P) and boron (B) are thermally diffused to thereby bring the N-type semiconductor layer 3 and the P-type semiconductor layer 5 into contact with each other (in FIG. ) Compensate each other to form a substantially intrinsic semiconductor layer 7. Except for this region, the first and second controlled electrodes P1 and P2 are formed by the electrode metal film 4, the lower N-type semiconductor layer 3 and the upper P-type semiconductor layer 5. Also in the present embodiment, the same conductivity type semiconductor layers are connected by the substantially intrinsic semiconductor layer 7. However, the point that the substantially intrinsic semiconductor layer 7 for connecting the N-type semiconductor layers 3 and the P-type semiconductor layers 5 is integrated is the same as in the above-described embodiment. Also in the present embodiment, all steps are completed only by using the resist film three times, and a semiconductor device capable of performing either an N-channel type or a P-channel type operation is obtained. In this embodiment, the N-type semiconductor layer 3 and the P-type semiconductor layer 5
Impurities are mutually diffused by thermal diffusion to form the substantially intrinsic semiconductor layer 7, but the N-type and P-type semiconductor layers
By selecting the impurity concentration and the thickness of 3,5, the depletion layer is formed by the contact between the N-type region and the P-type region without interdiffusion of the internal impurities. It is also possible to effectively constitute a substantially intrinsic semiconductor layer. In the above embodiment and the other embodiments, only one device is shown. However, the gate electrode formation region and the controlled electrode formation region are alternately arranged on the entire surface of the insulating substrate 1 to connect a large number of devices continuously. It is needless to say that various circuits can be formed by selecting the wiring between the electrodes and the polarity of the voltage applied to each electrode. In this case, a pair of two gate electrodes, which are disposed vertically opposite to each other with the substantially intrinsic semiconductor layer interposed therebetween, and two controlled electrodes located at a position sandwiching the gate electrode in the middle, are set, and the voltage applied to these electrodes is reduced. By selection, a plurality of N-channel or P-channel semiconductor elements can be mixed on the same substrate. When a number of elements formed on the same substrate are paired with two adjacent elements, one of which is operated as an N-channel type and the other is operated as a P-channel type, a complementary thin film semiconductor device (C- MOS).
【本発明の第３の実施例の説明】 上記２つの実施例では、いずれも第1,第２のゲート電
極G1,G2に印加する電圧により、Ｎチャネル型とＰチャ
ネル型動作を任意に選択できる構成を説明した。 本発明は更に構造的に相補型半導体装置を構成するこ
とができる。次にその例を説明する。 第４図に示す如く、同一基板上に３つの被制御電極P
1,P2,P3を配置し、隣接配置された２つの被制御電極間
を、それぞれ略真性半導体層７で接続する。 この構成は上記２つの実施例と同様でよい。つまり第
４図には略真性半導体層７を、上記第３図と同じ構造と
した例を描いてあるが、第２図と同一構造としてもよ
い。 本実施例では、上記略真性半導体層７の上下に第１お
よび第２のゲート電極を対向配置するのに変えて、被制
御電極P1,P2間には略真性半導体層７の下側に第１のゲ
ート電極G1を配置し、被制御電極P2,P3間には略真性半
導体層７の上側に第２のゲート電極G2を配置した。 この構成とした場合には、上記一導電型および逆導電
型をそれぞれＮ型およびＰ型とすると、図の左側の素子
はＮチャネル型、右側の素子はＰチャネル型となり、Ｎ
チャネル型とＰチャネル型が構造的に定まった相補型薄
膜半導体装置が得られる。 本実施例の製造に際しては、前述の第２図および第３
図の実施例と、一部マスクパターンを変更するのみでよ
く、必要なフォトマスクの枚数および工程数は同じであ
る。 なお、本実施例では各素子に第１のゲート電極G1また
は第２ゲート電極G2の一方のみを配置したが、図に点線
で示す如く第１および第２のゲート電極G1′,G2′を設
け、すべての素子にゲート電極を対向配置しても差し支
えない。 その場合には、前記第１および第２の実施例の素子を
連続配置したものとなる。 以上の実施例では、半導体層にはポリシリコンを用い
たが、半導体材料であれば、単結晶であっても微結晶で
あっても良く、また非結晶であっても良いのは言うまで
もない。また、一導電型および逆導電型半導体層を不純
物濃度の異なる２層以上の構造、もしくは、傾斜をもっ
て濃度を変化させた構造としてもよい。更に、絶縁層，
電極等の材質，成膜方法についても、特に限定する必要
はない。 〔発明の効果〕 以上説明した如く本発明によれば、Ｎ型,P型何れのTF
Tも同一の工程により形成されるため、一つの素子をＮ
チャネル型,Pチャネル型に使い分けできる半導体装置お
よび構造的に決定した相補型半導体装置のいずれも、安
価に提供できる。従って、アクティブマトリクス型液晶
表面装置，イメージセンサ,SOI集積回路等に適用して極
めて大きな効果を奏することが可能である。[Explanation of Third Embodiment of the Present Invention] In each of the above two embodiments, the N-channel type operation and the P-channel type operation are arbitrarily selected by the voltage applied to the first and second gate electrodes G1 and G2. A possible configuration has been described. The present invention can further structurally configure a complementary semiconductor device. Next, an example thereof will be described. As shown in FIG. 4, three controlled electrodes P on the same substrate
1, P2 and P3 are arranged, and two controlled electrodes arranged adjacent to each other are connected by a substantially intrinsic semiconductor layer 7, respectively. This configuration may be similar to the above two embodiments. That is, FIG. 4 illustrates an example in which the substantially intrinsic semiconductor layer 7 has the same structure as that in FIG. 3, but may have the same structure as in FIG. In the present embodiment, the first and second gate electrodes are opposed to each other above and below the substantially intrinsic semiconductor layer 7, and the first and second gate electrodes are disposed below the substantially intrinsic semiconductor layer 7 between the controlled electrodes P 1 and P 2. One gate electrode G1 was disposed, and a second gate electrode G2 was disposed substantially above the intrinsic semiconductor layer 7 between the controlled electrodes P2 and P3. In this configuration, assuming that the one conductivity type and the opposite conductivity type are N-type and P-type, respectively, the element on the left side of the drawing is an N-channel type, and the element on the right side is a P-channel type.
A complementary thin film semiconductor device in which the channel type and the P channel type are structurally determined is obtained. In manufacturing the present embodiment, the above-described FIG. 2 and FIG.
Only a part of the mask pattern needs to be changed, and the required number of photomasks and the number of steps are the same as those in the embodiment of the figure. In this embodiment, only one of the first gate electrode G1 and the second gate electrode G2 is arranged in each element, but the first and second gate electrodes G1 'and G2' are provided as shown by dotted lines in FIG. Alternatively, the gate electrodes may be arranged to face all the elements. In that case, the elements of the first and second embodiments are arranged continuously. In the above embodiments, polysilicon is used for the semiconductor layer. However, it goes without saying that any semiconductor material may be single crystal, microcrystal, or amorphous. Further, the semiconductor layers of the one conductivity type and the opposite conductivity type may have a structure of two or more layers having different impurity concentrations, or a structure in which the concentrations are changed with a gradient. Furthermore, an insulating layer,
The material of the electrodes and the like and the film formation method need not be particularly limited. [Effects of the Invention] As described above, according to the present invention, any of N-type and P-type TF
Since T is also formed by the same process, one element is
Both a semiconductor device that can be selectively used as a channel type and a P-channel type and a complementary semiconductor device that is structurally determined can be provided at low cost. Therefore, the present invention can be applied to an active matrix type liquid crystal surface device, an image sensor, an SOI integrated circuit, and the like, and can provide an extremely large effect.
第１図は本発明の構成および原理説明図、 第２図は本発明の第１の実施例説明図、 第３図は本発明の第２の実施例説明図、 第４図は本発明の第３の実施例説明図、 第５図は従来のＣ−MOSの構造および製造方法説明図で
ある。 図において、１は絶縁性基板、２は第１のゲート絶縁
膜、３は一導電型（Ｎ型）半導体層、４は電極金属膜、
５は逆導電型（Ｐ型）半導体層、６は第２のゲート絶縁
膜、７は略真性半導体層、８はチャネル領域、G1および
G2は第１および第２のゲート電極、P1およびP2は第１お
よび第２の被制御電極を示す。FIG. 1 is a diagram illustrating the configuration and principle of the present invention, FIG. 2 is a diagram illustrating a first embodiment of the present invention, FIG. 3 is a diagram illustrating a second embodiment of the present invention, and FIG. FIG. 5 is an explanatory view of a third embodiment, and FIG. 5 is an explanatory view of a structure and a manufacturing method of a conventional C-MOS. In the figure, 1 is an insulating substrate, 2 is a first gate insulating film, 3 is a one conductivity type (N-type) semiconductor layer, 4 is an electrode metal film,
5 is a reverse conductivity type (P-type) semiconductor layer, 6 is a second gate insulating film, 7 is a substantially intrinsic semiconductor layer, 8 is a channel region, and G1 and
G2 indicates first and second gate electrodes, and P1 and P2 indicate first and second controlled electrodes.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 松本 友孝 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 29/786 H01L 27/092 H01L 21/8238 H01L 21/336 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tomotaka Matsumoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Within Fujitsu Limited (58) Field surveyed (Int.Cl. 6 , DB name) H01L 29/786 H01L 27 / 092 H01L 21/8238 H01L 21/336
Claims (8)
（４）と逆導電型半導体層（５）を積層した構造の二つ
の被制御電極（P1,P2）の、前記一導電型半導体層同士
および逆導電型半導体層同士をそれぞれ略真正半導体層
（7,71,72）を介して接続し、且つ、前記略真正半導体
層の上下に二つの制御電極（G1,G2）を対向配置した構
成を具備してなることを特徴とする薄膜半導体装置。1. One of the two controlled electrodes (P1, P2) having a structure in which a semiconductor layer (3) of one conductivity type, an electrode metal film (4) and a semiconductor layer (5) of opposite conductivity type are laminated. The semiconductor layers and the opposite conductivity type semiconductor layers are connected through substantially genuine semiconductor layers (7, 71, 72), respectively, and two control electrodes (G1, G2) are opposed above and below the substantially genuine semiconductor layers. A thin-film semiconductor device having a configuration in which the components are arranged.
における一導電型半導体層（３）同士を接続する下層の
略真正半導体層（71）および逆導電型半導体層（５）同
士を接続する上層の略真正半導体層（72）が、一体化さ
れてなることを特徴とする請求項１記載の薄膜半導体装
置。2. The two adjacent controlled electrodes (P1, P2).
The lower substantially genuine semiconductor layer (71) connecting the one conductivity type semiconductor layers (3) and the upper substantially genuine semiconductor layer (72) connecting the opposite conductivity type semiconductor layers (5) are integrated with each other. 2. The thin film semiconductor device according to claim 1, wherein:
層（５）との間に電極金属膜（４）を挟んだ構造の三つ
の被制御電極（P1,P2,P3）のそれぞれの間を略真正半導
体層（７）を介して接続し、且つ、一方の略真正半導体
層の下側に第１制御電極（G1）、他方の略真正半導体層
の上側に第２制御電極（G2）を設けてなることを特徴と
する薄膜半導体装置。3. The three controlled electrodes (P1, P2, P3) having a structure in which an electrode metal film (4) is sandwiched between a semiconductor layer of one conductivity type (3) and a semiconductor layer of opposite conductivity type (5). Each of them is connected via a substantially genuine semiconductor layer (7), and a first control electrode (G1) is provided below one substantially genuine semiconductor layer, and a second control electrode is provided above the other substantially genuine semiconductor layer. (G2) A thin film semiconductor device characterized by comprising:
導体層（７）中に埋設してなることを特徴とする請求項
１または３記載の薄膜半導体装置。4. The thin film semiconductor device according to claim 1, wherein said controlled electrodes (P1, P2) are buried in said substantially genuine semiconductor layer (7).
に、略真正半導体層（７）を設けてなることを特徴とす
る請求項１または３記載の薄膜半導体装置。5. The thin-film semiconductor device according to claim 1, wherein an approximately genuine semiconductor layer is provided between two adjacent controlled electrodes (P1, P2).
第１および第２のゲート絶縁膜（2,6）と、その外側に
接する第１および第２の制御電極（G1,G2）を有し、 該第１および第２の制御電極に印加する電圧を制御する
ことにより、Ｎチャネル型およびＰチャネル型動作のい
ずれも選択可能としたことを特徴とする請求項１記載の
薄膜半導体装置。6. A first and second gate insulating film (2, 6) contacting above and below said substantially genuine semiconductor layer (7), and first and second control electrodes (G1, G2) contacting outside thereof. 2. The thin-film semiconductor according to claim 1, wherein a voltage applied to the first and second control electrodes is controlled to select either an N-channel type operation or a P-channel type operation. apparatus.
1）を形成し、その上を被覆する第１のゲート絶縁膜
（２）を形成した後、 該第１のゲート絶縁膜の上に略真正半導体層（71）を形
成し、 該略真正半導体層上に前記第１の制御電極を両側から挟
むように一導電型半導体層（３）と電極金属膜（４）と
逆導電型半導体層（５）との積層膜からなる被制御電極
（P1,P2）を形成し、 これら被制御電極を含む基板上に再び略真正半導体層
（72）を形成し、前記第１の制御電極形成領域において
該上層の略真正半導体層と先に形成した下層の略真正半
導体層との積層構造を形成し、 該上層の略真正半導体層（72）上に第２のゲート絶縁膜
（６）を形成した後、その上の前記第１の制御電極（G
1）の真上部に第２の制御電極（G2）を形成する 工程を含むことを特徴とする薄膜半導体装置の製造方
法。7. A first control electrode (G) on an insulating substrate (1).
1) is formed, a first gate insulating film (2) covering the first gate insulating film (2) is formed, and a substantially genuine semiconductor layer (71) is formed on the first gate insulating film. A control electrode (P1) formed of a laminated film of a semiconductor layer of one conductivity type (3), an electrode metal film (4) and a semiconductor layer of opposite conductivity type (5) so as to sandwich the first control electrode from both sides on the layer. , P2), a substantially genuine semiconductor layer (72) is formed again on the substrate including these controlled electrodes, and the upper genuine semiconductor layer and the lower layer formed earlier are formed in the first control electrode formation region. And a second gate insulating film (6) is formed on the upper substantially genuine semiconductor layer (72), and then the first control electrode (G) is formed thereon.
Forming a second control electrode (G2) directly above 1).
1）を形成し、その上を被覆する第１のゲート絶縁膜
（２）を形成した後、 該第１のゲート絶縁膜上に一導電型半導体層（３）を形
成し、その上に前記第１の制御電極を両側から挟むよう
に２つの電極金属膜（４）を形成し、 これら電極金属膜を含む一導電型半導体層上に逆導電型
半導体層（５）を形成して、一導電型半導体層と電極金
属膜と逆導電型半導体層との積層構造により二つの被制
御電極（P1,P2）を形成し、 前記第１の制御電極形成領域において上下に接する逆導
電型半導体層と一導電型半導体層に対して、それら半導
体層中の不純物を相互に拡散させるための加熱処理を施
して、当該領域を略真正半導体層（７）に形成し、 前記逆導電型半導体層の上に第２のゲート絶縁膜（６）
を形成した後、その上の前記第１の制御電極（G1）の真
上部に第２の制御電極（G2）を形成する 工程を含むことを特徴とする薄膜半導体装置の製造方
法。8. A first control electrode (G) on an insulating substrate (1).
1) is formed, a first gate insulating film (2) covering the first gate insulating film (2) is formed, and a one conductivity type semiconductor layer (3) is formed on the first gate insulating film. Two electrode metal films (4) are formed so as to sandwich the first control electrode from both sides, and a reverse conductivity type semiconductor layer (5) is formed on one conductivity type semiconductor layer including these electrode metal films. Two controlled electrodes (P1, P2) are formed by a laminated structure of a conductive type semiconductor layer, an electrode metal film, and a reverse conductive type semiconductor layer, and a reverse conductive type semiconductor layer vertically contacting in the first control electrode formation region And the one conductivity type semiconductor layer is subjected to a heat treatment for mutually diffusing impurities in the semiconductor layers to form the region substantially in the genuine semiconductor layer (7). A second gate insulating film (6) thereon
Forming a second control electrode (G2) directly above the first control electrode (G1) on the thin film semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160672A JP2884723B2 (en) | 1990-06-18 | 1990-06-18 | Thin film semiconductor device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2160672A JP2884723B2 (en) | 1990-06-18 | 1990-06-18 | Thin film semiconductor device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0449665A JPH0449665A (en) | 1992-02-19 |
| JP2884723B2 true JP2884723B2 (en) | 1999-04-19 |
Family
ID=15719987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2160672A Expired - Lifetime JP2884723B2 (en) | 1990-06-18 | 1990-06-18 | Thin film semiconductor device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2884723B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG176316A1 (en) | 2001-12-05 | 2011-12-29 | Semiconductor Energy Lab | Organic semiconductor element |
| EP1367659B1 (en) * | 2002-05-21 | 2012-09-05 | Semiconductor Energy Laboratory Co., Ltd. | Organic field effect transistor |
| JP2005223048A (en) * | 2004-02-04 | 2005-08-18 | Ricoh Co Ltd | Semiconductor device, its fabrication process, and display |
| TWI248681B (en) * | 2004-03-29 | 2006-02-01 | Imec Inter Uni Micro Electr | Method for fabricating self-aligned source and drain contacts in a double gate FET with controlled manufacturing of a thin Si or non-Si channel |
| JP5041267B2 (en) * | 2005-01-20 | 2012-10-03 | 富士電機株式会社 | Thin film field effect transistor and method for manufacturing the same |
| JP4586573B2 (en) * | 2005-02-28 | 2010-11-24 | エプソンイメージングデバイス株式会社 | Electro-optical device and manufacturing method thereof, thin film transistor, electronic device |
-
1990
- 1990-06-18 JP JP2160672A patent/JP2884723B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0449665A (en) | 1992-02-19 |
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