JP5807352B2 - Manufacturing method of semiconductor device and manufacturing method of electro-optical device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing an electro-optical device.

In recent years, electro-optical devices, such as liquid crystal projectors, direct-view display devices, and organic EL devices, which control light transmittance and light emission intensity have been widely used. Conventionally, a signal processing board has been added to separately process information processing and light control. However, for cost and wiring reasons, information processing and light control are collectively performed on the light control board 1. Sheet processing methods have been developed.
When information processing and light control are collectively performed on one light control substrate, it is necessary to form TFTs having different characteristics. For example, in order to perform information processing, the first TFT with high LDD concentration that operates at high speed, and the amount of accumulated charge (which determines the potential that determines the brightness of the pixel) as much as possible during the light control period are avoided. Therefore, a second TFT having a low LDD concentration and a small leakage current is required as compared with the portion that performs information processing. As described above, for example, Patent Document 1 is known as a technique for performing TFTs having a plurality of characteristics with one light control substrate.
Also disclosed is a technique for forming a resist film having a plurality of levels of film thickness using a halftone mask and manufacturing TFTs having different impurity concentrations in the intrinsic semiconductor region and the LDD region without increasing the photomask. ing. As a technique for reducing the number of used photomasks, for example, Patent Document 2 is known.

JP-A-6-088972 JP 2007-13055 A

However, in the technique described in Patent Document 1, it is necessary to use an expensive photomask according to the type of TFT, and accordingly, the price of the light control substrate is increased and the number of processes is increased. There was a problem. In the technique described in Patent Document 2, since the thin film portion and the thick film portion are close to each other, it is difficult to form a resist for the thin film portion with uniform film thickness because they interfere with each other. There was a problem of being.
On the other hand, halftone exposure / development has a smaller exposure amount and development time margin than normal exposure / development. Therefore, as disclosed in Patent Document 2, if there is another pattern in the vicinity of the halftone pattern, it is difficult to accurately transfer the halftone pattern to the resist film. Specifically, the resist film in the region corresponding to the halftone pattern has a shape defect such as skirting or dripping, which makes it difficult to secure the yield. Further, in the technique of Patent Document 2, since a resist is directly formed on a semiconductor layer and ashing is performed after ion implantation, there is a problem that damage and contamination (impurities and defects) enter the semiconductor layer.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  [Application Example 1] In the manufacturing method of the semiconductor device according to this application example, the first region, the second region, and the third region formed by separating the semiconductor film covering the insulator into islands are arranged on the one surface side. A first gate electrode formed in the first region, a first NMOS TFT including a first LDD having a first concentration sandwiching the first gate electrode in plan view on the one surface side, and the second NMOS TFT A second NMOS electrode formed in a region, a second NMOS TFT including a second LDD having a concentration higher than the first concentration sandwiching the second gate electrode in plan view, and a second NMOS TFT formed in the third region. A method of manufacturing a semiconductor device including a PMOS TFT including three gate electrodes, wherein a gate insulating film included in the first NMOS TFT, the second NMOS TFT, and the PMOS TFT is formed on the one surface side of the substrate. An edge film manufacturing step, a gate electrode forming step of forming the first gate electrode, the second gate electrode, and the third gate electrode on the one surface side, and the thickness in the first region is the third region A step resist forming step of forming a third resist which is thinner than the first region and has a portion corresponding to the second region opened, and the third resist and the second gate electrode covering the third region and the first region As a mask, the first LDD ion implantation step of introducing an N-type impurity by implanting ions into the second LDD precursor, and increasing the acceleration voltage of the ion implantation, the third resist located in the third region By passing ions through the third resist located in the first region, the passage of ions is blocked, and using the third resist, the first gate electrode, and the second gate electrode as a mask, A first LDD precursor, a second LDD ion implantation step of ion-implanting an N-type impurity into the second LDD precursor, forming the first LDD and the second LDD, and a step of removing the third resist. It is characterized by that.

According to this, the third region constituting the PMOS TFT and the first region and the second region constituting the NMOS TFT having two types of LDD concentrations can be processed with a small number of photomasks. Specifically, the process of forming the first LDD and the second LDD can be completed with a single photomask.
The second LDD is formed by two ion implantations. However, in the first ion implantation to the second LDD, ion implantation into the first LDD part is blocked by the third resist covering the first LDD part, and the second LDD is selectively performed. Ion implantation is performed.
Then, in the second ion implantation into the second LDD and the ion implantation into the first LDD portion, the ion energy is increased and the third resist covering the first LDD portion is passed through to the first LDD and the second LDD. To do.
In this way, by using the third resist separately for the ion implantation blocking film and the transmission film according to the implantation energy, the first NMOS TFT having the first LDD and the second NMOS TFT having the second LDD can be suppressed while suppressing an increase in the number of photomasks. It becomes possible to form.
In addition, the third resist is provided in regions separated according to the resist film thickness, and a region having a large film thickness is not formed adjacent to a region having a thin resist film thickness. That is, the shape of each third resist is a simple shape. Therefore, the influence due to the complexity of the shape can be suppressed, and the film thickness stability can be ensured. In addition, since an insulating film as a gate insulating film is formed and a third resist including regions having different thicknesses is formed after the gate electrode is formed, the channel portion of the TFT formed at a position covered with the gate electrode The TFT can be manufactured without contaminating.

[Application Example 2] In the manufacturing method of the semiconductor device according to this application example, the first region, the second region, and the third region formed by separating the semiconductor film covering the insulator into islands are arranged on one side. A first gate electrode formed in the first region, a first NMOS TFT including a first LDD having a first concentration sandwiching the first gate electrode in plan view on the one surface side, and the second NMOS TFT A second NMOS electrode formed in a region, a second NMOS TFT including a second LDD having a concentration higher than the first concentration sandwiching the second gate electrode in plan view, and a second NMOS TFT formed in the third region. A method of manufacturing a semiconductor device including a PMOS TFT including three gate electrodes, wherein a gate insulating film included in the first NMOS TFT, the second NMOS TFT, and the PMOS TFT is formed on the one surface side of the substrate. And Enmaku manufacturing process,
A gate electrode forming step of forming the first gate electrode, the second gate electrode, and the third gate electrode on the one surface side; and a thickness in the first region is smaller than a thickness in the third region And a step resist forming step of forming a third resist having an opening corresponding to the second region, the third resist covering the third region and the first region, and the second gate electrode as a mask. A first LDD ion implantation step of implanting ions into the 2LDD precursor and introducing an N-type impurity; the third resist is not left in the first region, and the third resist is left in the third region Using the third resist, the first gate electrode, and the second gate electrode as a mask, an N-type impurity is formed in the second LDD precursor and the first LDD precursor using the third resist, the first gate electrode, and the second gate electrode as a mask. Ion implantation, after forming the first 2LDD and the second LDD, characterized in that it and a second 2LDD ion implantation step of removing the third resist.

According to this, the third region constituting the PMOS TFT and the first region and the second region constituting the NMOS TFT having two types of LDD concentrations can be processed with a small number of photomasks. Specifically, the process of forming the first LDD and the second LDD can be completed with a single photomask.
The second LDD is formed by two ion implantations. However, in the first ion implantation to the second LDD, ion implantation into the first LDD part is blocked by the third resist covering the first LDD part, and the second LDD is selectively performed. Ion implantation is performed.
Subsequently, the third resist is thinned, the first LDD portion is exposed, and the second ion implantation is performed, so that the first LDD and the second LDD having different concentrations can be formed with one photomask.
In addition, since the second LDD ion implantation performed twice is performed with the second LDD region exposed, variations in TFT characteristics due to variations in the film thickness of the third resist can be suppressed.
In addition, the third resist is provided in regions separated according to the resist film thickness, and a region having a large film thickness is not formed adjacent to a region having a thin resist film thickness. That is, the shape of each third resist is a simple shape. Therefore, the influence due to the complexity of the shape can be suppressed, and the film thickness stability can be ensured. In addition, since an insulating film as a gate insulating film is formed and a third resist including regions having different thicknesses is formed after the gate electrode is formed, the channel portion of the TFT formed at a position covered with the gate electrode The TFT can be manufactured without contaminating.

  [Application Example 3] In the method of manufacturing a semiconductor device according to this application example, the first region, the second region, and the third region formed by separating the semiconductor film covering the insulator into islands are arranged on one surface side. A first gate electrode formed in the first region, a first NMOS TFT including a first LDD having a first concentration sandwiching the first gate electrode in plan view on the one surface side, and the second NMOS TFT A second gate electrode formed in a region; a second NMOS TFT including a second LDD having a concentration higher than the first concentration sandwiching the second gate electrode in plan view; and the second NMOS TFT formed in the third region. A method of manufacturing a semiconductor device including a third gate electrode and a PMOS TFT including a third source / drain formed in three regions, wherein the first NMOS TFT and the second NMOS TFT are formed on the one surface side of the substrate. And before An insulating film manufacturing process for forming a gate insulating film included in the PMOS TFT; a gate electrode forming process for forming the first gate electrode, the second gate electrode, and the third gate electrode on the one surface side; Step resist formation for forming a third resist that covers one region and the second region, has a thickness in the second region smaller than that in the first region, and opens a portion corresponding to the third region Ion implantation is performed using the third resist covering the second region and the first region and the third gate electrode as a mask, and a P-type impurity is introduced to form the third source / drain. In the PSD ion implantation step, the acceleration voltage of the ion implantation is increased so that the third resist located in the first region blocks the passage of ions, and the third resist located in the second region Ion implantation with a dose smaller than the dose in the PSD ion implantation process using the third resist, the first gate electrode, and the second gate electrode located in the first region as a mask. The first LDD ion implantation step of introducing N-type impurities into the second LDD precursor, the step of removing the third resist, and the third source / drain in a range of dose that keeps the P-type. And a second LDD ion implantation step of forming the first LDD and the second LDD by performing ion implantation for introducing a type impurity.

According to this, the third region constituting the PMOS TFT and the first region and the second region constituting the NMOS TFT having two types of LDD concentrations can be processed with a small number of photomasks.
When a known technique is used, starting from an insulating film manufacturing process for forming a gate insulating film, a PMOS TFT having a source / drain, a first NMOS TFT having a source / drain and an LDD, and a second NMOS TFT are formed. Although 7 photomasks are required, the technology of the present invention can be used to form 5 photomasks, shorten the manufacturing process, improve the yield, and reduce the number of expensive photomasks. An inexpensive and highly reliable semiconductor device can be provided.
Further, the second LDD is formed by two ion implantations. In the first ion implantation to the second LDD, the third resist covering the first LDD part prevents the ion implantation to the first LDD part.
In the second ion implantation into the second LDD and the ion implantation into both the first LDD portion, the energy is changed and the third resist covering the second LDD portion is passed through and ion implantation is performed in the second LDD. ing.
In this way, by using the third resist separately for the ion implantation blocking film and the transmission film according to the implantation energy, the first NMOS TFT having the first LDD and the second NMOS TFT having the second LDD can be suppressed while suppressing an increase in the number of photomasks. It becomes possible to form.
In addition, the third resist is provided in regions separated according to the resist film thickness, and a region having a large film thickness is not formed adjacent to a region having a thin resist film thickness. That is, the shape of each third resist is a simple shape. Therefore, the influence due to the complexity of the shape can be suppressed, and the film thickness stability can be ensured. In addition, since an insulating film as a gate insulating film is formed and a third resist including regions having different thicknesses is formed after the gate electrode is formed, the channel portion of the TFT formed at a position covered with the gate electrode The TFT can be manufactured without contaminating.

  Application Example 4 In the method of manufacturing a semiconductor device according to this application example, the first region, the second region, and the third region formed by separating the semiconductor film that covers the insulator into island shapes are on the one surface side. A first gate electrode formed in the first region, a first NMOS TFT including a first LDD having a first concentration sandwiching the first gate electrode in plan view on the one surface side, and the second NMOS TFT A second NMOS electrode formed in a region, a second NMOS TFT including a second LDD having a concentration higher than the first concentration sandwiching the second gate electrode in plan view, and a second NMOS TFT formed in the third region. A method of manufacturing a semiconductor device including three gate electrodes and a PMOS TFT including a third source / drain, wherein the first NMOS TFT, the second NMOS TFT, and the PMOS TFT are provided on the one surface side of the substrate. An insulating film manufacturing process for forming a gate insulating film, and a portion corresponding to the first region and the second region are opened, and ion implantation is performed using the first resist covering the third region as a mask, And an NCD ion implantation step of removing the first resist after introducing a P-type impurity into the semiconductor film in the second region, opening a portion corresponding to the third region, and Ion implantation using the second resist covering the two regions as a mask, introducing an N-type impurity, and then removing the second resist; and the first gate electrode on the one surface side; A gate electrode forming step of forming the second gate electrode and the third gate electrode; and the first region and the second region are covered, and the thickness in the second region is larger than the thickness in the first region. Also thin and the above A step resist forming step for forming a third resist having an opening corresponding to the three regions, ion implantation using the third resist covering the second region and the first region, and the third gate electrode as a mask, P A PSD ion implantation step of forming a third source / drain by introducing a type impurity, and the third resist remains in the first region and the third resist does not remain in the second region. From the dose in the PSD ion implantation process, using the third resist, the first gate electrode, and the second gate electrode located in the first region as a mask. A first LDD ion implantation step of removing the third resist after introducing an N-type impurity into the second LDD precursor after performing ion implantation with a small dose amount; and And a second LDD ion implantation step of forming the first LDD and the second LDD by performing ion implantation for introducing an N-type impurity within a dose range in which the drain and drain maintain a P-type. And

According to this, the third region constituting the PMOS TFT and the first region and the second region constituting the NMOS TFT having two types of LDD concentrations can be processed with a small number of photomasks.
When a known technique is used, starting from an insulating film manufacturing process for forming a gate insulating film, a PMOS TFT having a source / drain, a first NMOS TFT having a source / drain and an LDD, and a second NMOS TFT are formed. Although 7 photomasks are required, the technology of the present invention can be used to form 5 photomasks, shorten the manufacturing process, improve the yield, and reduce the number of expensive photomasks. An inexpensive and highly reliable semiconductor device can be provided.
In addition, since an insulating film as a gate insulating film is formed and a third resist including regions having different thicknesses is formed after the gate electrode is formed, the channel portion of the TFT formed at a position covered with the gate electrode The TFT can be manufactured without contaminating.
In addition, the third resist is provided in regions separated according to the resist film thickness, and a region having a large film thickness is not formed adjacent to a region having a thin resist film thickness. That is, the shape of each third resist is a simple shape. Therefore, the influence due to the complexity of the shape can be suppressed, and the film thickness stability can be ensured.
Subsequently, the third resist is thinned, the first LDD portion is exposed, and the second ion implantation is performed, so that the first LDD and the second LDD having different concentrations can be formed with one photomask.
Further, in this case, the second LDD ion implantation performed twice is performed with the second LDD region exposed, so that variation in TFT characteristics due to variation in the film thickness of the third resist can be suppressed.

  Application Example 5 In the semiconductor device manufacturing method according to the application example described above, in the exposure step of forming the third resist, the light intensity is adjusted to a halftone level in the exposure of the thin region of the third resist. A method for manufacturing a semiconductor device, wherein a halftone mask having a pattern to be controlled is used.

  According to the application example described above, a resist film having two types of film thickness can be formed by self-alignment, and high positional accuracy can be ensured. In addition, since a resist film having two types of film thickness can be formed by a single photolithography process, the processing cost can be reduced.

  Application Example 6 A method for manufacturing a semiconductor device according to this application example includes the method for manufacturing a semiconductor device according to the application example described above, forming the first NMOS TFT for controlling the potential or current value of a pixel, and manipulating image information. The second NMOS TFT and the PMOS TFT are formed.

  According to this, since the first NMOS TFT having a small number of masks and less leaking and suitable for the holding operation, the second NMOS TFT capable of high-speed operation and excellent in processing speed for manipulating image information, and the PMOS TFT can be formed. It is possible to provide a manufacturing method for manufacturing an electro-optical device with few attachment parts.

It is the schematic which shows the structure of a liquid crystal device, The figure (a) is a front view, The figure (b) is the HH 'sectional view taken on the line (a). FIG. 3 is an equivalent circuit diagram of a liquid crystal device. Process sectional drawing which shows the manufacturing process concerning 1st Embodiment. Process sectional drawing which shows the manufacturing process concerning 1st Embodiment. Process sectional drawing for demonstrating the manufacturing process concerning 2nd Embodiment. Process sectional drawing for demonstrating the manufacturing process concerning 3rd Embodiment. Process sectional drawing for demonstrating the manufacturing process concerning 4th Embodiment.

(First embodiment)
FIG. 1 is a schematic diagram illustrating a structure of a liquid crystal device as an electro-optical device. FIG. 2 is an equivalent circuit diagram of the liquid crystal device shown in FIG. Hereinafter, the structure of the liquid crystal device will be described with reference to FIGS.
In the present embodiment, an active matrix liquid crystal device including a thin film transistor (hereinafter referred to as TFT) as a pixel switching element will be described as an example. Here, the pixel switching TFT is also referred to as a TFT 30 hereinafter.
The illustrated liquid crystal device 100 can be suitably used as, for example, a light modulation means (liquid crystal light valve or the like) of a projection display device (liquid crystal projector) described later or a direct-view display. In addition, the electro-optical device can be applied to, for example, an organic EL device and electronic paper other than the liquid crystal device.

<Configuration of liquid crystal device>
First, the liquid crystal device of this embodiment will be described with reference to FIGS. 1A and 1B are schematic views showing the configuration of the liquid crystal device, where FIG. 1A is a front view, and FIG. 1B is a cross-sectional view taken along line HH ′ of FIG.

As shown in FIGS. 1A and 1B, the liquid crystal device 100 of this embodiment includes an element substrate 10 and a counter substrate 20 as substrates, and a liquid crystal layer 50 sandwiched between the pair of substrates.
The element substrate 10 is slightly larger than the counter substrate 20, and both substrates are bonded via a sealing material 52, and liquid crystal having positive dielectric anisotropy is sealed in the gap to form the liquid crystal layer 50. .

  As shown in FIG. 2A, a data line driving circuit 101 is provided along one side portion of the element substrate 10, and a plurality of terminal portions 102 electrically connected thereto are arranged. On the other two sides orthogonal to the one side and facing each other, a scanning line driving circuit 104 is provided along the two sides. A plurality of wirings 105 that connect the two scanning line driving circuits 104 are provided on the other one side facing the one side across the counter substrate 20.

  A parting portion 53 is also provided in a frame shape on the inside of the sealing material 52 arranged in a frame shape. The parting part 53 is a display region 10 a having a plurality of pixels G inside the parting part 53 using a light-shielding metal material or resin material.

  As shown in FIG. 2B, the element substrate 10 is provided with a BM (black matrix) as a light shielding film that partitions the pixels G. In this case, the BM includes a light-shielding metal material such as Al or Ti, or a film in which these are laminated.

  An alignment film 29 is formed on the surface of the counter substrate 20 on the liquid crystal layer 50 side so as to cover at least the parting portion 53 and the display region 10a. The alignment film 18 and the alignment film 29 are subjected to an alignment process in a predetermined direction.

FIG. 2 is an equivalent circuit diagram of the liquid crystal device. As shown in FIG. 2, the display area 10a of the liquid crystal device 100 includes m rows (m is an integer) of scanning lines 3a extending in the row direction and n columns (n is an integer) of data extending in the column direction. A line 6a and a plurality of pixels G arranged in a matrix at each intersection of the scanning line 3a and the data line 6a are provided. Each pixel G includes a pixel electrode 9 as a second electrode and a TFT 30 as a first NMOS TFT for switching control of the pixel electrode 9. A liquid crystal layer 50 is interposed between the pixel electrode 9 and the common electrode 19 as the first electrode. The common electrode 19 is electrically connected to the common line 3 b extending from the scanning line driving circuit 104, and is held at a common potential in each pixel G.
The scanning line driving circuit 104 includes a circuit including an NMOS TFT 40n and a PMOS TFT 40p as second NMOS TFTs that can be switched at a higher speed than the TFT 30, and drives the scanning line 3a and performs timing data and other signal processing. ing.

A data line 6 a extending from the data line driving circuit 101 is electrically connected to the source of the TFT 30. The data line driving circuit 101 supplies the image signals D1, D2,..., Dn to each pixel G through the data line 6a. The image signals D1 to Dn may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a.
The data line driving circuit 101 includes a circuit including an NMOS TFT 40n and a PMOS TFT 40p that can be switched at a higher speed than the TFT 30, and drives the data line 6a and performs timing data and other signal processing.

  Further, the scanning line 3 a extending from the scanning line driving circuit 104 is electrically connected to the gate of the TFT 30. Scan signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 104 to the scanning line 3a at a predetermined timing are applied to the gates of the TFTs 30 in this order. The pixel electrode 9 is electrically connected to the drain of the TFT 30.

  The TFT 30 serving as a switching element is turned on for a certain period by the input of the scanning signals SC1, SC2,..., SCm, so that the image signals D1, D2,. Writing is performed on the pixel electrode 9. Image signals D1, D2,..., Dn written to the liquid crystal layer 50 through the pixel electrode 9 are held for a certain period between the pixel electrode 9 and the common electrode 19 facing through the liquid crystal layer 50. The

  Thus, when a voltage signal is applied to the liquid crystal layer 50, the alignment state of the liquid crystal molecules changes depending on the applied voltage level. Thereby, the light incident on the liquid crystal layer 50 is modulated to generate image light.

In the following, with respect to a method for manufacturing a liquid crystal device as the electro-optical device described above, the manufacturing process of the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 will be described with reference to the drawings.
3 and 4 are process cross-sectional views for explaining the manufacturing process according to the present embodiment.

First, a silicon nitride layer 151 is deposited on the first surface of the element substrate 10 using an insulator such as quartz, and then a silicon oxide layer 152 is deposited. Then, for example, a polycrystalline silicon film 153 (FIG. 3A is 158, please correct it) is deposited as a semiconductor film at about 1000 ° C. A cross-sectional view after the steps up to here are shown in FIG.
Although the case where quartz is used as the insulator has been described here, a semiconductor or conductor covered with an insulator (insulating portion) may be used as the element substrate 10.

  Next, the polycrystalline silicon film 153 is separated into an island shape in a plan view of the element substrate 10 by photolithography / etching to form a first region 155, a second region 156, and a third region 157. Here, there are usually a plurality of first regions 155, second regions 156, and third regions 157. A cross-sectional view after the steps so far are shown in FIG.

  Next, a gate insulating film 158 is formed on the first surface of the element substrate 10. The gate insulating film 158 can be formed using a CVD method or a thermal oxidation method. In this embodiment, the description is continued assuming that the CVD method is used (insulating film manufacturing process). The figure which completed the process so far is shown in FIG.3 (c).

  Next, the portion corresponding to the first region 155 and the second region 156 is opened, and the first resist 201 covering the third region 157 is used as a mask, and the portion corresponding to the first region 155 and the second region 156 shows P-type impurities. (For example, boron) is ion-implanted. Then, after the ion implantation, the first resist 201 is removed (NCD ion implantation step). A cross-sectional view in a state where ion implantation is performed is shown in FIG.

  Next, using the second resist 202 covering the first region 155 and the second region 156 and opening the third region 157 as a mask, an N-type impurity (for example, phosphorus) is ionized in the portion corresponding to the third region 157. inject. Then, after the ion implantation, the second resist 202 is removed (PCD ion implantation step). A cross-sectional view in a state where ion implantation is performed is shown in FIG.

  Next, the first gate electrode 160 is formed in the first region 155, the second gate electrode 161 is formed in the second region 156, and the third gate electrode 162 is formed in the third region 157. The first gate electrode 160, the second gate electrode 161, and the third gate electrode 162 may be made of metal, polysilicon, a compound of metal and silicon, or a multilayer structure thereof. The first gate electrode 160, the second gate electrode 161, and the third gate electrode 162 can be formed by photolithography / etching after forming a gate electrode precursor (not shown) (gate electrode forming step). A cross-sectional view after the steps up to here are shown in FIG.

  Next, a third resist 203 is formed in which the thickness in the first region 155 is smaller than the thickness in the third region 157 and the second region 156 is opened (step resist forming step). A cross-sectional view after the steps up to here are shown in FIG. Thus, when setting the resist thickness at a plurality of levels, it is preferable to use a halftone mask because an increase in the number of manufacturing steps can be suppressed. Here, the thickness of the third resist 203 in the first region 155 is about 200 nm, for example, and the thickness of the third region 157 is about 600 nm, for example.

  Next, an ion acceleration voltage is set so that the third resist 203 covering the first region 155 and the third region 157 prevents the passage of ions. Then, using the third resist 203 covering the first region 155 and the third region 157 and the second gate electrode 161 as a mask, ion implantation of an N-type impurity (for example, phosphorus) is performed on the second region 156 to form the second LDD. A precursor 165a is formed (first LDD ion implantation step). When phosphorus is used, if an acceleration voltage of about 60 keV is used, the passage of phosphorus ions is blocked by the third resist 203 in the first region 155, and phosphorus ions are implanted in the second region 156. FIG. 3H shows a cross-sectional view in a state where ion implantation is performed.

  Next, the acceleration energy used for ion implantation is increased, and the region to be the first LDD 164, the second LDD precursor 165a, and the third region 157, the second gate electrode 161, and the first gate electrode 160 are used as a mask. N-type impurities (for example, phosphorus) are ion-implanted to form second LDD 165 and first LDD 164 (second LDD ion implantation step). Then, after ion implantation, the third resist 203 is removed. When phosphorus is used as the N-type impurity, phosphorus ions are implanted into the first region 155 and the second region 156 when an acceleration voltage of about 80 keV is used. A cross-sectional view in a state where ion implantation is performed is shown in FIG. Since the first gate electrode 160 and the second gate electrode 161 are used as a mask, the first LDD 164 sandwiches the first gate electrode 160 in a plan view of the element substrate 10, and the second LDD 165 sandwiches the second gate electrode 161. It becomes. Note that the first LDD ion implantation step and the high-acceleration second LDD ion implantation step can interchange the order of the steps.

  Next, a portion corresponding to the third region 157 is opened, a fourth resist 204 covering the portions corresponding to the first region 155 and the second region 156 is formed, and ion implantation is performed using the fourth resist 204 and the third gate electrode 162 as a mask. Then, a P-type impurity (for example, boron) is implanted to form the third source / drain 170 of the PMOS TFT 40p (PSD ion implantation process). Then, after ion implantation, the fourth resist 204 is removed. A cross-sectional view in a state where ion implantation is performed is shown in FIG. In the (PSD ion implantation step), it is preferable that the dose amount is controlled so that the third source / drain 170 has an impurity concentration enough to form an ohmic contact with an electrode 175 described later.

  Next, the third region 157, the first LDD 164, the second LDD 165, the first gate electrode 160, and the second gate electrode 161 are covered, and the region to be the first source / drain 171 and the region to be the second source / drain 172 Ion implantation is performed using the fifth resist 205 having an opening corresponding to the corresponding portion as a mask, an N-type impurity (for example, phosphorus) is introduced, and a part of the first LDD 164 is converted into the N-type first source / drain 171. A part of the 2LDD 165 is converted into a high-concentration N-type second source / drain 172. After the ion implantation, the fifth resist 205 is removed. (NSD ion implantation step). A cross-sectional view in a state where ion implantation is performed is shown in FIG. In the (NSD ion implantation step), the dose is controlled so that the first source / drain 171 and the second source / drain 172 have an impurity concentration enough to form an ohmic contact with an electrode 175 described later. It is preferable.

  Next, after the interlayer insulating film 180 is formed, an electrode 175 connected to the first source / drain 171, the second source / drain 172, and the third source / drain 170 is formed (electrode formation step). A cross-sectional view after the steps so far are shown in FIG.

  By using the manufacturing process described above, for example, the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 suitable for driving the liquid crystal device 100 can be formed.

  The above-described manufacturing method of the electro-optical device has the following effects.

As shown in FIG. 2, for a liquid crystal device, an organic EL device, electronic paper, etc., as shown in FIG. 2, the TFT 30 with low leakage and excellent charge retention characteristics and the data line 6a are driven. The NMOS TFT 40n and the PMOS TFT 40p, which are excellent in operation speed for performing timing data and other signal processing, can be formed on the same substrate while suppressing an increase in the number of masks.
Specifically, the process of forming the gate insulating film 158 and the process of forming the N-type first source / drain 171 and the N-type second source / drain 172 are formed using six photomasks. can do. This corresponds to the number of photomasks when the NMOS TFT 40n is not formed in the conventional process. That is, the NMOS TFT 40n can be formed as a new TFT without increasing the photomask.

  In addition to the effects of the above-described embodiments, the method for manufacturing a semiconductor device according to the present embodiment has the following effects.

  In order to perform the ion implantation and the photolithography process after forming the gate insulating film 158, the channel of the TFT 30, the NMOS TFT 40n, and the PMOS TFT 40p (a part of the first region 155 covered with the first gate electrode 160, the second region 156, respectively). The damage to the portion covered with the second gate electrode 161 and the portion covered with the third gate electrode 162 of the third region 157) and the intrusion of contamination (impurities and defects) can be suppressed. Fewer manufacturing processes can be built.

  By manufacturing a resist pattern having a step using a halftone mask, a resist film having two types of film thickness can be formed by self-alignment, and high positional accuracy can be ensured. In addition, since a resist film having two types of film thickness can be formed by a single photolithography process, the processing cost can be reduced.

  When a positive resist is used, the halftone mask pattern is surrounded by the light transmission region. Therefore, since interference with other light shielding patterns can be avoided, the pattern shape and resist thickness reproducibility can be improved.

  After forming a stepped third resist 203 using a halftone mask, the concentration of the first LDD 164 and the second LDD 165 is adjusted by changing the acceleration energy of ions. That is, the third resist 203 is selectively used as an ion implantation blocking film and a transmissive film according to the ion implantation energy, thereby suppressing the increase in the number of photomasks and forming the TFT 30 including the first LDD 164 and the NMOS TFT 40n including the second LDD 165. be able to.

(Second Embodiment)
As a manufacturing method of the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 used in the liquid crystal device 100 and various electro-optical devices, manufacturing methods other than those described above can be used. Hereinafter, embodiments for manufacturing these will be described with reference to the drawings.
FIG. 5 is a process cross-sectional view for explaining a manufacturing process according to the second embodiment. In this embodiment, since there is a portion overlapping with the above description, the above description is cited for the overlapping portion, and the overlap is avoided.

  First, since the steps up to the step resist forming process are the same, the description starts from the point where the step resist forming process is repeated.

  A third resist 203 having a thickness in the first region 155 smaller than that of the third region 157 and opening the second region 156 is formed (step resist forming step). A cross-sectional view after the steps up to here are shown in FIG. As a method of forming the third resist 203, it is preferable to use a halftone mask from the viewpoint of alignment accuracy and the like.

  Next, using the third resist 203 covering the third region 157 and the first region 155 and the second gate electrode 161 as a mask, ion implantation of N-type impurities (for example, phosphorus) is performed on the second region 156, A 2LDD precursor 165a is formed (first LDD ion implantation step). A cross-sectional view in a state where ion implantation is performed is shown in FIG.

  Next, the third resist 203 is thinned by using a method such as ashing so that the third resist 203 remains in the third region 157 and the third resist 203 does not remain in the first region 155 (thinning step). . A cross-sectional view after the steps up to here are shown in FIG.

  Next, an N-type impurity (for example, phosphorus) is added to the second LDD precursor 165a using the third resist 203, the second gate electrode 161, and the first gate electrode 160 remaining in the third region 157 as a mask. Ion implantation is performed to form the second LDD 165. Here, the first LDD 164 is also formed at the same time. After the ion implantation, the third resist 203 is removed (second LDD ion implantation step). FIG. 5D shows a cross-sectional view in a state where ion implantation is performed. Since the first gate electrode 160 and the second gate electrode 161 are used as a mask, the first LDD 164 sandwiches the first gate electrode 160 in a plan view of the element substrate 10, and the second LDD 165 sandwiches the second gate electrode 161. It becomes.

  Thereafter, by performing (PSD ion implantation process), (NSD ion implantation process) and (electrode formation process) in the first embodiment, for example, NMOS TFT 40n, PMOS TFT 40p and TFT 30 suitable for driving the liquid crystal device 100 are formed. be able to.

  In addition to the effects of the above-described embodiments, the method for manufacturing a semiconductor device according to the present embodiment has the following effects.

  Since the ion implantation for forming the first LDD 164 and the second LDD 165 is performed after the thin region of the third resist 203 is removed by means such as ashing, ion implantation having the same profile is performed on both LDDs. Become. Therefore, it is not affected by the thickness distribution of the third resist 203. Therefore, the impurity concentrations of the first LDD 164 and the second LDD 165 can be kept stable.

(Third embodiment)
As a manufacturing method of the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 used in the liquid crystal device 100 and various electro-optical devices, manufacturing methods other than those described above can be used. Hereinafter, embodiments for manufacturing these will be described with reference to the drawings.
FIG. 6 is a process cross-sectional view for explaining a manufacturing process according to the third embodiment. In this embodiment, since there is a portion overlapping with the above description, the above description is cited for the overlapping portion, and the overlap is avoided.

First, since the same process as in the first embodiment is used until the gate electrode formation process, the description starts from the step resist formation process.
A third resist 303 is formed to cover the first region 155 and the second region 156, the thickness of the second region 156 is smaller than the thickness of the first region 155, and the third region 157 is opened (step resist) Forming step). A cross-sectional view after the steps up to here are shown in FIG.
Thus, when adjusting the thickness of the resist, it is preferable to use a halftone mask. Here, the thickness of the third resist 203 in the first region 155 is about 600 nm, for example, and the thickness of the second region 156 is about 200 nm, for example.

  Next, ion implantation is performed using the third resist 303 covering the second region 156 and the first region 155 and the third gate electrode 162 as a mask, and P-type impurities are introduced to form the third source / drain 170. (PSD ion implantation process). A cross-sectional view in a state where ion implantation is performed is shown in FIG. In this step, the third source / drain 170 can form an ohmic contact with the electrode 175 even after N-type impurity implantation is performed by the (first LDD ion implantation step) and (second LDD ion implantation step) described later. It is preferable that the dose is controlled so that the impurity concentration is about a certain level.

Next, the ion acceleration voltage is adjusted so that the third resist 303 covering the first region 155 blocks the passage of ions and the third resist 303 located at the position covering the second region 156 allows the ions to pass therethrough.
Then, using the third resist 303 located in the first region 155, the first gate electrode 160, and the second gate electrode 161 as a mask, ion implantation is performed with a dose smaller than that in the (PSD ion implantation step). (First LDD ion implantation step). Then, after introducing an N-type impurity into the second LDD precursor 165a, the third resist 303 is removed. When phosphorus is used as an N-type impurity, if an acceleration voltage of about 80 keV is used, the third resist 303 in the first region 155 blocks the passage of phosphorus ions, and phosphorus ions are implanted into the second region 156. The A cross-sectional view in a state where ion implantation is performed is shown in FIG. At this time, an N-type impurity is added to the third source / drain 170, but the N-type impurity enters only a dose smaller than the dose in the (PSD ion implantation step). 170 keeps P-type. Therefore, the operation of the PMOS TFT 40p is hardly affected. Note that the order of the PSD ion implantation step and the high-acceleration first LDD ion implantation step can be interchanged with each other.

  Next, the first LDD 164 and the second LDD 165 are formed by performing ion implantation for introducing an N-type impurity within a dose range in which the third source / drain 170 maintains the P-type (second LDD ion implantation step). . A cross-sectional view in a state where ion implantation is performed is shown in FIG. Even in this case, an N-type impurity is introduced into the third source / drain 170, but the operation of the PMOS TFT 40p is hardly affected as in the (first LDD ion implantation step). Since the first gate electrode 160 and the second gate electrode 161 are used as a mask, the first LDD 164 sandwiches the first gate electrode 160 in a plan view of the element substrate 10, and the second LDD 165 sandwiches the second gate electrode 161. It becomes.

  Thereafter, by performing the (NSD ion implantation step) and the (electrode formation step) in the first embodiment, for example, the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 suitable for driving the liquid crystal device 100 can be formed.

  In addition to the effects of the above-described embodiments, the method for manufacturing a semiconductor device according to the present embodiment has the following effects.

As shown in FIG. 2, for a liquid crystal device, an organic EL device, electronic paper, etc., as shown in FIG. 2, the TFT 30 with low leakage and excellent charge retention characteristics and the data line 6a are driven. The NMOS TFT 40n and the PMOS TFT 40p, which are excellent in operation speed for performing timing data and other signal processing, can be formed on the same substrate while suppressing an increase in the number of masks.
When a TFT including the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 is formed using a conventional process, seven photomasks are required. On the other hand, when this embodiment is used, five photomasks can be used.
As an example, the second LDD 165 is formed by two ion implantations. However, in the first ion implantation to the second LDD 165, ion implantation into the first LDD 164 part is blocked by the third resist covering the first LDD 164 part, and the second LDD 165 part. During the second ion implantation and ion implantation into the first LDD 164 portion, the energy is changed and the third resist covering the second LDD 165 portion is passed through and implanted into the second LDD 165. By using the third resist 303 as an ion implantation blocking film and a transmission film according to the implantation energy, the first LDD 164 and the second LDD 165 can be formed with one resist pattern (that is, one photomask). An increase in the number of masks can be suppressed.
Note that the concentration of the third source / drain 170 of the PMOS TFT 40p is usually higher than that of the first LDD 164 and the second LDD 165 by one digit or more. Therefore, the influence of the third source / drain 170 is below the normal detection limit. It will fit.

(Fourth embodiment)
As a manufacturing method of the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 used in the liquid crystal device 100 and various electro-optical devices, manufacturing methods other than those described above can be used. Hereinafter, embodiments for manufacturing these will be described with reference to the drawings.
FIG. 7 is a process cross-sectional view for explaining a manufacturing process according to the fourth embodiment. In this embodiment, since there is a portion overlapping with the above-described third embodiment, the above description is cited for the overlapping portion, and the overlap is avoided.
Here, since the same process as that of the third embodiment is used until (PSD ion implantation process), the cross-sectional shape after (PSD ion implantation process) is shown again in FIG. The explanation starts from.

  In the thinning step, the third resist 303 is thinned so that the third resist 303 remains in the first region 155 and the third resist 303 does not remain in the second region 156. A cross-sectional view after the steps up to here are shown in FIG.

  Next, using the third resist 303 covering the first region 155, the first gate electrode 160, and the second gate electrode 161 as a mask, ion implantation is performed with a dose smaller than that in the (PSD ion implantation step). To introduce N-type impurities into the second LDD precursor 165a. Then, after the ion implantation, the third resist 303 is removed (first LDD ion implantation step). A cross-sectional view in a state where ion implantation is performed is shown in FIG.

  Thereafter, by subsequently processing from the (second LDD ion implantation step) in the third embodiment, for example, the NMOS TFT 40n, the PMOS TFT 40p, and the TFT 30 suitable for driving the liquid crystal device 100 can be formed.

  In addition to the effects of the above-described embodiments, the method for manufacturing a semiconductor device according to the present embodiment has the following effects.

  After forming a stepped third resist 303 using a halftone mask, ion implantation of the second LDD 165 not covered with the third resist 303 is performed. Then, the third resist 303 is removed, and N-type ion implantation is performed on one surface side of the element substrate 10 to form the first LDD 164 and the second LDD 165, so that the thickness of the third resist 303 is different. The second LDD 165 is formed without being affected. Therefore, the impurity concentration of the second LDD 165 can be stabilized against process fluctuations. Note that since the concentration of the third source / drain 170 of the PMOS TFT 40p is usually different by one digit or more, the influence of the third source / drain 170 falls below the normal detection limit.

  3a ... scanning line, 6a ... data line, 9 ... pixel electrode, 10 ... element substrate, 10a ... display region, 18 ... alignment film, 19 ... common electrode, 20 ... counter substrate, 29 ... alignment film, 30 ... TFT, 40n ... NMOS TFT, 40p ... PMOS TFT, 50 ... Liquid crystal layer, 52 ... Sealing material, 53 ... Parting part, 100 ... Liquid crystal device, 101 ... Data line driving circuit, 102 ... Terminal part, 104 ... Scanning line driving circuit, 105 ... Wiring, 151 ... Silicon nitride layer, 152 ... Silicon oxide layer, 153 ... Polycrystalline silicon film, 155 ... First region, 156 ... Second region, 157 ... Third region, 158 ... Gate insulating film, 160 ... First gate electrode, 161 ... second gate electrode, 162 ... third gate electrode, 164 ... first LDD, 165 ... second LDD, 165a ... second LDD precursor, 170 ... third source / drain, 171 ... first Source / drain, 172 ... second source / drain, 175 ... electrode, 180 ... interlayer insulating film, 201 ... first resist, 202 ... second resist, 203 ... third resist, 204 ... fourth resist, 205 ... fifth Resist, 303 ... third resist.

Claims (4)

A substrate provided with a first region, a second region, and a third region on one surface side formed by separating a semiconductor film covering an insulator into an island shape;
A first NMOS TFT including a first gate electrode formed in the first region and a first LDD having a first concentration sandwiching the first gate electrode in plan view on the one surface side;
A second NMOS TFT including a second gate electrode formed in the second region and a second LDD having a concentration higher than the first concentration sandwiching the second gate electrode in the plan view;
A PMOS TFT including a third gate electrode formed in the third region;
A method of manufacturing a semiconductor device including:
An insulating film manufacturing step of forming a gate insulating film included in the first NMOS TFT, the second NMOS TFT, and the PMOS TFT on the one surface side of the substrate;
A gate electrode forming step of forming the first gate electrode, the second gate electrode, and the third gate electrode on the one surface side;
A step resist forming step of forming a third resist in which the thickness in the first region is smaller than the thickness in the third region and the portion corresponding to the second region is opened;
Using the third resist covering the third region and the first region and the second gate electrode as a mask, a first LDD ion implantation step of implanting an N-type impurity by implanting ions into the second LDD precursor;
By increasing the acceleration voltage of ion implantation, the third resist located in the third region is prevented from passing ions, and the third resist located in the first region is allowed to pass ions, Using the resist, the first gate electrode, and the second gate electrode as a mask, N-type impurities are ion-implanted into the first LDD precursor and the second LDD precursor to form the first LDD and the second LDD. A second LDD ion implantation step, a step of removing the third resist,
A method for manufacturing a semiconductor device, comprising: A substrate provided with a first region, a second region, and a third region on one surface side formed by separating a semiconductor film covering an insulator into an island shape;
A first NMOS TFT including a first gate electrode formed in the first region and a first LDD having a first concentration sandwiching the first gate electrode in plan view on the one surface side;
A second NMOS TFT including a second gate electrode formed in the second region and a second LDD having a concentration higher than the first concentration sandwiching the second gate electrode in the plan view;
A PMOS TFT including a third gate electrode formed in the third region;
A method of manufacturing a semiconductor device including:
An insulating film manufacturing step of forming a gate insulating film included in the first NMOS TFT, the second NMOS TFT, and the PMOS TFT on the one surface side of the substrate;
A gate electrode forming step of forming the first gate electrode, the second gate electrode, and the third gate electrode on the one surface side;
A step resist forming step of forming a third resist in which the thickness in the first region is smaller than the thickness in the third region and the portion corresponding to the second region is opened;
Using the third resist covering the third region and the first region and the second gate electrode as a mask, a first LDD ion implantation step of implanting an N-type impurity by implanting ions into the second LDD precursor;
A thinning step of thinning the third resist so that the third resist remains in the third region without leaving the third resist in the first region;
N-type impurities are ion-implanted into the second LDD precursor and the first LDD precursor using the third resist, the first gate electrode, and the second gate electrode as a mask, and the first LDD and the second LDD are And a second LDD ion implantation step of removing the third resist after the configuration. A method of manufacturing a semiconductor device according to claim 1 or 2, wherein the third resist the formation exposure process, the exposure of the third thickness of the resist is thin region controls the light intensity in the halftone A method for manufacturing a semiconductor device, comprising using a halftone mask having a pattern to be processed. Includes a method of manufacturing a semiconductor device according to any one of claim 1 to 3 the first 1NMOSTFT form included in the pixels constituting the display area of the electro-optical device, included in the circuit for driving the pixel A method of manufacturing an electro-optical device, wherein the second NMOS TFT and the PMOS TFT are formed.

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