JPH06216322A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To materialize high integration by making the cell area of a semiconductor integrated circuit device while maintaining the effect of preventing latch up phenomena. CONSTITUTION:The first layer wirings 6a and 6b required for power supply to the guard rings 5d, 5e, 4d, and 4e at the center of a cell 10 are also used as the power supply lines to the diffused layers of a transistor, thus the power supply line by the first layer wirings at the top and the bottom of the cell are eliminated and these sections are used as wiring areas for signals. Furthermore, rows of these cells are arranged so that the same channel regions 1 and 1, and 2 and 2 may face each other between the rows of cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a CMOS semiconductor integrated circuit device using a cell having a guard ring for preventing latch-up.

[0002]

2. Description of the Related Art FIG. 7 is a pattern diagram of an inverter cell having a conventional guard ring for preventing latch-up. In the figure, 1 is an N well, and this portion is a P channel region in which a PMOS transistor is formed. . Reference numeral 2 denotes a P well, which serves as an N channel region in which an NMOS transistor is formed. 3 is a gate electrode. Four
a and 4b are P + diffusion layers, which are the source and drain of the PMOS transistor, and 5a and 5b.
Reference numeral b is an N + diffusion layer, which is the source and drain of the NMOS transistor, respectively. In addition to using the gate electrode as the wiring, the wiring is arranged at a second distance from the wiring of the first wiring layer which is arranged at a predetermined first distance from the main surface of the semiconductor substrate. The wiring of the second wiring layer is used, and the former is called the first layer wiring and the latter is called the second layer wiring. For example, the drains 4b and 5b are connected to the first layer wirings 6c and 6d and the second layer wiring 7 in order to intersect with the first layer wiring of the guard ring portion, which will be described later. Contact 8 which is a hole for conducting the layer metal
a, 8b and through holes 9a, 9b which are holes for conducting the first layer wiring and the second layer wiring are used. Further, power supply to the transistors is performed from the first power supply line 6e and the second power supply line 6f by the first layer wiring at the upper and lower ends of the cell. For example, from the first power supply line 6e to the source 4a of the PMOS transistor, the first layer metal 6g and the contact 8 are formed.
source 5a of NMOS transistor
To the second power supply line 6f using the first layer metal 6h and the contact 8d. And 5c, 5d, 5e
Is an N + diffusion layer having a first power source potential, and 4c, 4d, 4
e is a P + diffusion layer having a second power source potential, and these are guard rings for preventing latch-up. Gate wiring 3
In order to supply power to the diffusion layers 5d and 5e and the diffusion layers 4d and 4e, respectively, which sandwich the wiring, the first power supply line 6a and the second power supply line 6b of the first layer wiring are provided on the diffusion layer of the guard ring. , The contacts 8e to 8h are opened to supply power to them.

FIG. 8 shows a layout and wiring of cells having a conventional guard ring for preventing latch-up. In the figure, 10 is a cell and 11 is a cell row, and all the cells are arranged in the same direction (the upper side in the drawing is the N well 1).
First layer wiring 12 connected to the power supply line on the left and right of the cell row
On the diffusion layer 13 and placing the cell column end cells 15 configured to make them conductive by the contacts 14 around the N-well 1 and the P-well 2 of the entire cell column and to connect each power supply line by the first-layer wiring. , And is surrounded by a guard ring made of a diffusion layer having a power supply potential. The outside of the cell row is used as a signal wiring area 50, and each cell 10 is connected by the wiring 16.
Wiring between.

Next, the operation of the latch-up preventing guard ring will be described. FIG. 9 is a diagram showing an inverter pattern of a cell without a guard ring. Compared to FIG. 7, the cell area is reduced by the absence of the guard ring, and the drains 4b and 5b are connected only by the first layer wiring 6i.

FIGS. 10 and 11 are conceptual views of vertical cross sections of the cells of FIGS. 9 and 7, respectively, and FIGS. 12 and 13 are circuit diagrams of the parasitic bipolar transistors of FIGS. 10 and 11, respectively. . A parasitic bipolar transistor is structurally formed in the CMOS transistor. Of these, a P + drain 4b, an N well 1 and a P well 2 form a P
NP transistor Q1, N well 1, P well 2, N
+ NPN transistor Q2 with drain 5b and P +
The PNP transistor Q3 composed of the source 4a, the N well 1 and the P well 2 and the NPN transistor Q4 composed of the N well 1, the P well 2 and the N + source 5a participate in the latch-up. There are two possible processes leading to latch-up.

First, when an external excessive voltage is applied to the diffusion layer 4b which is the emitter of the PNP transistor Q1,
The voltage of the emitter 4b becomes higher than the base potential of the N well 1 and the PNP transistor Q1 operates, so that the voltage drop of the diffusion resistance Rp of the P well 2 occurs, and then the NPN transistor Q4 starts to operate and the N well 1 A voltage drop occurs in the diffusion resistance Rn of the PNP transistor Q3, which causes the thyristor of the PNPN structure formed by the PNP transistor Q3 and the NPN transistor Q4 to operate, and the operation after the voltage drop of the diffusion resistance Rp is repeated. Excessive current continues to flow between the two power supplies.

The other is that when an external undervoltage is applied to the diffusion layer 5b which is the emitter of the NPN transistor Q2, it becomes lower than the base potential of the P well 2 and the NPN transistor Q2 operates, so that the N well 1 A voltage drop occurs in the diffused resistor Rn, and the same cycle as the previous process is repeated, leading to latch-up.

Compared to FIG. 10, in FIG. 11, there are guard rings such as N + diffusion layers 5d and 5e having the first power supply potential and P + diffusion layers 4d and 4e having the second power supply potential. P + drain 4 in addition to the parasitic bipolar transistor
b, the N well 1, P + diffusion layers 4d and 4e form a PNP transistor Q5, and the N + diffusion layers 5d and 5e, the P well 2 and the N + drain 5b form an NPN transistor Q6. From this fact, when an excessive voltage is applied to the diffusion layer 4b, the PNP transistor Q5 operates and the diffusion layer 5b
When an undervoltage is applied to the NPN transistor Q6, the excessive current can be released. Further, since the regions 4a and 5a at both ends forming the thyristor are separated by the existence of the guard ring, the thyristor becomes hard to work accordingly. From these two points, the guard ring has an effect of preventing latch-up.

[0009]

Since the conventional CMOS semiconductor integrated circuit device using the cell having the latch-up prevention guard ring is configured as described above, it is different from the case where the cell having no guard ring is used. In comparison, although there is an effect of preventing latch-up, there is a problem that the cell area becomes large.

The present invention has been made in order to solve the above problems, and it is a semiconductor integrated device which has a guard ring and can reduce the chip area compared with the conventional cell having a guard ring. The purpose is to obtain a circuit device.

[0011]

In a semiconductor integrated circuit device according to the present invention, a power supply potential is superposed on a diffusion layer serving as a guard ring at a boundary portion between a P channel region and an N channel region in the center of a cell so as to be superposed thereon. The first layer wiring is provided to supply power to the diffusion layer, and the first layer wiring is also used as a power supply line for supplying power to the transistor, and the diffusion layers of the guard rings at the upper and lower ends of the cell remain unchanged. As a result, by removing the first layer wiring, which has been used as a power supply line in the related art, this portion can be used as a signal wiring area, and a first cell is provided.

Further, in the semiconductor integrated circuit device according to the present invention, the first cell row is arranged such that vertically opposed cells have channel regions of the same conductivity type facing each other.

Further, the semiconductor integrated circuit device according to the present invention has two or more above-mentioned first cell rows arranged vertically.
On the left and right of each of these cell rows, the first connected to the power line
A cell row end cell having a structure in which a layer wiring is superposed on a diffusion layer and the first layer wiring and the diffusion layer are electrically connected by a contact is arranged, and a power supply is provided around the P channel region or the N channel region of the entire cell row. It is surrounded by a guard ring formed of a diffusion layer having a potential, and the same portion except the upper and lower ends of the cell row is surrounded by each power supply line formed by the first layer wiring.

A semiconductor integrated circuit device according to the present invention is
A first layer wiring for sending a power supply potential is arranged in a diffusion layer serving as a guard ring at the boundary between the P channel region and the N channel region at the center of the cell, and power is supplied to the diffusion layer from the first layer wiring. The layer wiring is also used as a power supply line for supplying power to the transistor, and the first layer wiring and the guard ring diffusion layer, which were used as the conventional power supply line at the upper and lower ends of the cell, are deleted to make the cell area smaller by that amount. It has a cell.

Further, in the semiconductor integrated circuit device according to the present invention, the second cells are arranged such that vertically opposed cells have channel regions of the same conductivity type facing each other.

Further, the semiconductor integrated circuit device according to the present invention has two or more above-mentioned second cell rows arranged vertically.
On the left and right of each cell row, the first layer wiring connected to the power supply line is overlapped with the diffusion layer, and the cell row end cells having the structure in which the first layer wiring and the diffusion layer are electrically connected by the contact are arranged. Around the P-channel region or N-channel region,
Except for the sides in contact with the wiring regions at the upper and lower ends of the cell, each power supply line is formed by the first layer wiring and the guard ring is formed by the diffusion layer having the power supply potential.

In the semiconductor integrated circuit device according to the present invention, the transistor included in the cell is formed by expanding the transistor outside the frame of the cell, has a large transistor width, and has a large driving capability. The wiring, contact, and through hole used for the transistor are arranged in the cell so as not to obstruct the wiring area.

Further, in the semiconductor integrated circuit device according to the present invention, the second cell row is arranged such that vertically opposed cells have channel regions of the same conductivity type facing each other, and the cell rows facing each other have the same channel type. A common P channel region or N channel region is formed by using the channel region and a signal wiring region sandwiched between them as one channel region, and the periphery of the P channel region or N channel region including the guard ring at the center of the cell is formed. Is surrounded by a guard ring made of a diffusion layer having a power supply potential.

Also, in the semiconductor integrated circuit device according to the present invention, the transistors included in each of the cell rows except the uppermost row and the lowermost row are expanded to outside the frame of the cell to have a large transistor width. In addition, the wiring, contact, and through hole used for the transistor are arranged in the cell so as not to obstruct the wiring region.

[0020]

In the first cell according to the present invention, the portion where the first layer wiring, which is the conventional power supply line at the upper and lower ends of the cell, is deleted, while having the conventional effect of preventing the latch-up by the guard ring. The chip area can be reduced accordingly.

Further, in the first cell arrangement according to the present invention, since the channel regions of the same conductivity type face each other in the upper and lower cell columns, latch-up due to the P channel region and the N channel region being adjacent to each other between the cell columns. There is no cause for it.

Further, cell row end cells provided on the left and right of the first cell row in the present invention, and a guard ring formed of a diffusion layer having a power supply potential surrounding the P channel region or the N channel region of the entire cell column, and The power supply line by the first layer wiring surrounding the same portion except the upper and lower ends of the cell row acts as a guard ring surrounding each of the plurality of first cell rows,
Moreover, by using the first cell, the chip area is small, and there is no cause for latch-up due to the P channel region and the N channel region being adjacent to each other between the cell columns.

In the second cell of the present invention, the guard ring has the conventional effect of preventing latch-up with respect to the inside of the cell, and the first layer wiring and the guard ring, which are the conventional power supply lines at the upper and lower ends of the cell, are provided. The cell area can be reduced as much as the diffusion layer can be eliminated.

In the second cell arrangement according to the present invention, since the channel regions of the same conductivity type face each other in the upper and lower cell columns, the latch-up due to the P channel region and the N channel region being adjacent to each other between the cell columns. There is no cause for it.

Further, the first layer surrounding the cell row end cells provided on the left and right of the second cell row and the P channel region or the N channel region of the entire cell row except the upper and lower ends of the cell row in the present invention. The power line by wiring has a plurality of second
Which acts as a guard ring surrounding each of the cell rows and uses the second cells to reduce the chip area, and causes the latch-up due to the P channel region and the N channel region being adjacent to each other between the cell columns. Disappears.

Further, the transistors included in the cell row in the present invention are formed to extend outside the frame of the cell, have a large transistor width, and have a large driving capability. Since the through holes are arranged in the cell so as not to obstruct the wiring area, a transistor having a large driving capability can be obtained.

The cell arrangement of the second cell row in which the upper and lower cell rows face each other in the channel regions of the same conductivity type according to the present invention is performed by diffusing the first layer wiring and the guard ring which are the conventional power supply lines at the upper and lower ends of the cell. Since the layers are deleted, the arrangement of the cell columns is such that one common P channel region or N channel is formed by the same channel region of each cell facing each other between the upper and lower cell columns and the signal wiring region between them. Regions can be formed, and this arrangement eliminates the factor that causes latch-up between cell columns.

In addition, the cell column end cells provided on the left and right of the cell column in the present invention, the diffusion layer having the power supply potential by connecting the cell column end cells across the wiring region in the vertical direction, and the signal wiring region are formed in the same portion. The formed first layer wiring acts as a guard line surrounding the periphery of the P channel region or the N channel region including the signal wiring region over the entire cell column.

Further, the transistors included in each cell row except the cell row at the uppermost end and the cell row at the lowermost end in the present invention are:
It is assumed that the transistor is formed to extend outside the frame of the cell, has a large transistor width, and has a large driving capability, and that wirings, contacts, and through holes used for the transistor are provided in the cell so as not to obstruct the wiring region. Since they are arranged, a transistor with a large driving capability can be obtained.

[0030]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. 1 is a pattern diagram of an inverter cell which is a first cell 10 in a semiconductor integrated circuit device according to a first embodiment of the present invention, and FIG.
It is a figure which shows the arrangement wiring which used 0. Reference numerals that are the same as those in FIGS. 7 and 8 are the same as those in the drawings.

In FIGS. 1 and 2, in the first cell 10, the diffusion layers 5d, 5 of the guard ring in the center of the cell are used.
e or 4d, 4e, which is also necessary for supplying power to the first layer wirings 6a and 6b in the center of the cell, is also used as a power supply line for supplying power to the diffusion layers 4a and 5a of the transistor. To the source 4a of the NMOS transistor from the first power supply line 6a using the first layer wiring 6j and the contact 8c, and to the source 5a of the NMOS transistor from the second power supply line 6b to the first layer wiring 6k.
And power is supplied using the contact 8d.

In addition, in FIG. 2 showing the arrangement and wiring using the first cell 10, the cell row ends of the upper and lower first cell rows 11 are similar to those in the conventional example of FIG. By arranging the first layer wiring 12 connected to the power supply line on the diffusion layer 13 on the left and right sides and placing the cell row end cells 15 configured to make them conductive by the contacts 14, the N well 1 and the P well 2 of the entire cell row are arranged. The periphery is surrounded by the power supply lines 6a, 6b, 12 by the first layer wiring and the guard ring by the diffusion layer 13 having the power supply potential. Cell row 11
In the inter-wiring region 50, the wiring 16 is used to perform wiring between the upper and lower cells 10.

In the first embodiment, by adopting the above-mentioned configuration as the cell configuration, the first layer wirings 6e and 6f at the upper and lower ends of the cell, which are the power supply lines in the conventional cell of FIG. 7, are formed.
Since this is unnecessary, it can be deleted, and this portion, that is, the portion of the first layer wiring on the diffusion layers 5c and 4c can be used as a signal wiring region. Further, the guard ring (diffusion layers 5d, 5e or 4d, 4e, 5c, 4c, 13) of the first cell 10 is provided in the P channel region 1
Enclosing the N-channel region 2 and the N-channel region 2 respectively has the effect of preventing the latch-up that occurs between the P-channel region 1 and the N-channel region 2 by the same action as in the conventional case. In addition, since a part of the cell (diffusion layer 5c or 4c) can be used as a signal wiring region, the chip area can be reduced as compared with the case of using a cell having a conventional latch-up prevention guard ring.

Example 2. FIG. 3 is a diagram showing the layout and wiring in the semiconductor integrated circuit device according to the second embodiment of the present invention, which uses the first cell 10 described above. In the figure, in the cell rows arranged vertically, the same channel regions of cells facing each other vertically (P channel region 1 and P channel region 1 or N channel region 2 and N channel region 2) face each other. It is located in. To the left and right of the cell row,
The cell row end cell 15 is placed and the N wells 1 and P of the entire cell row are placed.
Surrounding the well 2 with each power supply line by the first layer wiring,
In the wiring region 50 between the cell rows 11, the wiring ring is surrounded by a guard ring formed of a diffusion layer having a power supply potential.
Wiring between the upper and lower cells 10 using the wiring 16 is the same as in the first embodiment.

In the semiconductor integrated circuit device of the second embodiment, the guard ring of the first cell 10 has an effect of preventing latch-up by the same operation as the conventional one, and the first cell 10 is used. In addition to the effect of the first embodiment that the chip area can be reduced, the same channel regions of the upper and lower cell rows (P channel region 1 and P channel region 1 or N channel region 2) are further formed.
And the N channel region 2) face each other, so that there is an effect that latch-up does not occur due to the P channel region and the N channel region being adjacent to each other between the upper and lower cells when viewed in the vertical direction in the drawing.

Example 3. FIG. 4 is a pattern diagram of an inverter cell which is the second cell 20 in the semiconductor integrated circuit device according to the third embodiment of the present invention, and FIG. 5 is a diagram showing a layout wiring using the second cell 20. .

In the second cell 20 of the third embodiment shown in FIG. 4, power is supplied to the transistor by the first cell 10 described above.
Similarly to the above, the first layer wirings 6a and 6b are arranged on the guard ring in the center of the cell so as to overlap the guard ring, supply the power supply potential to the diffusion layer forming the guard ring, and 6a and 6b are also used as a power supply line for supplying power to the transistors. As a result, the first layer wirings 6e and 6f at the upper and lower ends of the cell, which are the power supply lines in the conventional cell of FIG. 7, are removed, and the diffusion layers 5c and 4c of the guard ring in this portion are also removed. Therefore, this portion can be used as a signal wiring region, and a cell having a smaller area can be obtained.

Further, in FIG. 5 showing the layout and wiring using the second cell 20, the first layer connected to the power supply line is provided on the left and right of the cell row at the cell row ends of the upper and lower second cell rows 21. Placing the wiring 12 on the diffusion layer 13 and placing the cell row end cell 15 configured to make them conductive by the contact 14, and in the wiring region 50 between the cell rows 21, by using the wiring 16 between the upper and lower cells 20. Wiring is
This is similar to Embodiments 1 and 2 above.

In the semiconductor integrated circuit device of the third embodiment, the second cell 20 does not have a guard ring at the upper and lower ends of the cell, but a guard ring (diffusion layer 5) at the center of the cell.
d, 5e or 4d, 4e) makes it possible to prevent latch-up that occurs between the P-channel region 1 and the N-channel region 2; The same action as the conventional one has almost the same latch-up prevention effect. Further, since the cell area is smaller than that of the first cell 10 of the conventional example and the first embodiment, the chip area of the semiconductor integrated circuit device can be further reduced.

Example 4. FIG. 6 shows the second cell 20 in the semiconductor integrated circuit device according to the fourth embodiment of the present invention.
It is a figure which shows arrangement | positioning wiring using. In the figure, in the cell rows 20 arranged vertically, the same channel regions (P channel region 1 and P channel region 1 or N channel region 2 and N channel region 2) of cells facing each other vertically face each other. To arrange. The common channel region 1 or 2 facing each other and the signal wiring region 51 or 52 sandwiched therebetween are combined to form a common well 100 or 200 as one channel region. The periphery of the well 100 or 200 is surrounded by a guard ring formed by the diffusion layer 13 having a power supply potential.

In the semiconductor integrated circuit device according to the fourth embodiment as described above, the second cell 2 is used as in the third embodiment.
By using 0, the chip area can be further reduced. Further, the guard ring of the second cell 20 has substantially the same latch-up prevention effect on the inside of the cell by the same action as in the conventional case, and further, the same channel region where cell rows arranged vertically are opposed to each other. Are connected by a common well 100 or 200, which is surrounded by a guard ring including a diffusion layer 13, so that there is no cause for latch-up between the upper and lower cells as in the case of the second embodiment. Has the effect that
As compared with the case of the first embodiment of FIG. 2 and the third embodiment of FIG. 5, a better latch-up prevention effect can be obtained.

Example 5. Further, in the second cell in which the diffusion layers of the guard rings at the upper and lower ends of the cell are also removed, the transistor can be expanded to the outside of the cell frame, so that the transistor width can be increased to increase the driving capability without changing the chip area. You can

FIG. 14 is a pattern diagram of an inverter cell which is the third cell 30 in the semiconductor integrated circuit device according to the fifth embodiment of the present invention, and FIG. 15 shows a layout wiring using the third cell. FIG.

In the third cell 30 of the present fifth embodiment shown in FIG. 14, the power supply to the transistor is performed on the guard ring in the center of the cell by overlapping the guard ring in the same manner as the second cell 20. The first layer wirings 6a and 6b are provided to supply a power supply potential to the diffusion layer forming the guard ring, and the first layer wirings 6a and 6b are also used as power supply lines for supplying power to the transistors. To do. And this
In the conventional cell of FIG. 7, the first layer wirings 6e and 6f at the upper and lower ends of the cell, which were the power supply lines, are deleted, and the diffusion layers 5c and 4c of the guard ring in this portion are also deleted. This portion can be used as a signal wiring region, and a cell having a smaller area can be obtained.

Further, in the second cell 30 of the fifth embodiment shown in FIG. 14, the diffusion layers 4a, 4b and the diffusion layers 4a and 4b forming the transistor are provided while having the same configuration and effect as the second cell 20. 5a and 5b are expanded to the outside of the cell frame, and wirings, contacts, and through holes used for transistors are arranged in the cell so as not to obstruct the wiring region. In the semiconductor integrated circuit device of the fifth embodiment as described above, the driving ability can be greatly improved as compared with the conventional case without changing the chip area.

The third cell 30 can be used to form a semiconductor integrated circuit device having the same structure as that of the second cell 20. In FIG. 15 showing the layout and wiring using the third cell 30, the first layer wiring 12 connected to the power supply line is provided on the left and right of the cell row at the cell row ends of the upper and lower third cell rows 31. Cell row end cell 15 having a structure in which the cells are stacked on 13 and electrically connected by a contact 14.
And wiring between the upper and lower cells 30 using the wiring 16 in the wiring region 50 between the cell rows 31 is the same as in the third and fourth embodiments.

In the semiconductor integrated circuit device of the fifth embodiment, the third cell 30 does not have a guard ring at the upper and lower ends of the cell, but a guard ring (diffusion layer 5) at the center of the cell.
d, 5e or 4d, 4e) makes it possible to prevent latch-up between the P-channel region 1 and the N-channel region 2 and, although not so much as in the first and second embodiments, With respect to, the same effect as in the conventional case can be obtained and a similar effect of preventing latch-up can be obtained. Further, since the cell area is smaller than that of the first cell 10 of the conventional example and the first embodiment, the chip area of the semiconductor integrated circuit device can be further reduced. Further, since the cell 30 in which the transistor is extended to the outside of the cell frame is used, the driving ability can be greatly improved without changing the chip area.

Example 6. FIG. 16 is a diagram showing layout and wiring in the semiconductor integrated circuit device according to the sixth embodiment of the present invention, which uses the third cell 30. In the figure, in the cell row 30 arranged vertically and the cell rows 20 provided at the upper and lower ends of the plurality of cell rows, the same channel region of cells vertically facing each other (P channel region 1 and P channel region 1 are , Or the N channel region 2 and the N channel region 2) are arranged so as to face each other. In addition, the same channel region 1 or 2 facing each other and the signal wiring region 53 or 54 sandwiched therebetween are combined to form a common well 300 or 40 as one channel region.
Form 0. The periphery of the well 300 or 400 is surrounded by a guard ring formed by the diffusion layer 13 having a power supply potential.

In the semiconductor integrated circuit device of the sixth embodiment as described above, the third cell 30 is used in the cell line except the uppermost end and the lowermost end of the plurality of cell lines forming the semiconductor integrated circuit device. As a result, similar to the fifth embodiment, there is an effect that the driving area of the transistor can be improved and the chip area can be further reduced. In addition, the guard ring of the third cell 30 has substantially the same latch-up prevention effect on the inside of the cell by the same action as in the conventional case, and further, the same channel region where the vertically aligned cell rows face each other. Are connected by a common well 300 or 400, which is surrounded by a guard ring including a diffusion layer 13, so that there is no cause for latch-up between the upper and lower cells as in the case of the fourth embodiment. As compared with the case of the first embodiment of FIG. 2, the third embodiment of FIG. 5, and the fifth embodiment of FIG. 15, a better effect of preventing latch-up is obtained. To be

[0050]

As described above, according to the semiconductor integrated circuit device of the present invention, the P channel region at the cell center and the N channel region are formed.
A power supply line for arranging a first-layer wiring on the guard ring region arranged along the boundary of the channel region, supplying a power supply potential to the first-layer wiring, and supplying the first-layer wiring to a transistor. It is also used as
Since the power supply line by the layer wiring is not provided and only the guard ring is provided, and the cells are formed by using the area of the first layer wiring at the upper and lower ends of the cell as the signal wiring area, the conventional latch is provided by the guard ring. While having the effect of preventing up, the first layer wiring, which was the conventional power supply line at the upper and lower ends of the cell, or the part where the diffusion layer of the guard ring is removed is used for the signal wiring area. There is an effect that the chip area can be reduced and the cell can be highly integrated.

Further, according to the semiconductor integrated circuit device of the present invention, since the cell rows arranged vertically are arranged such that the channel regions of the same conductivity type face each other, the P channel region and the N channel region are arranged between the cell rows. Adjacent to the channel region has an effect of preventing latch-up from occurring.

Further, according to the semiconductor integrated circuit device of the present invention, the first cell row having two or more rows of the first cell rows arranged vertically is provided, and the first layer connected to the power supply line is provided on the left and right of each cell row. A cell row end cell having a structure in which a wiring is superposed on a diffusion layer and the first wiring and the diffusion layer are electrically connected by a contact is arranged, and a power supply potential is provided around the P channel region or the N channel region of the entire cell column. Since it is surrounded by a guard ring made of a diffusion layer having the same structure, and the same portion except the upper and lower ends of the cell row is surrounded by each power supply line formed by the first layer wiring, the P channel region and the N channel region are adjacent to each other between the upper and lower cells. Therefore, there is an effect that it is possible to eliminate the occurrence of latch-up.

Further, according to the semiconductor integrated circuit device of the present invention, the first layer wiring for sending the power supply potential is arranged in the diffusion layer which becomes the guard ring at the boundary portion between the P channel region and the N channel region in the center of the cell. The first layer wiring and the guard ring, which are provided to supply power to the diffusion layer and also use the first layer wiring as a power supply line for supplying power to the transistor, which is the conventional power supply line at the upper and lower ends of the cell. Since the second diffusion layer is removed so that the second cell has a smaller cell area by that amount, the semiconductor integrated circuit can be constructed with a smaller chip area than the case where the first cell is used.

Further, according to the semiconductor integrated circuit device of the present invention, the second cells are arranged such that the cells facing each other in the vertical direction have channel regions of the same conductivity type facing each other. Has an effect that it is possible to prevent the latch-up from occurring because the channel regions of the same conductivity type face each other and the P channel region and the N channel region are adjacent to each other between the cell columns.

Further, according to the semiconductor integrated circuit device of the present invention, it has two or more above-mentioned second cell rows arranged vertically, and the first layer wiring connected to the power supply line is provided on the left and right of each cell row. A cell column end cell having a structure in which the first layer wiring and the diffusion layer are electrically connected to each other by overlapping with a diffusion layer is arranged, and the periphery of the P channel well or the N channel well of the entire cell column is arranged at the upper and lower ends of the cell. Since each side is connected to the power supply line formed by the first layer wiring and the guard ring formed by the diffusion layer having the power supply potential, except for the side in contact with the wiring region of
The diffusion layer and the first layer wiring act as a guard ring that surrounds each of the plurality of second cell columns, and by using the second cell, the chip area is small, and P
Since the channel region and the N channel region are adjacent to each other, it is possible to prevent latch-up from occurring.

Further, according to the semiconductor integrated circuit device of the present invention, the transistor included in the cell is formed by extending it outside the frame of the cell, has a large transistor width, and has a large drivability. Since the wiring, contact, and through hole used for the transistor are arranged in the cell so as not to obstruct the wiring region, it is possible to obtain a semiconductor integrated circuit device having a transistor with a large driving capability. There is.

Further, according to the semiconductor integrated circuit device of the present invention, the channel regions of the same conductivity type, which are opposed to each other in the upper and lower cells of each cell row, are aligned with the signal wiring regions sandwiched therebetween. And one channel region, and on the left and right of each cell row, the first
Arranging cell row end cells having a structure in which the first layer wiring and the diffusion layer are electrically connected to each other by stacking the layer wiring on the diffusion layer,
Further, a diffusion layer having a power supply potential is provided by vertically crossing the signal wiring region and connecting the upper and lower cell column end cells to each other, thereby providing a P channel region or an N-channel region including the signal wiring region over the entire cell column. Surround the periphery of the channel region with a guard ring made of a diffusion layer having a power supply potential,
Since the same portion except for the signal wiring region is surrounded by the power supply lines of the first layer wiring, the channel regions of the same conductivity type of the cells facing each other between the upper and lower cell columns and the signal wiring region between them are provided. With, it is possible to form one common P-channel region or N-channel region, and this arrangement has an effect that latch-up between cell columns can be prevented.

Further, according to the semiconductor integrated circuit device of the present invention, the transistors included in each of the cell rows except the uppermost row and the lowermost row are formed by expanding them outside the cell frame. It has a transistor width and a large driving capability, and the wiring, contact, and through hole used for the transistor are arranged in the cell so as not to obstruct the wiring area. The transistors included in the cell rows at the uppermost and lowermost ends are formed to extend outside the frame of the cell, have a large transistor width, and have a large driving capability, and wiring, contacts, and Since the through hole is placed in the cell so as not to obstruct the wiring area, it has a transistor with a large driving capability. There is an effect that it is possible to obtain a body integrated circuit device.

[Brief description of drawings]

FIG. 1 is a diagram showing a pattern of a first cell in a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of placement and wiring using the first cell in the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an example of placement and wiring using the first cell in a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a pattern of a second cell in the semiconductor integrated circuit device according to the third embodiment of the present invention.

FIG. 5 is a diagram showing an example of layout wiring using a second cell in a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIG. 6 is a diagram showing an example of placement and wiring using a second cell in a semiconductor integrated circuit device according to a fourth embodiment of the present invention.

FIG. 7 is a pattern diagram of cells in a conventional semiconductor integrated circuit device having a guard ring.

FIG. 8 is a diagram showing placement and wiring of cells in a conventional semiconductor integrated circuit device.

FIG. 9 is a pattern diagram of a cell without a conventional guard ring.

10 is a diagram showing a vertical cross section of the cell of FIG. 9. FIG.

11 is a diagram showing a vertical cross section of the cell of FIG. 7. FIG.

12 is a diagram showing a circuit of the parasitic bipolar transistor of FIG.

13 is a diagram showing a circuit of the parasitic bipolar transistor of FIG.

FIG. 14 is a diagram showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 15 is a diagram showing an example of placement and wiring using a second cell in a semiconductor integrated circuit device according to a fifth embodiment of the present invention.

FIG. 16 is a diagram showing an example of placement and wiring using a second cell in a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

[Explanation of symbols]

 1 P channel region (N well) 2 N channel region (P well) 4 P + diffusion layer 5 N + diffusion layer 6a First power supply line 6b Second power supply line 10 First cell 11 Cell of first cell Row 13 Diffusion layer (guard ring) 15 Cell row end cell 20 Second cell 21 Second cell cell row 30 Third cell 31 Third cell cell row 50 Wiring area 100 P channel area (N well) 200 N channel region (P well)

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[Procedure amendment]

[Submission date] February 22, 1994

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 5

[Correction method] Change

[Correction content]

[Figure 5]

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 6

[Correction method] Change

[Correction content]

[Figure 6]

[Procedure 3]

[Document name to be corrected] Drawing

[Correction target item name] Figure 15

[Correction method] Change

[Correction content]

FIG. 15

Claims (9)

[Claims] 1. A CMOS semiconductor integrated circuit device having a guard ring for preventing latch-up by a diffusion layer having a power supply potential along its periphery in each region of a P-channel region and an N-channel region in the cell, A first layer wiring is provided so as to overlap the guard ring region arranged along the boundary between the central P channel region and the N channel region, and a power supply potential is supplied to the first layer wiring. It is also used as a power supply line for supplying power to the cell, the power supply line by the first layer wiring is not provided at the upper and lower ends of the cell, only the guard ring is provided, and the area of the first layer wiring at the upper and lower ends of the cell is used as the signal wiring area. A semiconductor integrated circuit device comprising: 2. The semiconductor integrated circuit device according to claim 1, wherein there are two or more cell rows arranged vertically, and the cells facing each other are arranged such that channel regions of the same conductivity type face each other. A semiconductor integrated circuit device comprising: 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein there are two or more cell rows arranged vertically, and a diffusion layer is provided on the left and right of each cell row and connected to a power supply line. Over,
A cell row end cell having a structure in which both of them are made conductive by a contact is arranged, and a P channel region or N cell of the entire cell row is arranged.
A semiconductor integrated circuit device, characterized in that the periphery of the channel region is surrounded by a guard ring formed of a diffusion layer having a power supply potential, and the same portion except the upper and lower ends of the cell row is surrounded by each power supply line formed by the first layer wiring. 4. A CMOS semiconductor integrated circuit device having a guard ring for preventing latch-up by a diffusion layer having a power supply potential along its periphery in each region of a P channel region and an N channel region in the cell, A first layer wiring is provided so as to overlap the guard ring region arranged along the boundary between the central P channel region and the N channel region, and a power supply potential is supplied to the first layer wiring. It also serves as a power supply line for supplying power to the
A semiconductor integrated circuit device having a cell not provided with a diffusion layer of a guard ring. 5. The semiconductor integrated circuit device according to claim 4, wherein there are two or more cell rows arranged vertically, and the cells facing each other are arranged such that channel regions of the same conductivity type face each other. A semiconductor integrated circuit device comprising: 6. The semiconductor integrated circuit device according to claim 4 or 5, wherein there are two or more cell rows arranged vertically, and a first layer wiring connected to a power supply line is formed on a diffusion layer on the left and right of each cell row. Overlap
A cell row end cell having a structure in which both of them are made conductive by a contact is arranged, and a P channel region or N cell of the entire cell row is arranged.
It is characterized in that the periphery of the channel region is surrounded by each power supply line formed by the first layer wiring and a guard ring formed by a diffusion layer having a power supply potential, except for the sides in contact with the wiring regions at the upper and lower ends of the cell. Semiconductor integrated circuit device. 7. The semiconductor integrated circuit device according to claim 4, wherein the transistor included in the cell has a large transistor width formed by expanding outside the frame of the cell, and has a large driving capacity. A semiconductor integrated circuit device having a capability, wherein the wiring, contact, and through hole used for the transistor are arranged in the cell so as not to obstruct the wiring region. 8. The semiconductor integrated circuit device according to claim 5, wherein the channel regions of the same conductivity type, which are opposed to each other in the upper and lower cells of each cell row, and the signal wiring region sandwiched therebetween are combined. A cell row end cell having a structure in which a first layer wiring connected to a power supply line is overlapped with a diffusion layer on the left and right of each cell row as one channel region and the two are electrically connected by a contact, and the above-mentioned signal is provided. Of the P-channel region or the N-channel region including the signal wiring region over the entire cell column by providing the diffusion layer having the power supply potential across the wiring region of the above and below and connecting the upper and lower cell column end cells. It is characterized in that the periphery is surrounded by a guard ring formed of a diffusion layer having a power supply potential, and the same portion except the signal wiring area is surrounded by each power supply line formed by the first layer wiring. The semiconductor integrated circuit device. 9. The semiconductor integrated circuit device according to claim 8, wherein the transistors included in each cell row except the uppermost row and the lowermost row are formed to extend outside the cell frame and have a large transistor width. The semiconductor integrated circuit device is characterized in that the wiring, contact, and through hole used for the transistor are arranged in the cell so as not to obstruct the wiring region. .