JPH04309264A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase design freedom in the placement of cells and routing by constituting a composite cell which can be constituted of either two kinds of bipolar transistor elements or one of MOS transistor elements in one cell. CONSTITUTION:An N<+>-type diffusion layer 10 is provided as the emitter of an NPN transistor 16 and P<+>-type diffusion layers 14a-14c which become the source-drain area of a P-channel MOS transistor 15 and base area of a lateral PNP transistor 17 are provided in alignment with a gate electrode 8. As a result, a cell which can constitute a total of three kinds of transistor elements, namely, the P-channel MOS transistor 15, NPN transistor 16, and lateral PNP transistor 17 can be formed in one field oxide film 18. Therefore, design freedom in the placement of cells and routing can be increased.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to semiconductor integrated circuits.
In particular, the present invention relates to a semi-custom semiconductor integrated circuit (hereinafter referred to as a semi-custom LSI) in which a plurality of types of transistor elements can be selected by changing contact and wiring patterns.

0002

[Prior Art] In conventional semi-custom LSIs, a base substrate on which a plurality of basic elements such as transistors, resistors, capacitors, etc. are arranged is prepared in advance, and wiring design and wiring formation after the contact formation process is performed. Since it is only necessary to carry out the process, an LSI with desired specifications can be obtained in a short delivery time.

In the conventional semi-custom LSI configuration method, multiple types of cells that can configure only one type of element are formed in advance on the base by arranging them in each field, and the desired configuration is performed after the contact process. The cells necessary to realize the circuit were selected and wired to form an LSI.

0004

[Problems to be Solved by the Invention] However, in the above-mentioned conventional semiconductor integrated circuit, only cells that can constitute only one type of element in one field are placed on the base, so it is difficult to select elements within one cell. Since the type of cell is determined and formed only in the base process, from the contact process onward, all you need to do is select the cells necessary to realize the desired circuit from among the multiple types of cells that have already been formed. Therefore, there was a limit to the degree of freedom in cell placement and wiring in wiring design.

[0005]

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes an N+ type buried layer provided on one main surface of a P type silicon substrate, and an N- type buried layer provided on the surface including the N+ type buried layer. an epitaxial layer, a field oxide film provided on the surface of the N-type epitaxial layer to partition an element formation region, a gate electrode provided on the element formation region via a gate oxide film, and a field oxide film aligned with the gate electrode. first and second P-type diffusion layers provided in the N-type epitaxial layer;
The device includes an N- type diffusion layer provided in the second P-type diffusion layer, and an N+ type diffusion layer provided in the N- type epitaxial layer and reaching the N+ buried layer.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are a schematic plan view and a cross-sectional view taken along the line A-A' showing a first embodiment of the present invention.

As shown in FIGS. 1A and 1B, an N+ type buried layer 2 is provided on one main surface of a P type silicon substrate 1, and an N+ type buried layer 2 is provided on one main surface of a P type silicon substrate 1.
An N- type epitaxial layer 3 is formed on the surface including the type buried layer 2.
form. Next, an N+ type diffusion layer 4 which will become a P channel MOS transistor region is formed in the N- type epitaxial layer 3.
a, an N+ type diffusion layer 4b which will serve as the collector extraction region of the NPN transistor and a base region of the lateral PNP transistor, a P type diffusion layer 6 which will serve as the base region of the NPN transistor, and a gate formed on the N+ type diffusion layer 4a. A gate electrode 8 of a P-channel MOS transistor is formed through an oxide film. After this, an N+ type diffusion layer 10 that will become the emitter of the NPN transistor is provided, and further aligned with the gate electrode 8, the source and drain regions of the P channel MOS transistor, the collector region and emitter region of the lateral PNP transistor, and the base region of the NPN transistor are formed. By providing P+ type diffusion layers 14a, 14b, and 14c, a P channel MOS transistor 15 and an NPN transistor 1 are formed in one field oxide film 18.
6. A cell can be formed in which three types of transistor elements, ie, the lateral PNP transistor 17, can be configured. In this cell, a necessary element can be selected from the three types of elements described above after the contact process, and a contact can be provided at the contact position and wired.

FIGS. 2(a) and 2(b) are a schematic plan view and a sectional view taken along the line B-B' showing a second embodiment of the present invention.

As shown in FIGS. 2A and 2B, a composite transistor is formed in the same manner as in the first embodiment, and a P channel MOS transistor 15 is formed in one field oxide film 18.
, an NPN transistor 16, and a lateral PNP transistor 17. The structure is the same as that of the first embodiment except that a gate electrode 8 and a P+ type diffusion layer 14b serving as the base region of the lateral PNP transistor are provided to surround the P+ type diffusion layer 14a serving as the collector of the lateral PNP transistor. This has the advantage of improving the electrical characteristics of the lateral PNP transistor 17.

[0011]

Effects of the Invention As explained above, the present invention provides a composite cell in which either two types of bipolar transistor elements or one type of MOS transistor element can be configured by changing the contacts and wiring patterns. By configuring the
Since a necessary element can be selected from among various types of transistor elements, there is an effect that the degree of freedom in cell placement and wiring in wiring design is increased.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view and a cross-sectional view taken along line A-A' showing a first embodiment of the present invention.

FIG. 2 is a schematic plan view and a sectional view taken along the line B-B' showing a second embodiment of the present invention.

[Explanation of symbols]

1 P type silicon substrate 2 N+ type buried layer 3 N- type epitaxial layer 4a, 4b N+ type diffusion layer 6 P type diffusion layer 8 Gate electrode 10 N+ type diffusion layer 14a, 14b, 14c P+ type diffusion layer 15
P-channel MOS transistor 16 NP
N transistor 17 Lateral PNP transistor 18
field oxide film

Claims (1)

[Claims] [Claim 1] N provided on one principal surface of a P-type silicon substrate.
a + type buried layer, an N- type epitaxial layer provided on the surface including the N+ type buried layer, a field oxide film for partitioning an element formation region provided on the surface of the N- type epitaxial layer, and the element A gate electrode provided on the formation region via a gate oxide film, and first and second P electrodes provided in the N- type epitaxial layer in alignment with the gate electrode.
A type diffusion layer, an N- type diffusion layer provided in the second P-type diffusion layer, and an N+ type diffusion layer provided in the N- type epitaxial layer and reaching the N+ buried layer. Features of semiconductor integrated circuits.