JPH0691199B2 - Semiconductor integrated circuit - Google Patents

Description

The present invention relates to a semiconductor integrated circuit, and more particularly to a Bi-MOS type semiconductor integrated circuit including a MOS transistor and a bipolar transistor.

[Conventional technology]

Conventionally, a Bi-MOS type semiconductor integrated circuit in which a MOS transistor and a bipolar transistor are integrated on one semiconductor chip has been used so that the MOS transistor has a large input impedance and the bipolar transistor has a high current driving capability. .

[Problems to be Solved by the Invention]

In most of the conventional Bi-MOS type semiconductor integrated circuits, the bipolar transistor and the MOS transistor are respectively formed in the island regions electrically insulated by the insulating separation layer and connected by the wiring. Therefore, there is a drawback that the area occupied by the chip becomes large. There is also a problem that the advantages and disadvantages of the characteristics of the bipolar transistor and the MOS transistor are maintained as they are, and the disadvantages are not improved.

[Means for Solving the Problems]

The semiconductor integrated circuit according to the present invention includes a buried layer of one conductivity type formed on a semiconductor substrate, a semiconductor layer of opposite conductivity type formed on the semiconductor substrate, and a semiconductor layer of opposite conductivity type in contact with the buried layer. A reverse-conductivity-type high-concentration region provided in a layer, a gate electrode provided on the surface of the reverse-conductivity-type semiconductor layer through an insulating film, and in the reverse-conductivity-type semiconductor layer below both sides of the gate electrode A MOS formed of the gate electrode and the two one-conductivity type regions existing on both sides of the gate electrode and having one one-conductivity type region formed in contact with the opposite conductivity type high concentration region. It is configured to include a transistor, and a bipolar transistor including the buried layer, the opposite conductivity type high concentration region, and one conductivity type region in contact with the opposite conductivity type high concentration region.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention.

The concentration is 5 × 10 ^{15 on} the P-type silicon substrate 1 with a specific resistance of 10Ω · cm.
/ cm ³ N-type diffusion layer 2 is formed, and the specific resistance is 1 Ω · cm on it.
The P-type epitaxial layer 3 is formed to a thickness of 1 μm.
P that contacts the N-type buried layer 2 in the epitaxial layer 3
The mold base region 4 is formed by using an ion implantation technique. A gate oxide film 5 having a thickness of 50 nm is formed on the surface of the epitaxial layer 3, and a gate electrode 6 made of polycrystalline silicon containing 10 ²¹ cm ⁻³ or more of phosphorus is formed thereon. The gate electrode length is 1 μm. Arsenic is ion-implanted by using this gate electrode 6 as a mask to form a junction depth of 0.5 μm and a concentration of 20 ²¹ / cm ³
The above N-type regions 7 and 8 are formed. The N-type region 7 is formed so as to be in contact with the P-type base region 7. Film thickness by CVD method
An interlayer insulating film 9 having a thickness of 0.5 μm is deposited, contact holes are formed by photolithography, and a power electrode 10 and an output electrode 11 for taking out an output are formed of Al-1% Si having a film thickness of 1 μm.

NPN with N type buried layer 2, P type base region 4 and N type region 7
A transistor is formed, and the gate electrode 6 and the N-type regions 7 and 8 are formed.
And form an N-channel MOS transistor.

In this way, the MOS transistor can be combined with the bipolar transistor.

With this combination, when the channel length of the MOS transistor becomes short, the substrate current of the MOS transistor becomes extremely large, and the drawbacks of the MOS transistor are eliminated,
Moreover, the advantages of the prior art are maintained.

〔The invention's effect〕

As described above, according to the present invention, the bipolar transistor is combined with the MOS transistor by providing the base region between the source region of the MOS transistor and the buried layer below, so that the high input impedance and the large current driving capability are provided. There is an effect that an active element having

In addition, the collector (or emitter) of the bipolar transistor and the drain of the MOS transistor are shared and the MOS
Since the transistor and the bipolar transistor are formed in the same island region, there is an effect that an insulating separation layer is not required, an occupied area can be significantly reduced, and an integration density can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention. 1 ... P-type silicon substrate, 2 ... N-type buried layer, 3 ... P
-Type epitaxial layer, 4 ... P-type base region, 5 ... Gate oxide film, 6 ... Gate electrode, 7,8 ... N-type region, 9
...... Interlayer insulation film, 10 …… Power supply electrode, 11 …… Output electrode.

Claims (1)

[Claims] 1. A buried layer of one conductivity type formed on a semiconductor substrate, a semiconductor layer of opposite conductivity type formed on the semiconductor substrate, and a semiconductor layer in contact with the buried layer in the semiconductor layer of opposite conductivity type. A reverse-conductivity-type high-concentration region provided, a gate electrode provided on the surface of the reverse-conductivity-type semiconductor layer through an insulating film, and one formed in the reverse-conductivity-type semiconductor layer below both sides of the gate electrode. Region having two one-conductivity-type regions in contact with the opposite-conductivity-type high-concentration region, and is composed of the gate electrode and the two one-conductivity-type regions existing below both sides thereof.
A semiconductor integrated circuit comprising: an S-transistor; a bipolar transistor including the buried layer, the opposite conductivity type high concentration region, and one conductivity type region in contact with the opposite conductivity type high concentration region.