JPH0380565A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance of a depletion layer and increase signal transmission speed, by arranging a low concentration N-type region between a P-type semiconductor substrate and a high concentration N-type burried layer. CONSTITUTION:After a surface protecting oxide film is formed on a main surface of a P-type semiconductor substrate 101, phosphorus is introduced by ion-implantion method, and a low concentration N-type region 102 is formed by heat treatment. Boron is introduced by ion-implantation method, and a P-type buried layer 103 is formed by heat treatment. After that, the surface protecting oxide film is eliminated, and an N-type epitaxial layer 104 is formed. By the same means as the forming of the buried layer, phosphorus and boron are introduced, and an N-type well 105 and a P-type well 106 are formed on the buried layer. A field oxide film 107 is formed by selective oxidation method. Hence the parasitic capacitance of the buried layer part is reduced, and signal transfer delay time can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a semiconductor device, and particularly to a structure for improving the electrical characteristics of a BiCMO8 type semiconductor device.

[Conventional technology]

FIG. 2(a) shows a conventional example of this type of semiconductor device.

This will be explained using (b). First, as shown in FIG. 2(a), an N-type buried layer 202 and a P-type buried layer 203 are formed on a P-type semiconductor substrate 201 made of silicon by known means, and then an N-type epitaxial layer 204 is formed. Stack. Next, as shown in FIG. 2(b), N
type well 205, P type well 20 on the P type buried layer 203
6 is formed, and a field oxide film 207 is formed by selective oxidation method.
will be established.

Thereafter, by known means, a gate oxide film 208, a gate electrode 209 made of polycrystalline silicon, a P-type source/drain region 210, an N-type source/drain region (not shown in the figure), and a height for reducing the collector resistance of the bipolar transistor are formed. A doped N-type region 211, a P-type region 212 for a base, an oxide film 213 for interlayer insulation, an emitter electrode 214 of a bipolar transistor using polycrystalline silicon, and an N-type region 215 for an emitter are formed. Next, the semiconductor device is completed by forming an interlayer insulating film, contact openings, aluminum electrodes for wiring, etc.

[Problem to be solved by the invention]

The conventional semiconductor device described above has an impurity concentration of 101016a.
High concentration (10”~
Since an N-type buried layer of 10" atoms/cnt) is formed, a depletion layer of about 1 μm spreads between the P-type semiconductor substrate and the N-type buried layer. Because of the highly concentrated N-type buried layer, The width of the depletion layer is narrow and a parasitic capacitance component is generated, which is one of the causes of increasing signal transmission delay time.

[Means to solve the problem]

The semiconductor device of the present invention includes a highly doped N-type buried layer provided in a P-type semiconductor substrate, a lightly doped N-type region provided at the bottom of the N-type buried layer, and a lightly doped N-type region formed on the top of the N-type buried layer. It has an N-type well. Therefore, the parasitic capacitance of the buried layer portion is reduced, and the signal transmission delay time can be reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) and 1(b) are longitudinal sectional views of an embodiment of the present invention.

First, as shown in FIG. 1(a), a surface protective oxide film (not shown in the figure) of 20 to 40 Ω is coated on the whole surface of a P-type semiconductor substrate 101 made of silicon and having a resistivity of 10 to 14 Ω.
After forming the N-type region 12 nm thick, phosphorus is introduced at a concentration of 1013 to 10" atoms/cnt using an ion implantation method, and a low concentration N-type region 12 is formed by heat treatment at about 1000°C.
form 0. Next, 10' of arsenic was added using the ion implantation method.
Introduced at a concentration of 5-101 aatoms/cnt, 1
A high concentration N-type buried layer 102 is formed by heat treatment at about OOO°C.
form. In this case, since the heat treatment for diffusing arsenic also progresses the diffusion of the previously introduced phosphorus, it is necessary to appropriately adjust the heat treatment time after the phosphorus implantation so that the low concentration N-type region 120 does not spread too much. Next, poron was implanted at 1013 to 10 ”atoms/cn by ion implantation method.
P-type buried layer 103 is introduced at a concentration of i and subjected to heat treatment.
form. Thereafter, the surface protective oxide film is removed, and an N-type epitaxial layer 104 is formed to a thickness of 1 to 2 μm. Next, as shown in FIG. 1(b), phosphorus at 1012 to 10101 sato/crA and poron at 1013 to 1014 atoms/cnf are introduced into the N-type well 105 and the P-type well by the same means as for forming the buried layer. 106 is formed on the buried layer, and a field oxide film 107 with a thickness of 500 to 600 nm is provided by selective oxidation. After this,
A gate oxide film 10 with a thickness of 15 to 30 nm is formed by known means.
8. Gate electrode 109 made of polycrystalline silicon. P-type source/drain region 110, N-type source/drain region (not shown), high concentration N-type region 111 for collector of bipolar transistor, P-type region for base 12,
An oxide film 113 for interlayer insulation, an emitter electrode 114 of a bipolar transistor using polycrystalline silicon, and an N-type region 115 for an emitter are formed. Thereafter, an interlayer insulating film, contact openings, wiring aluminum electrodes, etc. are formed, and the semiconductor device is completed.

Another embodiment of the invention will now be described.

As in the previous embodiment, after forming a lightly doped N-type region and a heavily doped N-type buried layer in a P-type semiconductor substrate, a P-type epitaxial layer is formed. Thereafter, an N-type well is formed on the N-type buried layer, and MOS transistors and bipolar transistors are formed in the same manner. In this case, since the P-type buried layer and the P-type well are not required, the number of steps can be significantly reduced.

〔Effect of the invention〕

As explained above, the present invention utilizes a P-type semiconductor substrate and a high concentration N.
By providing a lightly doped N-type region between the type buried layers, parasitic capacitance due to the depletion layer can be reduced and signal transmission speed can be increased.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are longitudinal sectional views of an embodiment of the present invention,
FIGS. 2(a) and 2(b) are longitudinal sectional views of a conventional example. 101.201...P-type semiconductor substrate, 102°202...N-type buried layer, 103,203...
...P type buried layer, 104,204...N type epitaxial layer, 105,205...N type well, 106°206...P type well, 120・
...Low concentration N-type region, 109,209...
・Gate electrode, 114°214...Emitter electrode.

Claims (1)

[Claims] A first semiconductor region of a second conductivity type with a high impurity density provided in at least a portion of a first conductivity type semiconductor substrate; a second semiconductor region, an epitaxial layer provided on the first conductivity type semiconductor substrate, and a third semiconductor region of a second conductivity type formed in the epitaxial layer so as to be in contact with at least one of the first semiconductor region. A semiconductor device comprising: