JP2884787B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2884787B2 JP2884787B2 JP3017249A JP1724991A JP2884787B2 JP 2884787 B2 JP2884787 B2 JP 2884787B2 JP 3017249 A JP3017249 A JP 3017249A JP 1724991 A JP1724991 A JP 1724991A JP 2884787 B2 JP2884787 B2 JP 2884787B2
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- conductivity type
- epitaxial layer
- impurity concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000009792 diffusion process Methods 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 13
- 239000012535 impurity Substances 0.000 claims description 12
- 239000010410 layer Substances 0.000 description 45
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- -1 boron ions Chemical class 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 238000007373 indentation Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
にＤＳＡ（ｄｉｆｆｕｓｉｏｎ ｓｅｌｆ−ａｌｉｇｎ
ｅｄ）構造の縦型ＭＯＳＦＥＴに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a DSA (diffusion self-align).
ed) The present invention relates to a vertical MOSFET having a structure.
【０００２】[0002]
【従来の技術】従来の半導体装置は、図２に示すよう
に、Ｎ+ 型シリコン基板１の上に設けたドレイン耐圧を
高めるためのＮ- 型エピタキシャル層３と、Ｎ- 型エピ
タキシャル層３に選択的に設けてＮ+ 型シリコン基板１
に達するＰ+ 型拡散層４と、 Ｐ+ 型拡散領域４に接続し
て設けたＰ型チャネル領域５と、Ｐ型チャネル領域５内
に設けたＮ+ 型ソース領域６とを有して形成されてい
る。 ここで、Ｐ+ 型拡散層４と、Ｎ+ 型シリコン基板
１との間に形成されるＰＮ接合により、ドレイン耐圧が
定まる。Ｎ+ 型ソース領域６およびＮ- 型エピタキシャ
ル層３と、Ｐ型チャネル領域５上にはゲート酸化膜７を
介して、多結晶シリコン層からなるゲート電極８が形成
されている。層間絶縁膜９は、ゲート酸化膜７及びゲー
ト電極８を被覆して形成され、その上に、ソース電極１
０が、Ｐ型チャネル領域５と、Ｎ+ 型ソース領域６に接
続して形成されている。ここで、Ｐ+型拡散層４とドレ
イン領域であるＮ+ 型半導体基板１が広い面積で直接接
合されているため、サージ等によりブレークダウンを生
じてもブレークダウン電流が局部的に集中せず、熱破壊
を生じ難い利点がある。Conventional semiconductor device, as shown in FIG. 2, N to improve the drain breakdown voltage which is provided on the N + -type silicon substrate 1 - -type epitaxial layer 3, N - -type epitaxial layer 3 Selectively provided N + type silicon substrate 1
Formed with a P + type diffusion layer 4, a P type channel region 5 connected to the P + type diffusion region 4, and an N + type source region 6 provided in the P type channel region 5. Have been. Here, the drain breakdown voltage is determined by the PN junction formed between the P + type diffusion layer 4 and the N + type silicon substrate 1. A gate electrode 8 made of a polycrystalline silicon layer is formed on the N + type source region 6 and the N − type epitaxial layer 3 and the P type channel region 5 via a gate oxide film 7. The interlayer insulating film 9 is formed to cover the gate oxide film 7 and the gate electrode 8, and the source electrode 1 is formed thereon.
0 is connected to the P-type channel region 5 and the N + -type source region 6. Here, since the P + -type diffusion layer 4 and the N + -type semiconductor substrate 1 serving as the drain region are directly joined to each other over a wide area, even if a breakdown occurs due to a surge or the like, the breakdown current does not concentrate locally. This has the advantage of hardly causing thermal destruction.
【０００３】[0003]
【発明が解決しようとする課題】この従来の半導体装置
では、Ｎ- 型エピタキシャル層２の厚さのばらつきによ
り、熱拡散によりＮ- 型シリコン基板１まで押し込まれ
ているＰ+ 型拡散層３とＮ+ 型シリコン基板１との接合
部でのＰ+ 型拡散層３の不純物濃度がばらつき、この不
純物濃度によって支配されているＮ+ 型シリコン基板１
とＰ+ 型拡散層３とのＰＮ接合の耐圧がばらつくといっ
た問題点があった。In this conventional semiconductor device, the P + -type diffusion layer 3 pushed into the N − -type silicon substrate 1 by thermal diffusion due to the variation in the thickness of the N − -type epitaxial layer 2. The impurity concentration of the P + -type diffusion layer 3 at the junction with the N + -type silicon substrate 1 varies, and the N + -type silicon substrate 1 is dominated by the impurity concentration.
And there is a problem that the withstand voltage varies the PN junction between the P + -type diffusion layer 3.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体装置は、
高不純物濃度の一導電型半導体基板の一主面に設けた逆
導電型の埋込層と、前記埋込層を含む表面に設けた低不
純物濃度の一導電型エピタキシャル層と、前記エピタキ
シャル層に設けて前記埋込層に達する高不純物濃度の逆
導電型拡散層と、前記逆導電型拡散層を含む前記エピタ
キシャル層の表面に設けたゲート絶縁膜上に設けたゲー
ト電極と、前記ゲート電極に整合し且つ前記逆導電型拡
散層に接続して前記エピタキシャル層に設けた逆導電型
のチャネル領域と、前記ゲート電極に整合して前記チャ
ネル領域に設けたソース領域とを有する。According to the present invention, there is provided a semiconductor device comprising:
A buried layer of the opposite conductivity type provided on one main surface of the one conductivity type semiconductor substrate having a high impurity concentration, a one conductivity type epitaxial layer having a low impurity concentration provided on the surface including the buried layer, and A high impurity concentration reverse conductivity type diffusion layer provided to reach the buried layer; a gate electrode provided on a gate insulating film provided on a surface of the epitaxial layer including the reverse conductivity type diffusion layer; The semiconductor device includes a channel region of the opposite conductivity type provided in the epitaxial layer so as to match and connected to the diffusion layer of the opposite conductivity type, and a source region provided in the channel region so as to match the gate electrode.
【０００５】[0005]
【実施例】次に、本発明について図面を参照して説明す
る。Next, the present invention will be described with reference to the drawings.
【０００６】図１は本発明の一実施例を示す半導体チッ
プの断面図である。FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.
【０００７】図１に示すように、不純物濃度２×１０18
ｃｍ-3程度にＳｂがドープされ比抵抗が約０．０１５Ω
・ｃｍのＮ+ 型シリコン基板１の一主面に選択的にホウ
素をイオン注入、あるいは拡散してＰ型埋込層２を形成
し、Ｐ型埋込層２を含む表面にＮ- 型エピタキシャル層
３を形成する。３０Ｖ耐圧を例にとると、Ｎ- 型エピタ
キシャル層３の不純物濃度は１．６×１０15ｃｍ-3程
度，比抵抗は０．４Ω・ｃｍ，厚さは約６．５μｍであ
り、Ｐ型埋込層２のピーク不純物濃度は２×１０16〜５
×１０16ｃｍ-3に選ばれる。As shown in FIG. 1, the impurity concentration is 2 × 10 18
Sb is doped to about cm -3 and the specific resistance is about 0.015Ω.
1 cm of N + -type silicon substrate 1 is selectively ion-implanted or diffused with boron to form P-type buried layer 2, and N − -type epitaxial layer is formed on the surface including P-type buried layer 2. The layer 3 is formed. Taking a 30V breakdown voltage as an example, the impurity concentration of the N − -type epitaxial layer 3 is about 1.6 × 10 15 cm −3 , the specific resistance is 0.4 Ω · cm, the thickness is about 6.5 μm, and the P-type The peak impurity concentration of the buried layer 2 is 2 × 10 16 to 5
× 10 16 cm -3 is selected.
【０００８】次に、Ｎ- 型エピタキシャル層３の表面
に、選択的にホウ素イオンをドーズ量１．４×１０14ｃ
ｍ-2，加速エネルギー７０ｋｅＶでイオン注入し、１２
００℃，４０分の埋込み拡散を行ない、Ｐ型埋込層２と
接続するＰ+ 型拡散層４を形成する。Next, boron ions are selectively deposited on the surface of the N − -type epitaxial layer 3 at a dose of 1.4 × 10 14 c.
ion implantation at m- 2 , acceleration energy 70 keV, 12
The buried diffusion is performed at 00 ° C. for 40 minutes to form a P + type diffusion layer 4 connected to the P type buried layer 2.
【０００９】次に、Ｐ+ 型拡散層４を含むＮ- 型エピタ
キシャル層３の表面を熱酸化してゲート酸化膜７を設
け、ゲート酸化膜７の上に多結晶シリコン層を堆積して
選択的にエッチングしゲート電極８を設ける。次に、ゲ
ート電極８をマスクとしてホウ素イオンをドーズ量１×
１０14ｃｍ-2，加速エネルギー７０ｋｅＶでイオン注入
し、１２００℃，６０分間の押込み拡散によりＰ+ 型拡
散層４と接続するＰ型チャネル領域５を形成する。次
に、Ｐ+ 型拡散層４の表面に選択的にリンイオンをドー
ズ量５×１０15ｃｍ-2，加速エネルギー８０ｋｅＶでイ
オン注入し、１０００℃，３０分間の押込み拡散により
ゲート電極８に整合したＮ+ 型ソース領域６を形成す
る。Next, the surface of the N − -type epitaxial layer 3 including the P + -type diffusion layer 4 is thermally oxidized to provide a gate oxide film 7, and a polycrystalline silicon layer is deposited on the gate oxide film 7 for selection. Etching to provide a gate electrode 8. Next, using the gate electrode 8 as a mask, boron ions are dosed at a dose of 1 ×.
Ion implantation is performed at 10 14 cm -2 and an acceleration energy of 70 keV, and a P-type channel region 5 connected to the P + -type diffusion layer 4 is formed by indentation diffusion at 1200 ° C. for 60 minutes. Next, phosphorus ions are selectively implanted into the surface of the P + -type diffusion layer 4 at a dose of 5 × 10 15 cm −2 and an acceleration energy of 80 keV, and aligned with the gate electrode 8 by indentation diffusion at 1000 ° C. for 30 minutes. An N + type source region 6 is formed.
【００１０】次に、ゲート電極８を含む表面にＰＳＧ膜
を形成して選択的に開孔部を設け、開孔部のＮ+ 型ソー
ス領域６及びＰ+ 型拡散層４と接続するソース電極１０
を形成する。Next, a PSG film is formed on the surface including the gate electrode 8 to selectively form an opening, and the source electrode connected to the N + type source region 6 and the P + type diffusion layer 4 in the opening. 10
To form
【００１１】[0011]
【発明の効果】以上説明したように本発明は、Ｎ+ 型半
導体基板の表面にＰ型埋込層を設けてＮ- 型エピタキシ
ャル層内に設けたＰ+ 型拡散層と接続することにより、
Ｎ- 型エピタキシャル層の厚さがばらついても、Ｐ+ 型
拡散層の形成条件を一定にしておけばＰ型埋込層の不純
物濃度は変わらなく、Ｎ+ 型シリコン基板１とＰ型埋込
層との接合部で形成されるＰＮ接合の耐圧を安定化でき
るという効果を有する。As described above, according to the present invention, a P-type buried layer is provided on the surface of an N + -type semiconductor substrate and connected to a P + -type diffusion layer provided in an N -- type epitaxial layer.
N - type even if the thickness of the epitaxial layer varies, the impurity concentration of the P-type buried layer if in the constant forming conditions P + -type diffusion layer is not changed, N + -type silicon substrate 1 and the P-type buried This has the effect of stabilizing the breakdown voltage of the PN junction formed at the junction with the layer.
【図１】本発明の一実施例を示す半導体チップの断面図
である。FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.
【図２】従来の半導体装置の一例を示す半導体チップの
断面図である。FIG. 2 is a cross-sectional view of a semiconductor chip showing an example of a conventional semiconductor device.
１ Ｎ+ 型シリコン基板 ２ Ｐ型埋込層 ３ Ｎ- 型エピタキシャル層 ４ Ｐ+ 型拡散層 ５ Ｐ型チャネル領域 ６ Ｎ+ 型ソース領域 ７ ゲート酸化膜 ８ ゲート電極 ９ 層間絶縁膜 １０ ソース電極REFERENCE SIGNS LIST 1 N + type silicon substrate 2 P type buried layer 3 N − type epitaxial layer 4 P + type diffusion layer 5 P type channel region 6 N + type source region 7 Gate oxide film 8 Gate electrode 9 Interlayer insulating film 10 Source electrode
Claims (1)
主面に設けた逆導電型の埋込層と、前記埋込層を含む表
面に設けた低不純物濃度の一導電型エピタキシャル層
と、前記エピタキシャル層に設けて前記埋込層に達する
高不純物濃度の逆導電型拡散層と、前記逆導電型拡散層
を含む前記エピタキシャル層の表面に設けたゲート絶縁
膜上に設けたゲート電極と、前記ゲート電極に整合し且
つ前記逆導電型拡散層に接続して前記エピタキシャル層
に設けた逆導電型のチャネル領域と、前記ゲート電極に
整合して前記チャネル領域に設けたソース領域とを有す
ることを特徴とする半導体装置。A buried layer of the opposite conductivity type provided on one main surface of the one conductivity type semiconductor substrate having a high impurity concentration, and a low impurity concentration one conductivity type epitaxial layer provided on a surface including the buried layer. A high impurity concentration reverse conductivity type diffusion layer provided in the epitaxial layer and reaching the buried layer; and a gate electrode provided on a gate insulating film provided on the surface of the epitaxial layer including the reverse conductivity type diffusion layer. A channel region of the opposite conductivity type provided in the epitaxial layer in alignment with the gate electrode and connected to the diffusion layer of the opposite conductivity type; and a source region provided in the channel region in alignment with the gate electrode. A semiconductor device characterized by the above-mentioned.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3017249A JP2884787B2 (en) | 1991-02-08 | 1991-02-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3017249A JP2884787B2 (en) | 1991-02-08 | 1991-02-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04256370A JPH04256370A (en) | 1992-09-11 |
| JP2884787B2 true JP2884787B2 (en) | 1999-04-19 |
Family
ID=11938679
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3017249A Expired - Fee Related JP2884787B2 (en) | 1991-02-08 | 1991-02-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2884787B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2208229A4 (en) | 2007-09-21 | 2011-03-16 | Fairchild Semiconductor | Superjunction structures for power devices and methods of manufacture |
| US20120273916A1 (en) | 2011-04-27 | 2012-11-01 | Yedinak Joseph A | Superjunction Structures for Power Devices and Methods of Manufacture |
| US8836028B2 (en) | 2011-04-27 | 2014-09-16 | Fairchild Semiconductor Corporation | Superjunction structures for power devices and methods of manufacture |
-
1991
- 1991-02-08 JP JP3017249A patent/JP2884787B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04256370A (en) | 1992-09-11 |
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