JPH0766398A - High withstand voltage semiconductor device - Google Patents

High withstand voltage semiconductor device

Info

Publication number
JPH0766398A
JPH0766398A JP5211322A JP21132293A JPH0766398A JP H0766398 A JPH0766398 A JP H0766398A JP 5211322 A JP5211322 A JP 5211322A JP 21132293 A JP21132293 A JP 21132293A JP H0766398 A JPH0766398 A JP H0766398A
Authority
JP
Japan
Prior art keywords
type
region
drain
source
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5211322A
Other languages
Japanese (ja)
Inventor
美朝 ▲高▼橋
Yoshitomo Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5211322A priority Critical patent/JPH0766398A/en
Publication of JPH0766398A publication Critical patent/JPH0766398A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To prevent deterioration of withstand voltage between a source and a drain and deterioration of reliability of a gate oxide film, by forming a P-type region on the surface of an N-type substrate just under an edge part on the drain side of a gate electrode. CONSTITUTION:After a field oxide film 2, a gate oxide film 3, and a gate electrode 4 are selectively formed in order, a P-type base region 5 is formed by ion implantation of boron and forced diffusion. Boron ions are implanted in a P-type region 6, and phosphorus ions are implanted in an N<+> type source region 7 and an N<+> type drain electrode 8. The P-type region 6, an N<+> type source region 7, and an N<+> type drain electrode 8 are formed by forced diffusion. An interlayer insulating film 11 is formed and a contact hole is opened. A source electrode 9 and a drain electrode 10 are selectively formed. Thereby deterioration of withstand voltage between a drain and a source and deterioration of reliability of the gate oxide film can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は横型半導体装置の特性改
善に関し、特にドレイン・ソース間及びドレイン・ゲー
ト間の高耐圧化に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvement of characteristics of a lateral type semiconductor device, and more particularly to high breakdown voltage between drain and source and between drain and gate.

【０００２】[0002]

【従来の技術】従来の横型半導体装置は図２に示す様に
Ｎ型基板１の表面側にゲート酸化膜３、ゲート電極４、
Ｐ型ベース領域５、Ｎ+ ソース領域７、Ｎ+ ドレイン領
域８、ソース電極９、ドレイン電極１０が選択的に形成
され、さらにＰ型ベース領域５とＮ+ ドレイン領域８と
の間には電界緩和層としてのＰ型領域６が設けられてい
た。（例えば特開昭５６−４５０７４号公報）また従来
の縦型半導体装置を図３に示すが、Ｎ型基板１の表面側
にそれぞれ対象的にフィールド酸化膜２、ゲート酸化膜
３、ゲート電極４、Ｐ型ベース領域５、Ｎ+ ソース領域
７、ソース電極９が選択的に形成され、さらにＰ型ベー
ス領域５に挟まれたＮ型基板１の表面にはやはりガード
リングとしてのＰ型領域６が設けられていた。（例えば
特開昭５７−１１５８６７）2. Description of the Related Art As shown in FIG. 2, a conventional lateral semiconductor device has a gate oxide film 3, a gate electrode 4, and a gate oxide film 3 on the surface side of an N-type substrate 1.
A P-type base region 5, an N + source region 7, an N + drain region 8, a source electrode 9 and a drain electrode 10 are selectively formed, and an electric field is formed between the P-type base region 5 and the N + drain region 8. The P-type region 6 as the relaxation layer was provided. A conventional vertical semiconductor device is shown in FIG. 3, for example, the field oxide film 2, the gate oxide film 3, and the gate electrode 4 are symmetrically provided on the surface side of the N-type substrate 1, respectively. , P-type base region 5, N + source region 7, and source electrode 9 are selectively formed, and on the surface of the N-type substrate 1 sandwiched by the P-type base region 5, the P-type region 6 as a guard ring is also formed. Was provided. (For example, JP-A-57-115867)

【発明が解決しようとする課題】これらの従来の半導体
装置ではガードリングとしてのＰ型拡散領域６は有して
いるもののゲート電極４のエッジ部には形成されていな
い。 このため半導体装置がオフしている時はゲート電
極４のエッジ部にドレインからの電界が集中し、ドレイ
ン・ソース間の耐圧がが劣化し（ゲート・ソース間はゼ
ロバイアス）、またゲート酸化膜の信頼性が低下すると
いう問題点があった。In these conventional semiconductor devices, the P-type diffusion region 6 as the guard ring is provided, but it is not formed at the edge portion of the gate electrode 4. Therefore, when the semiconductor device is off, the electric field from the drain is concentrated on the edge portion of the gate electrode 4, the breakdown voltage between the drain and the source deteriorates (zero bias between the gate and the source), and the gate oxide film is formed. However, there was a problem in that the reliability of

【０００３】[0003]

【課題を解決するための手段】本発明の半導体装置では
ゲート電極４のエッジ部へのドレイン電界の集中を防ぐ
ためゲート電極４のエッジ部直下のＮ型基板１の表面に
Ｐ型領域６を有している。In the semiconductor device of the present invention, a P-type region 6 is formed on the surface of the N-type substrate 1 immediately below the edge of the gate electrode 4 in order to prevent the concentration of the drain electric field at the edge of the gate electrode 4. Have

【０００４】[0004]

【実施例】次に本発明について図面を参照して説明す
る。図１は本発明の一実施例のＮ型半導体装置の断面図
である。The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of an N-type semiconductor device according to an embodiment of the present invention.

【０００５】ドレイン・ソース間耐圧が６０Ｖの場合、
Ｎ型基板１は約５．６×１０15／ｃｍ3 程度にリンがド
ープされた厚さ約４４０μｍのシリコン基板が用いられ
る。When the drain-source breakdown voltage is 60 V,
As the N-type substrate 1, a silicon substrate having a thickness of about 440 μm doped with phosphorus at about 5.6 × 10 15 / cm 3 is used.

【０００６】厚さ約０．６μｍのフィールド酸化膜２、
厚さ約０．０５μｍのゲート酸化膜３、厚さ約０．６μ
ｍでリンが約５×１０19／ｃｍ3 程度ドープされたポリ
シリコンのゲート電極４を順次、選択的に形成した後、
Ｐ型ベース領域５を加速電圧約５０ｋｅＶ、ドーズ量約
８×１０13／ｃｍ2 のボロンのイオン注入と１２００℃
約１時間の押し込みにより形成する。A field oxide film 2 having a thickness of about 0.6 μm,
Gate oxide film 3 with a thickness of about 0.05 μm, thickness of about 0.6 μm
After selectively forming a gate electrode 4 of polysilicon in which phosphorus is doped at about 5 × 10 19 / cm 3 by m,
Ion implantation of P-type base region 5 with an accelerating voltage of about 50 keV, a dose of about 8 × 10 13 / cm 2 and 1200 ° C.
It is formed by pushing for about 1 hour.

【０００７】Ｐ型領域６は加速電圧が５０ｋｅＶ、ドー
ズ量が１×１０12〜１×１０15／ｃｍ2 のボロンのイオ
ン注入、Ｎ+ 型ソース領域７及びＮ+ 型ドレイン電極８
は加速電圧が約７０ｋｅＶ、ドーズ量が約５×１０15／
ｃｍ2 のリンのイオン注入が行われ、その後９５０℃約
３０分の押込みによりＰ型領域６、Ｎ+ 型ソース領域
７、Ｎ+ 型ドレイン領域８が形成される。この後層間絶
縁膜１１を形成しコンタクト穴をあけ、ソース電極９お
よびドレイン電極１０が選択的に形成される。The P-type region 6 has an accelerating voltage of 50 keV, a dose amount of 1 × 10 12 to 1 × 10 15 / cm 2 of boron ion implantation, an N + -type source region 7 and an N + -type drain electrode 8.
Has an accelerating voltage of about 70 keV and a dose of about 5 × 10 15 /
Ion implantation of phosphorus of cm 2 is performed, and thereafter, by pressing at 950 ° C. for about 30 minutes, a P-type region 6, an N + -type source region 7, and an N + -type drain region 8 are formed. After that, an interlayer insulating film 11 is formed, contact holes are opened, and a source electrode 9 and a drain electrode 10 are selectively formed.

【０００８】なお横方向の寸法を最小にするため通常は
Ｐ型ベース領域５、Ｎ+ 型ソース領域７、Ｐ型領域６の
ゲート電極４の下部の領域はゲート電極４をマスクとし
たセルファラインで形成される。In order to minimize the lateral dimension, the regions below the gate electrode 4 of the P-type base region 5, N + -type source region 7 and P-type region 6 are usually self-aligned using the gate electrode 4 as a mask. Is formed by.

【０００９】また本実施例ではＮ型基板１としたが、集
積回路等の応用の場合では半導体基板１はＰ型基板に形
成されたＮ型ウェルでもよく、さらに各種分離技術を用
いたＮ型分離層でも良い。Although the N-type substrate 1 is used in this embodiment, the semiconductor substrate 1 may be an N-type well formed on a P-type substrate in the case of application of an integrated circuit or the like, and an N-type substrate using various separation techniques. It may be a separation layer.

【００１０】[0010]

【発明の効果】以上説明したように本発明はゲート電極
のドレイン側のエッジ部直下のＮ型基板１の表面部にＰ
型領域６を有しているためドレイン電界はこのＰ型領域
６で終端するためゲート電極端部には集中しないためド
レイン・ソース間の耐圧劣化は起こらず、またこのため
ゲート酸化膜３の信頼性劣化も抑えられる。As described above, according to the present invention, P is formed on the surface of the N-type substrate 1 immediately below the edge of the gate electrode on the drain side.
Since the drain electric field is terminated at the P-type region 6 because it has the type region 6, the breakdown voltage between the drain and the source is not deteriorated because the drain electric field is not concentrated at the end of the gate electrode. Deterioration is also suppressed.

【００１１】一例としてＮ型１Ωｃｍのの抵抗率（リン
濃度約５．６×１０15／ｃｍ3 ）を有する基板で試作し
た所、従来製造では約４０Ｖのドレイン・ソース間耐圧
だったのに対し本発明の構造では約８０Ｖのドレイン・
ソース間耐圧が得られ約２倍に向上した。またゲートバ
イアステスト（温度１５０℃、ドレイン・ソース間ショ
ートでゲートに電圧を印加）ゲート酸化膜が０．０５μ
ｍの厚さの場合、従来構造ではＶGSS ＝±２０Ｖ、１０
００H の評価で不良数が１５ｐ／２０ｐだったのに対
し、本発明の構造では同一条件で不良数が０ｐ／２０ｐ
と大幅に改善された。As an example, when a prototype having a substrate having an N type resistance of 1 Ωcm (phosphorus concentration of about 5.6 × 10 15 / cm 3 ) was made, the conventional manufacturing method showed a drain-source breakdown voltage of about 40V. In the structure of the present invention, a drain of about 80 V
The withstand voltage between sources was obtained and improved about twice. Gate bias test (Temperature 150 ° C, voltage is applied to the gate due to short circuit between drain and source) Gate oxide film is 0.05μ
When the thickness is m, V GSS = ± 20 V, 10 in the conventional structure.
The number of defects was 15 p / 20 p in the evaluation of 00 H , while the number of defects was 0 p / 20 p under the same conditions in the structure of the present invention.
And was greatly improved.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例の断面図。FIG. 1 is a sectional view of an embodiment of the present invention.

【図２】従来技術の断面図。FIG. 2 is a sectional view of a conventional technique.

【図３】従来技術の断面図。FIG. 3 is a cross-sectional view of a conventional technique.

【符号の説明】[Explanation of symbols]

１ Ｎ型基板 ２ フィールド酸化膜 ３ ゲート酸化膜 ４ ゲート電極 ５ ｐ型ベース領域 ６ ｐ型領域 ７ Ｎ+ 型ソース領域 ８ Ｎ+ 型ドレイン領域 ９ ソース電極 １０ ドレイン電極 １１ 層間絶縁膜1 N-type substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 5 p-type base region 6 p-type region 7 N + type source region 8 N + type drain region 9 source electrode 10 drain electrode 11 interlayer insulating film

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 第１導電型半導体基板の表面に形成され
た第２導電型のベース領域と、この第２導電型のベース
領域の中に形成された第１導電型のソース領域とこの第
２導電型のベース領域と横方向に間隔を取った第１導電
型の高濃度のドレイン領域と、ソース領域、ベース領
域、ドレイン領域にゲート酸化膜を介して形成されたゲ
ート電極からなる横型半導体装置に於て、ゲート電極の
ベース領域と反対端下部の第１導電型半導体基板の表面
部に第２導電型の領域を設けた事を特徴とした横型半導
体装置。1. A second-conductivity-type base region formed on the surface of a first-conductivity-type semiconductor substrate, a first-conductivity-type source region formed in the second-conductivity-type base region, and a first-conductivity-type source region formed in the second-conductivity-type base region. A lateral semiconductor comprising a first-conductivity-type high-concentration drain region laterally spaced from a two-conductivity-type base region, and a gate electrode formed in the source region, the base region, and the drain region through a gate oxide film. A lateral semiconductor device, wherein in the device, a second conductivity type region is provided on a surface portion of a first conductivity type semiconductor substrate below the base region of the gate electrode.
JP5211322A 1993-08-26 1993-08-26 High withstand voltage semiconductor device Pending JPH0766398A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5211322A JPH0766398A (en) 1993-08-26 1993-08-26 High withstand voltage semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5211322A JPH0766398A (en) 1993-08-26 1993-08-26 High withstand voltage semiconductor device

Publications (1)

Publication Number Publication Date
JPH0766398A true JPH0766398A (en) 1995-03-10

Family

ID=16604038

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5211322A Pending JPH0766398A (en) 1993-08-26 1993-08-26 High withstand voltage semiconductor device

Country Status (1)

Country Link
JP (1) JPH0766398A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026328A (en) * 2000-07-04 2002-01-25 Toshiba Corp Horizontal semiconductor device
JP2008066508A (en) * 2006-09-07 2008-03-21 New Japan Radio Co Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56110264A (en) * 1980-02-04 1981-09-01 Oki Electric Ind Co Ltd High withstand voltage mos transistor

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002026328A (en) * 2000-07-04 2002-01-25 Toshiba Corp Horizontal semiconductor device
JP2008066508A (en) * 2006-09-07 2008-03-21 New Japan Radio Co Ltd Semiconductor device

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