JP2008066508A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2008066508A
JP2008066508A JP2006242648A JP2006242648A JP2008066508A JP 2008066508 A JP2008066508 A JP 2008066508A JP 2006242648 A JP2006242648 A JP 2006242648A JP 2006242648 A JP2006242648 A JP 2006242648A JP 2008066508 A JP2008066508 A JP 2008066508A
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drift region
electric field
semiconductor device
impurity
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JP5148852B2 (en
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Masaaki Sato
政明 佐藤
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New Japan Radio Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device wherein a necessary withstanding voltage can be secured without increasing the dimension of its drift region and further the lowering of its on-resistance can be achieved without lowering the withstanding voltage. <P>SOLUTION: The semiconductor device has a reduced surface field structure and an impurity region formed in a floating structure whose periphery is surrounded by a drift region immediately under the gate insulating film whereon its gate electrode is laminated and formed. The impurity concentration of the impurity region is so set that the electric-field strength of the electric-field locally maximum point of a junction which is formed by the impurity and the drift regions is smaller than or equal to the electric-field strength of other electric-field locally maximum points of the semiconductor device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は半導体装置に関し、特に高電圧や高電流用として使用されるＭＯＳ型半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a MOS type semiconductor device used for high voltage and high current.

従来、高電圧、高電流用のＭＯＳ型半導体装置として、ソース−ドレイン間耐圧の高い二重拡散ＭＯＳ（ＤＭＯＳ）トランジスタが広く用いられている。ＤＭＯＳトランジスタは、半導体基板表面に形成した拡散領域から、導電型の異なる不純物を拡散させ、拡散速度の差によって形成する不純物領域を実効チャネル長とするもので、一導電型のボディー領域と高不純物濃度の逆導電型のドレイン領域との間に、低不純物濃度の逆導電型のドリフト領域を備えた構造となっている。また、ゲート電極のドレイン領域側エッジのゲート絶縁膜直下の電界を緩和するため、ゲート絶縁膜を厚くすることもある。   Conventionally, a double diffusion MOS (DMOS) transistor having a high source-drain breakdown voltage has been widely used as a MOS semiconductor device for high voltage and high current. A DMOS transistor diffuses impurities of different conductivity types from a diffusion region formed on the surface of a semiconductor substrate, and makes an impurity region formed by a difference in diffusion speed an effective channel length. A reverse conductivity type drift region having a low impurity concentration is provided between the drain region and the reverse conductivity type. In addition, the gate insulating film may be thickened to alleviate the electric field immediately below the gate insulating film at the drain region side edge of the gate electrode.

このような構造のＤＭＯＳトランジスタでは、ソース−ドレイン間に電圧を印加していくと、ドリフト領域内の電界が最大となった接合が降伏する。この臨界電界を越えた電圧が、ＤＭＯＳトランジスタの耐圧となる。上述のＤＭＯＳトランジスタにおいて電界が最大となるのは、ドレイン領域とドリフト領域との接合部、ゲート絶縁膜の厚さが一定の場合はゲート電極のドレイン領域側エッジのゲート絶縁膜直下あるいはドレイン領域側でゲート絶縁膜の厚さが厚くなる場合はゲート絶縁膜の厚さが厚くなる境界のドリフト領域部、ドリフト領域とボディー領域との接合部のいずれかであることが知られている。   In the DMOS transistor having such a structure, when a voltage is applied between the source and the drain, the junction where the electric field in the drift region is maximized breaks down. The voltage exceeding the critical electric field is the withstand voltage of the DMOS transistor. In the above-described DMOS transistor, the electric field is maximized at the junction between the drain region and the drift region. When the thickness of the gate insulating film is constant, the edge of the gate electrode immediately below the gate insulating film or on the drain region side In the case where the thickness of the gate insulating film is increased, it is known that the gate insulating film is one of a drift region at the boundary where the thickness of the gate insulating film is increased and a junction between the drift region and the body region.

そこで、その電界を緩和することで耐圧を向上させる試みが種々なされている。例えば、ドレイン領域とドリフト領域との界面の電界を下げるため、ドリフト領域の寸法を大きくしたり、ドリフト領域を十分に空乏化させるため、ドリフト領域の不純物濃度を下げる方法がとられていた。   Thus, various attempts have been made to improve the breakdown voltage by relaxing the electric field. For example, in order to reduce the electric field at the interface between the drain region and the drift region, the drift region is increased in size, or in order to sufficiently deplete the drift region, the impurity concentration in the drift region is reduced.

しかしながら、ドリフト領域の寸法を大きくすることは、ドリフト領域の抵抗が上昇し、低オン抵抗化（低損失化）のためには素子面積を大きくしなければならないという問題が生じてしまう。   However, increasing the size of the drift region raises the resistance of the drift region, and causes a problem that the element area must be increased for low on-resistance (low loss).

このような問題を解決するため、リサーフ（Reduced Surface field：表面電界緩和）構造が提案されている（例えば、非特許文献１、非特許文献２、非特許文献３）。リサーフ構造として、図５に示す構造の半導体装置が知られている。図５において１は高濃度のｐ型シリコン基板、２は低濃度のｐ型半導体層、３は低濃度ｎ型のドリフト領域、４はｐ型のボディー領域、５は高濃度ｎ型のソース領域、６は高濃度ｎ型のドレイン領域、７はゲート絶縁膜、８はゲート電極、９はソース電極、１０はドレイン電極、１１は高濃度ｐ型のコンタクト領域である。   In order to solve such a problem, a RESURF (Reduced Surface field) structure has been proposed (for example, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3). As a RESURF structure, a semiconductor device having a structure shown in FIG. 5 is known. In FIG. 5, 1 is a high-concentration p-type silicon substrate, 2 is a low-concentration p-type semiconductor layer, 3 is a low-concentration n-type drift region, 4 is a p-type body region, and 5 is a high-concentration n-type source region. , 6 is a high concentration n-type drain region, 7 is a gate insulating film, 8 is a gate electrode, 9 is a source electrode, 10 is a drain electrode, and 11 is a high concentration p-type contact region.

図５に示すように、ドリフト領域３の下層に導電型の異なる半導体層（ｐ型半導体層２）を配置することによって、ドリフト領域３の不純物濃度を高くしてもドリフト領域３が空乏化しやすくなる。その結果、最大電界点の電界強度が下がり耐圧の低下を防ぐことができると同時に、低オン抵抗化を図ることができる構造となっている。   As shown in FIG. 5, by disposing a semiconductor layer (p-type semiconductor layer 2) having a different conductivity type below the drift region 3, the drift region 3 is easily depleted even if the impurity concentration of the drift region 3 is increased. Become. As a result, the electric field intensity at the maximum electric field point is reduced, and a reduction in breakdown voltage can be prevented, and at the same time, a low on-resistance can be achieved.

このような構造において、例えばドリフト領域３の不純物濃度を１．１×１０16ｃｍ-3とし、ボディー領域４とドレイン領域６との間の寸法を７μｍとしたとき、耐圧は９７Ｖであった。この条件での電界強度の算出結果を図６に示す。図６に示すように、電界は、ゲート絶縁膜の厚さが厚くなる境界のドリフト領域３と、ドレイン領域６とドリフト領域３との接合部、ドリフト領域３とボディー領域４の接合部で大きい（電界極大点が存在する）ことがわかった。 In such a structure, for example, when the impurity concentration of the drift region 3 is 1.1 × 10 16 cm −3 and the dimension between the body region 4 and the drain region 6 is 7 μm, the breakdown voltage is 97V. The calculation result of the electric field strength under these conditions is shown in FIG. As shown in FIG. 6, the electric field is large at the drift region 3 at the boundary where the thickness of the gate insulating film increases, the junction between the drain region 6 and the drift region 3, and the junction between the drift region 3 and the body region 4. (There is an electric field maximum point).

また図７に示すように、ＳＯＩリサーフ構造の半導体装置も提案されている。図７において１２はシリコン支持基板、１３は埋め込み絶縁膜である。ＳＯＩリサーフ構造の半導体装置においても、前述の従来例同様、ドリフト領域３の不純物濃度を高くしても、耐圧の低下を防ぐことができると同時に、低オン抵抗化を図ることができる構造となっている。   As shown in FIG. 7, a semiconductor device having an SOI resurf structure has also been proposed. In FIG. 7, 12 is a silicon support substrate, and 13 is a buried insulating film. Also in the semiconductor device having the SOI resurf structure, as with the above-described conventional example, even if the impurity concentration of the drift region 3 is increased, the breakdown voltage can be prevented from being lowered and the on-resistance can be reduced. ing.

このような構造において、例えばドリフト領域の不純物濃度を１．１×１０16ｃｍ-3とし、ボディー領域４とドレイン領域６との間の寸法を７μｍとしたとき、耐圧は９６Ｖであった。この条件での電界強度を算出したところ、最大電界は、ドリフト領域３のゲート電極８の直下で、ゲート絶縁膜の厚さが厚くなる境界付近であり、この境界のドリフト領域３でブレークダウンしていることがわかった。 In such a structure, for example, when the impurity concentration of the drift region is 1.1 × 10 16 cm −3 and the dimension between the body region 4 and the drain region 6 is 7 μm, the breakdown voltage is 96V. When the electric field strength under this condition is calculated, the maximum electric field is immediately below the gate electrode 8 in the drift region 3 and in the vicinity of the boundary where the thickness of the gate insulating film increases, and breakdown occurs in the drift region 3 at this boundary. I found out.

更に低オン抵抗化を図るため、ドリフト領域３の不純物濃度を１．１５×１０16ｃｍ-3としたところ、耐圧は５６Ｖに低下してしまった。これは、ドリフト領域３の空乏層がドレイン領域６に達しなくなったためと考えられる。
J.A.Appels and H.M.J.Vaes,「High voltage thin layer devices (RESURF devices)」、International Electron Devices Meeting Technical Digest、p.238-241、1979年12月 J.A.van der Pol他１５名、「A-BCD:An economic 100V RESURF silicon-on-insulator BCD technology for consumer and automotive applications」、The 12th International Symposium on Power Semiconductor Devices and ICs、p.327-330、2000年5月 N.Cezac他４名、「A new generation of power unipolar devices: the concept of the Floating islands MOS transistor(FLIMOST) 」、The 12th International Symposium on Power Semiconductor Devices and ICs、p.69-72、2000年5月 In order to further reduce the on-resistance, when the impurity concentration of the drift region 3 was 1.15 × 10 16 cm −3 , the breakdown voltage was reduced to 56V. This is probably because the depletion layer in the drift region 3 does not reach the drain region 6.
JAAppels and HMJVaes, `` High voltage thin layer devices (RESURF devices) '', International Electron Devices Meeting Technical Digest, p.238-241, December 1979 JAvan der Pol and 15 others, “A-BCD: An economic 100V RESURF silicon-on-insulator BCD technology for consumer and automotive applications”, The 12th International Symposium on Power Semiconductor Devices and ICs, p.327-330, May 2000 Moon N. Cezac and four others, "A new generation of power unipolar devices: the concept of the Floating islands MOS transistor (FLIMOST)", The 12th International Symposium on Power Semiconductor Devices and ICs, p.69-72, May 2000

従来のＤＭＯＳトランジスタにおいて、リサーフ構造とすることによって低オン抵抗化を図る場合、必ずしも十分な耐圧が得られておらず、必要な耐圧を確保するためには、従来同様、ドリフト領域の寸法を大きくせざるを得なかった。本発明は、ドリフト領域の寸法を大きくすることなく、必要な耐圧を確保することができる半導体装置を提供することを目的とする。さらに、耐圧の低下がなく、低オン抵抗化を図ることができる半導体装置を提供することを目的とする。   In a conventional DMOS transistor, when a low on-resistance is achieved by adopting a RESURF structure, a sufficient breakdown voltage is not necessarily obtained, and in order to ensure a necessary breakdown voltage, the size of the drift region is increased as in the conventional case. I had to do it. An object of the present invention is to provide a semiconductor device capable of ensuring a necessary breakdown voltage without increasing the size of a drift region. It is another object of the present invention to provide a semiconductor device that can reduce the on-resistance without lowering the withstand voltage.

上記目的を達成するため、本願請求項１に係る発明は、一導電型の半導体層表面に選択的に形成された、一導電型のボディー領域及び逆導電型のドリフト領域と、前記ボディー領域表面に選択的に形成された逆導電型のソース領域と、前記ドリフト領域表面に選択的に形成された逆導電型のドレイン領域と、前記ソース領域と前記ドリフト領域との間の前記ボディー領域及び前記ソース領域側の前記ドリフト領域上に、ゲート絶縁膜を介して形成されたゲート電極と、前記ソース領域に接続するソース電極と、前記ドレイン領域に接続するドレイン電極とを備えた半導体装置において、前記ゲート電極が積層形成された前記ゲート絶縁膜直下の前記ドリフト領域中に、周囲を前記ドリフト領域で囲まれ、前記ドリフト領域と形成する接合の電界極大点の電界強度が、前記ゲート電極エッジ直下の前記ドリフト領域部あるいは前記ゲート絶縁膜の厚さが厚くなる境界の前記ドリフト領域部、前記ドレイン領域と前記ドリフト領域との接合部のいずれかの電界極大点の電界強度より小さいか、あるいは略一致するよう設定された不純物濃度の一導電型の不純物領域が形成されていることを特徴とする。   In order to achieve the above object, the invention according to claim 1 of the present application includes a one-conductivity-type body region and a reverse-conductivity-type drift region selectively formed on the one-conductivity-type semiconductor layer surface, and the body region surface. A reverse conductivity type source region selectively formed on the surface, a reverse conductivity type drain region selectively formed on a surface of the drift region, the body region between the source region and the drift region, and the In the semiconductor device comprising the gate electrode formed on the drift region on the source region side through a gate insulating film, the source electrode connected to the source region, and the drain electrode connected to the drain region, The drift region immediately below the gate insulating film on which the gate electrode is formed is surrounded by the drift region, and the junction is formed with the drift region. The electric field intensity at the maximum point is either the drift region portion immediately below the edge of the gate electrode or the junction between the drain region and the drift region at the boundary where the thickness of the gate insulating film increases. One conductivity type impurity region having an impurity concentration set to be smaller than or substantially equal to the electric field intensity at the electric field maximum point is formed.

また本願請求項２に係る発明は、請求項１記載の半導体装置において、前記ドリフト領域は、支持基板及び埋め込み絶縁膜上に形成した半導体層からなり、該半導体層に選択的に前記ボディー領域が形成されていることを特徴とする。   The invention according to claim 2 of the present application is the semiconductor device according to claim 1, wherein the drift region includes a semiconductor layer formed on a support substrate and a buried insulating film, and the body region is selectively formed on the semiconductor layer. It is formed.

本発明は、周囲をドリフト領域３で囲まれたフローティング構造とした不純物領域１４を備えることによって、ゲート電極８近傍で高い電界のかかる部分を増やし、耐圧の高い半導体装置を得ることができる。また、耐圧が同じ場合には、ドリフト領域３の不純物濃度を相対的に高くしたり、ドレイン領域６とボディー領域４間の寸法を小さくすることができるので、耐圧の低下がなく、低オン抵抗化を図ることができる。   In the present invention, by providing the impurity region 14 having a floating structure surrounded by the drift region 3, the portion where a high electric field is applied in the vicinity of the gate electrode 8 can be increased, and a semiconductor device having a high breakdown voltage can be obtained. Further, when the breakdown voltage is the same, the impurity concentration of the drift region 3 can be relatively increased, and the dimension between the drain region 6 and the body region 4 can be reduced, so that the breakdown voltage does not decrease and the low on-resistance is reduced. Can be achieved.

特に本発明では、通常のリサーフ構造において、電界強度が大きくなる厚いゲート絶縁膜直下に、不純物領域１４を配置し、このドレイン領域側の接合の電界極大点の電界強度が、従来同様、高い電界のかかるゲート電極のドレイン領域側エッジのゲート絶縁膜の直下のドリフト領域部あるいはゲート酸化膜が厚くなる境界のドリフト領域部、ドレイン領域とドリフト領域の境界部のいずれかの電界極大点の電界強度より小さくなるように不純物濃度を設定することで、電界を分散させ、最大電界を下げることができるようにしている。その結果、半導体装置の耐圧を上げることができる。また電界強度が大きくなる部分の電界強度と不純物領域の接合の電界強度がほぼ一致するように、不純物領域の不純物濃度を設定することで、耐圧向上の効果がさらに大きくなる。   In particular, in the present invention, in a normal RESURF structure, the impurity region 14 is disposed immediately below the thick gate insulating film where the electric field strength is increased, and the electric field strength at the field maximum point of the junction on the drain region side is as high as in the conventional case. Electric field strength at the field maximum point of either the drift region immediately below the gate insulating film at the drain region side edge of the gate electrode or the boundary between the drift region where the gate oxide film is thickened or the boundary between the drain region and the drift region By setting the impurity concentration to be smaller, the electric field can be dispersed and the maximum electric field can be lowered. As a result, the breakdown voltage of the semiconductor device can be increased. Further, the effect of improving the breakdown voltage is further increased by setting the impurity concentration in the impurity region so that the electric field strength at the portion where the electric field strength increases and the electric field strength at the junction of the impurity region substantially coincide.

また耐圧が同じ場合、ドリフト領域３の不純物濃度を上げることができるので、半導体装置のオン抵抗を低減することができる。さらに、ドレイン領域６とボディー領域４との間の寸法を小さくすることができるので、単位面積当たりのオン抵抗を下げることができるという利点がある。   Further, when the breakdown voltage is the same, the impurity concentration of the drift region 3 can be increased, so that the on-resistance of the semiconductor device can be reduced. Furthermore, since the dimension between the drain region 6 and the body region 4 can be reduced, there is an advantage that the on-resistance per unit area can be reduced.

本発明の半導体装置は、通常のリサーフ構造の半導体装置において、電界強度が大きくなるゲート電極が積層したゲート絶縁膜を介した直下のドリフト領域中、あるいはゲート絶縁膜の厚さを厚くする場合にはゲート絶縁膜の厚さが厚くなる境界のドリフト領域部（ゲート電極エッジ直下のドリフト領域部に相当）に、周囲をドリフト領域で囲まれ、フローティング構造とし、ドリフト領域とは導電型の異なる不純物領域を備える構造としている。このような構造とすることで、不純物領域とドリフト領域との接合のドレイン側に電界が集中する部分が追加形成され、電界集中が分散する結果、全体として最大電界を下げることができる。   The semiconductor device of the present invention is a normal semiconductor device having a resurf structure, in the case where the thickness of the gate insulating film is increased in the drift region directly below the gate insulating film on which the gate electrode having a high electric field strength is stacked. Is a drift region surrounded by a drift region (corresponding to the drift region immediately below the gate electrode edge) where the thickness of the gate insulating film increases, and has a floating structure. Impurities differing in conductivity type from the drift region The structure is provided with a region. With such a structure, a portion where the electric field concentrates is additionally formed on the drain side of the junction between the impurity region and the drift region, and the electric field concentration is dispersed. As a result, the maximum electric field can be lowered as a whole.

さらに本発明の不純物領域とドリフト領域からなる接合部の電界極大点の電界強度が、ゲート電極エッジ直下のドリフト領域部あるいはゲート絶縁膜の厚さが厚くなる境界のドリフト領域部、ドレイン領域とドリフト領域との接合部のいずれかの電界極大点ので電界強度より小さく、あるいはほぼ一致するように、その不純物濃度を設定する。その結果、高い電界のかかる部分が増えると共に、それぞれの電界強度はほぼ同じように上がるようになり、耐圧の向上を図ることができる。   Further, the electric field strength at the electric field maximum point of the junction consisting of the impurity region and the drift region of the present invention is the drift region portion immediately below the gate electrode edge or the drift region portion at the boundary where the thickness of the gate insulating film is increased, the drain region and the drift region. The impurity concentration is set so that it is smaller than or substantially coincides with the electric field intensity at any field maximum point at the junction with the region. As a result, the portion where a high electric field is applied increases, and the electric field strengths of the respective portions increase in substantially the same manner, so that the breakdown voltage can be improved.

また同じ耐圧であれば、ドリフト領域の不純物濃度を高く設定したり、半導体装置の寸法を小さくすることができ、オン抵抗の低減を図ることができるようになる。以下、実施例について、詳細に説明する。   Further, if the breakdown voltage is the same, the impurity concentration in the drift region can be set high, the size of the semiconductor device can be reduced, and the on-resistance can be reduced. Examples will be described in detail below.

図１に本発明の第１の実施例の半導体装置を示す。図１に示す半導体装置は、ＳＯＩ（Silicon on Insulator）基板上に形成されたリサーフ構造の半導体装置である。通常のＳＯＩリサーフ構造のＤＭＯＳトランジスタ同様、シリコン支持基板１２上に埋め込み絶縁膜１３が積層し、この埋め込み絶縁膜１３上に低濃度ｎ型のドリフト領域３とｐ型のボディー領域４が形成されている。ボディー領域４表面には、高濃度ｎ型のソース領域５と、高濃度ｐ型のコンタクト領域１１が形成されている。また、低濃度ｎ型のドリフト領域３表面には、高濃度ｎ型のドレイン領域６が形成されている。ゲート絶縁膜７は、ドレイン領域６側で厚さが厚くなっている。   FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. The semiconductor device shown in FIG. 1 is a resurf structure semiconductor device formed on an SOI (Silicon on Insulator) substrate. Like a normal SOI resurf DMOS transistor, a buried insulating film 13 is laminated on a silicon support substrate 12, and a low-concentration n-type drift region 3 and a p-type body region 4 are formed on the buried insulating film 13. Yes. A high concentration n-type source region 5 and a high concentration p-type contact region 11 are formed on the surface of the body region 4. A high concentration n-type drain region 6 is formed on the surface of the low concentration n-type drift region 3. The gate insulating film 7 is thicker on the drain region 6 side.

ソース領域５とドリフト領域３の間のボディー領域４と、ソース領域５側のドリフト領域３上に、一部厚さが厚くなっているゲート絶縁膜７を介してゲート電極８が形成されている。またソース領域５とコンタクト領域１１（ボディー領域４）に接続するようにソース電極９が、ドレイン領域６に接続するようにドレイン電極１０がそれぞれ形成されている。   A gate electrode 8 is formed on the body region 4 between the source region 5 and the drift region 3 and on the drift region 3 on the source region 5 side through a gate insulating film 7 having a partly thick thickness. . A source electrode 9 is formed so as to be connected to the source region 5 and the contact region 11 (body region 4), and a drain electrode 10 is formed so as to be connected to the drain region 6.

本発明の半導体装置では、上記のような半導体装置において、ｐ型の不純物領域１４を備える構造となっている。ここで、ドリフト領域３の不純物濃度を１．５×１０16ｃｍ-3、ボディー領域４とドレイン領域６との間の寸法を７μｍとし、ボロンイオンを不純物ドーズ量１．８×１０12ｃｍ-2でイオン注入し、厚さ１．５μｍドリフト領域３のほぼ中間の深さに不純物領域１４を幅１μｍ程度で形成した。その結果、耐圧は１１６Ｖとなった。これは、通常のこの種の半導体装置、即ち不純物領域１４を備えない構造の半導体装置でドリフト領域６の不純物濃度を１．１×１０16ｃｍ-3程度に設定した場合と比較して、耐圧が１．２倍に上昇し、オン抵抗が７８％に低下する結果であった。 The semiconductor device of the present invention has a structure including the p-type impurity region 14 in the semiconductor device as described above. Here, the impurity concentration of the drift region 3 is 1.5 × 10 16 cm −3 , the dimension between the body region 4 and the drain region 6 is 7 μm, and boron ions are impurity dose amount of 1.8 × 10 12 cm −. 2 is ion-implanted to form an impurity region 14 with a width of about 1μm to about halfway the depth of the thickness of 1.5μm drift region 3. As a result, the withstand voltage was 116V. This is compared with the case where the impurity concentration of the drift region 6 is set to about 1.1 × 10 16 cm −3 in a normal semiconductor device of this type, that is, a semiconductor device having a structure without the impurity region 14. Increased 1.2 times, and the on-resistance decreased to 78%.

図２は、上記構造の半導体装置において、電界強度の算出結果を示したものである。図２に示すように、不純物領域１４とドリフト領域３との接合のドレイン側に電界極大点が生じていることがわかる。このように電界強度が高い部分が増えると、半導体装置の他の電界極大点の電界強度が相対的に低下する。例えば、ゲート絶縁膜の厚さが厚くなる境界のドリフト部の電界強度が低下することが確認できた。その結果、半導体装置の耐圧が上昇したと考えられる。   FIG. 2 shows the calculation result of the electric field strength in the semiconductor device having the above structure. As shown in FIG. 2, it can be seen that an electric field maximum point is generated on the drain side of the junction between the impurity region 14 and the drift region 3. Thus, when the portion where the electric field strength is high increases, the electric field strength at other electric field maximum points of the semiconductor device relatively decreases. For example, it has been confirmed that the electric field strength of the drift portion at the boundary where the thickness of the gate insulating film increases becomes low. As a result, it is considered that the breakdown voltage of the semiconductor device has increased.

上述の構造において、ボディー領域４とドレイン領域６との間の寸法のみを５．５μｍとすると、耐圧は９６Ｖとなり、不純物領域１４を備えない場合と同様となる。しかしながら、このときのオン抵抗は６３％に低下する。半導体装置の小型化に伴い、単位面積あたりでは、５４％と大幅な低減ができた。   In the above structure, if only the dimension between the body region 4 and the drain region 6 is 5.5 μm, the breakdown voltage is 96 V, which is the same as the case where the impurity region 14 is not provided. However, the on-resistance at this time decreases to 63%. Along with the miniaturization of semiconductor devices, a significant reduction of 54% per unit area was achieved.

なお、不純物領域１４とドリフト領域３の接合の電界極大点の電界強度が、半導体装置内の他の接合の電界極大点の電界強度より大きすぎるときには、耐圧向上の効果がない。従って、不純物領域１４の不純物濃度は、ドリフト領域３の不純物濃度に応じて、他の接合の電界極大点の電界強度より小さく、あるいはほぼ一致するように適宜設定する必要がある。   Note that when the electric field strength at the electric field maximum point at the junction of the impurity region 14 and the drift region 3 is too larger than the electric field strength at the electric field maximum point at the other junction in the semiconductor device, there is no effect of improving the breakdown voltage. Therefore, the impurity concentration of the impurity region 14 needs to be appropriately set according to the impurity concentration of the drift region 3 so as to be smaller than or substantially equal to the electric field intensity at the electric field maximum point of the other junction.

不純物領域１４を形成する深さは、フローティング構造であれば、深さと電界強度の分布及び耐圧に大きな依存性はなく、適宜設定すれば良い。不純物領域１４の幅（支持基板１２表面に平行なボディー領域４からドレイン領域６方向への拡がり幅）も、この領域が空乏化する範囲であれば電界緩和に大きな影響はない。しかし、この領域が空乏化しないほど不純物領域１４の不純物濃度が高い場合には、幅を広げ、この領域の体積濃度を下げる必要がある。   The depth at which the impurity region 14 is formed is not particularly dependent on the depth and the distribution of electric field strength and the withstand voltage as long as it is a floating structure, and may be set as appropriate. The width of the impurity region 14 (expansion width in the direction from the body region 4 parallel to the surface of the support substrate 12 to the drain region 6) is not greatly affected by electric field relaxation as long as this region is depleted. However, when the impurity concentration of the impurity region 14 is so high that the region is not depleted, it is necessary to widen the width and lower the volume concentration of the region.

なお、不純物領域１４のドレイン領域６側のエッジは、ドレイン領域６側に移動させるほど電界緩和の効果が少なくなり、半導体装置の耐圧を下げてしまう。またドリフト領域３の抵抗を増大させてしまう。例えば、不純物領域１４のドレイン領域６側のエッジを、ゲート電極８のドレイン領域６側エッジの直下から０．５μｍ程度ドレイン領域６側に移動させた場合、９６Ｖの耐圧が８３Ｖに低下することが確認された。このときの電界強度の算出結果をみると、電界強度の緩和の効果はあるものの、ドリフト領域３の寸法を実質的に短縮しているためと考えられる。従って、不純物領域１４のドレイン領域６側エッジは、ゲート電極８のドレイン領域６側エッジよりドレイン領域６側に突出しない構造とするのが好ましい。   Note that as the edge of the impurity region 14 on the drain region 6 side is moved to the drain region 6 side, the effect of electric field relaxation is reduced, and the breakdown voltage of the semiconductor device is lowered. Further, the resistance of the drift region 3 is increased. For example, when the edge of the impurity region 14 on the drain region 6 side is moved from the position immediately below the edge of the gate electrode 8 on the drain region 6 side to the drain region 6 side by about 0.5 μm, the withstand voltage of 96 V may drop to 83 V. confirmed. From the calculation result of the electric field strength at this time, it is considered that the dimension of the drift region 3 is substantially shortened although there is an effect of relaxing the electric field strength. Accordingly, it is preferable that the drain region 6 side edge of the impurity region 14 does not protrude from the drain region 6 side edge of the gate electrode 8 to the drain region 6 side.

次に第２の実施例について説明する。上述の第１の実施例では、ゲート絶縁膜７の厚さが、ドレイン領域６側で厚く形成されていた。しかしながら、ゲート絶縁膜７の厚さが一定の場合も本発明の不純物領域１４は、耐圧向上の効果を発揮する。ゲート絶縁膜７の厚さが一定の場合、ゲート電極８のドレイン領域６側エッジのゲート絶縁膜７直下のドリフト領域３に電界が集中する。図３に本実施例の半導体装置における電界強度の算出結果を示す。図３に示すように、ゲート電極８のドレイン領域６側エッジのゲート絶縁膜７直下のドリフト領域部、ドレイン領域６とドリフト領域３の接合部、不純物領域１４とドリフト領域３との接合のドレイン側に電界が集中していることがわかる。このように複数の部分に電界が集中する構造とすることで、電界が集中したそれぞれの部分において電界強度が低下することが確認された。具体的には、ドリフト領域３の不純物濃度を８×１０15ｃｍ-3、ボディー領域４とドレイン領域６との間の寸法を７μｍとし、ボロンイオンを不純物ドーズ量２．７×１０12ｃｍ-2でイオン注入して不純物領域１４を形成したとき、耐圧は７２Ｖであった（ドリフト領域３の不純物濃度が３．２×１０15ｃｍ-3で、不純物領域１４がないときの耐圧は５０Ｖ）。このように、ゲート絶縁膜７の厚さを厚くしない構造においても、高い耐圧が得られることが確認された。 Next, a second embodiment will be described. In the first embodiment described above, the gate insulating film 7 is formed thick on the drain region 6 side. However, even when the thickness of the gate insulating film 7 is constant, the impurity region 14 of the present invention exhibits the effect of improving the breakdown voltage. When the thickness of the gate insulating film 7 is constant, the electric field concentrates on the drift region 3 immediately below the gate insulating film 7 at the edge of the gate electrode 8 on the drain region 6 side. FIG. 3 shows the calculation result of the electric field strength in the semiconductor device of this example. As shown in FIG. 3, the drain region 6 edge of the gate electrode 8 immediately below the gate insulating film 7, the junction between the drain region 6 and the drift region 3, and the drain at the junction between the impurity region 14 and the drift region 3. It can be seen that the electric field is concentrated on the side. In this way, it was confirmed that the electric field strength is reduced in each portion where the electric field is concentrated by adopting a structure in which the electric field is concentrated in a plurality of portions. Specifically, the impurity concentration of the drift region 3 is 8 × 10 15 cm −3 , the dimension between the body region 4 and the drain region 6 is 7 μm, and boron ions are doped with an impurity dose of 2.7 × 10 12 cm −. When the impurity region 14 is formed by ion implantation in step 2 , the breakdown voltage is 72 V (the impurity concentration of the drift region 3 is 3.2 × 10 15 cm −3 and the breakdown voltage when there is no impurity region 14 is 50 V). . Thus, it was confirmed that a high breakdown voltage can be obtained even in a structure in which the thickness of the gate insulating film 7 is not increased.

本実施例においても、第１の実施例同様、不純物領域１４の形成深さは電界強度の分布及び耐圧に大きな依存性はなく、適宜設定すれば良い。また不純物領域１４の幅も、この領域が空乏化する範囲であれば電界緩和に大きな影響はない。不純物領域１４のドレイン領域６側エッジをゲート電極８のドレイン領域６側エッジより突出しない構造とするのが好ましいことも同様である。   Also in the present embodiment, as in the first embodiment, the formation depth of the impurity region 14 does not depend greatly on the electric field strength distribution and the withstand voltage, and may be set as appropriate. Further, the width of the impurity region 14 is not greatly affected by electric field relaxation as long as this region is depleted. Similarly, it is preferable that the edge of the impurity region 14 on the drain region 6 side does not protrude from the edge of the gate electrode 8 on the drain region 6 side.

次に第３の実施例について説明する。本実施例は、図４に示すようにＳＯＩ基板を用いない構造の半導体装置となる。従来例で説明した半導体装置において、不純物領域１４を備えていることが異なる。ＳＯＩ基板を用いない場合でも、上述の実施例同様の効果が発揮される。具体的には、ドリフト領域３の不純物濃度を１．５×１０16ｃｍ-3、ボディー領域４とドレイン領域６との間の寸法を７μｍとし、ボロンイオンを不純物ドーズ量２．０×１０12ｃｍ-2でイオン注入して不純物領域１４を形成したとき、耐圧は１２０Ｖとなった。これは、不純物領域１４のない構造の半導体装置（ドリフト領域３の不純物濃度１．１×１０16ｃｍ-3、耐圧９７Ｖ）と比較して、耐圧が１．２４倍に上昇したことになる。またオン抵抗は７９％に低下したことも確認された。 Next, a third embodiment will be described. This embodiment is a semiconductor device having a structure that does not use an SOI substrate as shown in FIG. The semiconductor device described in the conventional example is different in that the impurity region 14 is provided. Even when the SOI substrate is not used, the same effects as those of the above-described embodiments are exhibited. Specifically, the impurity concentration of the drift region 3 is 1.5 × 10 16 cm −3 , the dimension between the body region 4 and the drain region 6 is 7 μm, and boron ions are doped with an impurity dose of 2.0 × 10 12. When the impurity region 14 was formed by ion implantation at cm −2 , the breakdown voltage was 120V. This means that the breakdown voltage is increased 1.24 times as compared with a semiconductor device having a structure without the impurity region 14 (impurity concentration of the drift region 3 is 1.1 × 10 16 cm −3 , breakdown voltage of 97 V). It was also confirmed that the on-resistance was reduced to 79%.

同様の構造の半導体装置において、ボディー領域４とドレイン領域６との間の寸法を６μｍにしたところ、耐圧は１０２Ｖとなり、オン抵抗は６８％に低下したことが確認された。このようにＳＯＩ基板を用いない場合であっても、高い耐圧が得られると同時に、オン抵抗の低減に効果があることが確認できた。   In a semiconductor device having a similar structure, it was confirmed that when the dimension between the body region 4 and the drain region 6 was 6 μm, the breakdown voltage was 102 V and the on-resistance was reduced to 68%. Thus, it was confirmed that even when the SOI substrate was not used, a high breakdown voltage was obtained, and at the same time, the on-resistance was effective.

本実施例においても、上述の実施例同様、不純物領域１４の形成深さは電界強度の分布及び耐圧に大きな依存性はなく、適宜設定すれば良い。また不純物領域１４の幅も、この領域が空乏化する範囲であれば電界緩和に大きな影響はない。不純物領域１４のドレイン領域６側エッジをゲート電極８のドレイン領域６側エッジより突出しない構造とするのが好ましいことも同様である。   Also in this embodiment, the depth of formation of the impurity region 14 does not depend greatly on the distribution of electric field strength and the withstand voltage as in the above-described embodiment, and may be set as appropriate. Further, the width of the impurity region 14 is not greatly affected by electric field relaxation as long as this region is depleted. Similarly, it is preferable that the edge of the impurity region 14 on the drain region 6 side does not protrude from the edge of the gate electrode 8 on the drain region 6 side.

以上本発明の実施例について説明したが、本発明はこれらに限定されるものでないことはいうまでもない。例えば、不純物領域１４は、１つのみでなく、ボディー領域４から所定の寸法離し、複数の不純物領域１４が配置する構造とすることも可能である。また、導電型を反転させたＤＭＯＳトランジスタであっても、同様の効果を発揮するものである。   As mentioned above, although the Example of this invention was described, it cannot be overemphasized that this invention is not limited to these. For example, not only one impurity region 14 but also a structure in which a plurality of impurity regions 14 are arranged with a predetermined dimension away from the body region 4 may be employed. Even a DMOS transistor having a reversed conductivity type exhibits the same effect.

本発明の第１の実施例の半導体装置の説明図である。FIG. 3 is an explanatory diagram of the semiconductor device according to the first embodiment of this invention. 本発明の第１の実施例の半導体装置の電界強度の算出結果である。It is a calculation result of the electric field strength of the semiconductor device of 1st Example of this invention. 本発明の第２の実施例の半導体装置の電界強度の算出結果である。It is a calculation result of the electric field strength of the semiconductor device of 2nd Example of this invention. 本発明の第３の実施例の半導体装置の説明図である。It is explanatory drawing of the semiconductor device of the 3rd Example of this invention. 従来のこの種の半導体装置の説明図である。It is explanatory drawing of this kind of conventional semiconductor device. 従来の半導体装置の電界強度の算出結果である。It is the calculation result of the electric field strength of the conventional semiconductor device. 従来の別の半導体装置の説明図である。It is explanatory drawing of another conventional semiconductor device.

符号の説明Explanation of symbols

１：ｐ型シリコン基板、２：ｐ型半導体層、３：ドリフト領域、４：ボディー領域、５：ソース領域、６：ドレイン領域、７：ゲート絶縁膜、８；ゲート電極、９：ソース電極、１０：ドレイン電極、１１：コンタクト領域、１２：シリコン支持基板、１３：埋め込み絶縁膜、１４；半導体領域
1: p-type silicon substrate, 2: p-type semiconductor layer, 3: drift region, 4: body region, 5: source region, 6: drain region, 7: gate insulating film, 8: gate electrode, 9: source electrode, 10: drain electrode, 11: contact region, 12: silicon support substrate, 13: buried insulating film, 14: semiconductor region

Claims (2)

一導電型の半導体層表面に選択的に形成された、一導電型のボディー領域及び逆導電型のドリフト領域と、
前記ボディー領域表面に選択的に形成された逆導電型のソース領域と、
前記ドリフト領域表面に選択的に形成された逆導電型のドレイン領域と、
前記ソース領域と前記ドリフト領域との間の前記ボディー領域及び前記ソース領域側の前記ドリフト領域上に、ゲート絶縁膜を介して形成されたゲート電極と、
前記ソース領域に接続するソース電極と、
前記ドレイン領域に接続するドレイン電極とを備えた半導体装置において、
前記ゲート電極が積層形成された前記ゲート絶縁膜直下の前記ドリフト領域中に、周囲を前記ドリフト領域で囲まれ、前記ドリフト領域と形成する接合の電界極大点の電界強度が、前記ゲート電極エッジ直下の前記ドリフト領域部あるいは前記ゲート絶縁膜の厚さが厚くなる境界の前記ドリフト領域部、前記ドレイン領域と前記ドリフト領域との接合部のいずれかの電界極大点の電界強度より小さいか、あるいは略一致するよう設定された不純物濃度の一導電型の不純物領域が形成されていることを特徴とする半導体装置。 A one conductivity type body region and a reverse conductivity type drift region selectively formed on the surface of the one conductivity type semiconductor layer;
A reverse conductivity type source region selectively formed on the surface of the body region;
A reverse conductivity type drain region selectively formed on the surface of the drift region;
A gate electrode formed on the body region between the source region and the drift region and the drift region on the source region side through a gate insulating film;
A source electrode connected to the source region;
In a semiconductor device comprising a drain electrode connected to the drain region,
The drift region immediately below the gate insulating film in which the gate electrode is stacked is surrounded by the drift region, and the electric field strength at the electric field maximum point of the junction formed with the drift region is directly below the edge of the gate electrode. Less than or substantially equal to the electric field intensity at the electric field maximum point of the drift region portion or the junction between the drain region and the drift region at the boundary where the thickness of the drift region portion or the gate insulating film increases. A semiconductor device characterized in that an impurity region of one conductivity type having an impurity concentration set to match is formed. 請求項１記載の半導体装置において、前記ドリフト領域は、支持基板及び埋め込み絶縁膜上に形成した半導体層からなり、該半導体層に選択的に前記ボディー領域が形成されていることを特徴とする半導体装置。
2. The semiconductor device according to claim 1, wherein the drift region includes a semiconductor layer formed on a support substrate and a buried insulating film, and the body region is selectively formed in the semiconductor layer. apparatus.
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