JP5148852B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a MOS type semiconductor device used for high voltage and high current.

  Conventionally, a double diffusion MOS (DMOS) transistor having a high source-drain breakdown voltage has been widely used as a MOS semiconductor device for high voltage and high current. A DMOS transistor diffuses impurities of different conductivity types from a diffusion region formed on the surface of a semiconductor substrate, and makes an impurity region formed by a difference in diffusion speed an effective channel length. A reverse conductivity type drift region having a low impurity concentration is provided between the drain region and the reverse conductivity type. In addition, the gate insulating film may be thickened to alleviate the electric field immediately below the gate insulating film at the drain region side edge of the gate electrode.

  In the DMOS transistor having such a structure, when a voltage is applied between the source and the drain, the junction where the electric field in the drift region is maximized breaks down. The voltage exceeding the critical electric field is the withstand voltage of the DMOS transistor. In the above-described DMOS transistor, the electric field is maximized at the junction between the drain region and the drift region. When the thickness of the gate insulating film is constant, the edge of the gate electrode immediately below the gate insulating film or on the drain region side In the case where the thickness of the gate insulating film is increased, it is known that the gate insulating film is one of a drift region at the boundary where the thickness of the gate insulating film is increased and a junction between the drift region and the body region.

  Thus, various attempts have been made to improve the breakdown voltage by relaxing the electric field. For example, in order to reduce the electric field at the interface between the drain region and the drift region, the drift region is increased in size, or in order to sufficiently deplete the drift region, the impurity concentration in the drift region is reduced.

  However, increasing the size of the drift region raises the resistance of the drift region, and causes a problem that the element area must be increased for low on-resistance (low loss).

  In order to solve such a problem, a RESURF (Reduced Surface field) structure has been proposed (for example, Non-Patent Document 1, Non-Patent Document 2, and Non-Patent Document 3). As a RESURF structure, a semiconductor device having a structure shown in FIG. 5 is known. In FIG. 5, 1 is a high-concentration p-type silicon substrate, 2 is a low-concentration p-type semiconductor layer, 3 is a low-concentration n-type drift region, 4 is a p-type body region, and 5 is a high-concentration n-type source region. , 6 is a high concentration n-type drain region, 7 is a gate insulating film, 8 is a gate electrode, 9 is a source electrode, 10 is a drain electrode, and 11 is a high concentration p-type contact region.

  As shown in FIG. 5, by disposing a semiconductor layer (p-type semiconductor layer 2) having a different conductivity type below the drift region 3, the drift region 3 is easily depleted even if the impurity concentration of the drift region 3 is increased. Become. As a result, the electric field intensity at the maximum electric field point is reduced, and a reduction in breakdown voltage can be prevented, and at the same time, a low on-resistance can be achieved.

In such a structure, for example, when the impurity concentration of the drift region 3 is 1.1 × 10 ¹⁶ cm ⁻³ and the dimension between the body region 4 and the drain region 6 is 7 μm, the breakdown voltage is 97V. The calculation result of the electric field strength under these conditions is shown in FIG. As shown in FIG. 6, the electric field is large at the drift region 3 at the boundary where the thickness of the gate insulating film increases, at the junction between the drain region 6 and the drift region 3, and at the junction between the drift region 3 and the body region 4. (There is an electric field maximum point).

  As shown in FIG. 7, a semiconductor device having an SOI resurf structure has also been proposed. In FIG. 7, 12 is a silicon support substrate, and 13 is a buried insulating film. Also in the semiconductor device having the SOI resurf structure, as with the above-described conventional example, even if the impurity concentration of the drift region 3 is increased, the breakdown voltage can be prevented from being lowered and the on-resistance can be reduced. ing.

In such a structure, for example, when the impurity concentration of the drift region is 1.1 × 10 ¹⁶ cm ⁻³ and the dimension between the body region 4 and the drain region 6 is 7 μm, the breakdown voltage is 96V. When the electric field strength under this condition is calculated, the maximum electric field is immediately below the gate electrode 8 in the drift region 3 and in the vicinity of the boundary where the thickness of the gate insulating film becomes thick, and breakdown occurs in the drift region 3 at this boundary. I found out.

In order to further reduce the on-resistance, when the impurity concentration of the drift region 3 was 1.15 × 10 ¹⁶ cm ⁻³ , the breakdown voltage was reduced to 56V. This is probably because the depletion layer in the drift region 3 does not reach the drain region 6.
JAAppels and HMJVaes, `` High voltage thin layer devices (RESURF devices) '', International Electron Devices Meeting Technical Digest, p.238-241, December 1979 JAvan der Pol and 15 others, “A-BCD: An economic 100V RESURF silicon-on-insulator BCD technology for consumer and automotive applications”, The 12th International Symposium on Power Semiconductor Devices and ICs, p.327-330, May 2000 Moon N. Cezac and four others, "A new generation of power unipolar devices: the concept of the Floating islands MOS transistor (FLIMOST)", The 12th International Symposium on Power Semiconductor Devices and ICs, p.69-72, May 2000

  In a conventional DMOS transistor, when a low on-resistance is achieved by adopting a RESURF structure, a sufficient breakdown voltage is not necessarily obtained, and in order to ensure a necessary breakdown voltage, the size of the drift region is increased as in the conventional case. I had to do it. An object of the present invention is to provide a semiconductor device capable of ensuring a necessary breakdown voltage without increasing the size of a drift region. It is another object of the present invention to provide a semiconductor device that can reduce the on-resistance without lowering the withstand voltage.

In order to achieve the above object, the invention according to claim 1 of the present application includes a one-conductivity-type body region and a reverse-conductivity-type drift region selectively formed on the one-conductivity-type semiconductor layer surface, and the body region surface. A reverse conductivity type source region selectively formed on the surface, a reverse conductivity type drain region selectively formed on a surface of the drift region, the body region between the source region and the drift region, and the In the semiconductor device comprising the gate electrode formed on the drift region on the source region side through a gate insulating film, the source electrode connected to the source region, and the drain electrode connected to the drain region, The drift region immediately below the gate insulating film on which the gate electrode is formed is surrounded by the drift region, and the drain region side edge of the gate electrode is surrounded by the drift region. And an impurity region of one conductivity type that does not protrude to the drain region side, and the impurity concentration of the impurity region is such that the electric field strength at the electric field maximum point of the junction formed by the impurity region and the drift region is the gate Is the electric field intensity smaller than the electric field maximum point at any one of the drift region part immediately below the electrode edge or the junction between the drain region and the drift region at the boundary where the thickness of the gate insulating film increases? Alternatively, the structure is characterized in that the electric field is dispersed in the impurity region by setting so as to substantially match , thereby reducing the maximum electric field .

The invention according to claim 2 of the present application is the semiconductor device according to claim 1, wherein the one-conductivity-type semiconductor layer is replaced with a buried insulating film, and the drift region is formed on a support substrate and the buried insulating film. The body region is selectively formed in the semiconductor layer.

  In the present invention, by providing the impurity region 14 having a floating structure surrounded by the drift region 3, the portion where a high electric field is applied in the vicinity of the gate electrode 8 can be increased, and a semiconductor device having a high breakdown voltage can be obtained. Further, when the breakdown voltage is the same, the impurity concentration of the drift region 3 can be relatively increased, and the dimension between the drain region 6 and the body region 4 can be reduced, so that the breakdown voltage does not decrease and the low on-resistance is reduced. Can be achieved.

  In particular, in the present invention, in a normal RESURF structure, the impurity region 14 is disposed immediately below the thick gate insulating film where the electric field strength is increased, and the electric field strength at the field maximum point of the junction on the drain region side is as high as in the conventional case. Electric field strength at the field maximum point of either the drift region immediately below the gate insulating film at the drain region side edge of the gate electrode or the boundary between the drift region where the gate oxide film is thickened or the boundary between the drain region and the drift region By setting the impurity concentration to be smaller, the electric field can be dispersed and the maximum electric field can be lowered. As a result, the breakdown voltage of the semiconductor device can be increased. Further, the effect of improving the breakdown voltage is further increased by setting the impurity concentration in the impurity region so that the electric field strength at the portion where the electric field strength increases and the electric field strength at the junction of the impurity region substantially coincide.

  Further, when the breakdown voltage is the same, the impurity concentration of the drift region 3 can be increased, so that the on-resistance of the semiconductor device can be reduced. Furthermore, since the dimension between the drain region 6 and the body region 4 can be reduced, there is an advantage that the on-resistance per unit area can be reduced.

  The semiconductor device of the present invention is a normal semiconductor device having a resurf structure, in the case where the thickness of the gate insulating film is increased in the drift region directly below the gate insulating film on which the gate electrode having a high electric field strength is stacked. Is a drift region surrounded by a drift region (corresponding to the drift region immediately below the gate electrode edge) where the thickness of the gate insulating film increases, and has a floating structure. Impurities differing in conductivity type from the drift region The structure is provided with a region. With such a structure, a portion where the electric field concentrates is additionally formed on the drain side of the junction between the impurity region and the drift region, and the electric field concentration is dispersed. As a result, the maximum electric field can be lowered as a whole.

  Further, the electric field strength at the electric field maximum point of the junction consisting of the impurity region and the drift region of the present invention is the drift region portion immediately below the gate electrode edge or the drift region portion at the boundary where the thickness of the gate insulating film is increased, the drain region and the drift region. The impurity concentration is set so that it is smaller than or substantially coincides with the electric field intensity at any field maximum point at the junction with the region. As a result, the portion where a high electric field is applied increases, and the electric field strengths of the respective portions increase in substantially the same manner, so that the breakdown voltage can be improved.

  Further, if the breakdown voltage is the same, the impurity concentration in the drift region can be set high, the size of the semiconductor device can be reduced, and the on-resistance can be reduced. Examples will be described in detail below.

  FIG. 1 shows a semiconductor device according to a first embodiment of the present invention. The semiconductor device shown in FIG. 1 is a resurf structure semiconductor device formed on an SOI (Silicon on Insulator) substrate. Like a normal SOI resurf DMOS transistor, a buried insulating film 13 is laminated on a silicon support substrate 12, and a low-concentration n-type drift region 3 and a p-type body region 4 are formed on the buried insulating film 13. Yes. A high concentration n-type source region 5 and a high concentration p-type contact region 11 are formed on the surface of the body region 4. A high concentration n-type drain region 6 is formed on the surface of the low concentration n-type drift region 3. The gate insulating film 7 is thicker on the drain region 6 side.

  A gate electrode 8 is formed on the body region 4 between the source region 5 and the drift region 3 and on the drift region 3 on the source region 5 side through a gate insulating film 7 having a partly thick thickness. . A source electrode 9 is formed so as to be connected to the source region 5 and the contact region 11 (body region 4), and a drain electrode 10 is formed so as to be connected to the drain region 6.

The semiconductor device of the present invention has a structure including the p-type impurity region 14 in the semiconductor device as described above. Here, the impurity concentration of the drift region 3 is 1.5 × 10 ¹⁶ cm ⁻³ , the dimension between the body region 4 and the drain region 6 is 7 μm, and boron ions are impurity dose amount of 1.8 × 10 ¹² cm ^{−. 2} is ion-implanted to form an impurity region 14 with a width of about 1μm to about halfway the depth of the thickness of 1.5μm drift region 3. As a result, the withstand voltage was 116V. Compared with the case where the impurity concentration of the drift region 6 is set to about 1.1 × 10 ¹⁶ cm ⁻³ in a normal semiconductor device of this type, that is, a semiconductor device having a structure without the impurity region 14, the breakdown voltage is reduced. Increased 1.2 times, and the on-resistance decreased to 78%.

  FIG. 2 shows the calculation result of the electric field strength in the semiconductor device having the above structure. As shown in FIG. 2, it can be seen that an electric field maximum point is generated on the drain side of the junction between the impurity region 14 and the drift region 3. Thus, when the portion where the electric field strength is high increases, the electric field strength at other electric field maximum points of the semiconductor device relatively decreases. For example, it has been confirmed that the electric field strength of the drift portion at the boundary where the thickness of the gate insulating film increases becomes low. As a result, it is considered that the breakdown voltage of the semiconductor device has increased.

  In the above structure, if only the dimension between the body region 4 and the drain region 6 is 5.5 μm, the breakdown voltage is 96 V, which is the same as the case where the impurity region 14 is not provided. However, the on-resistance at this time decreases to 63%. Along with the miniaturization of semiconductor devices, a significant reduction of 54% per unit area was achieved.

  Note that when the electric field strength at the electric field maximum point at the junction of the impurity region 14 and the drift region 3 is too large than the electric field strength at the electric field maximum point at the other junction in the semiconductor device, there is no effect of improving the breakdown voltage. Therefore, the impurity concentration of the impurity region 14 needs to be appropriately set according to the impurity concentration of the drift region 3 so as to be smaller than or substantially equal to the electric field intensity at the electric field maximum point of the other junction.

  The depth at which the impurity region 14 is formed is not particularly dependent on the depth and the distribution of electric field strength and the withstand voltage as long as it is a floating structure, and may be set as appropriate. The width of the impurity region 14 (expansion width in the direction from the body region 4 parallel to the surface of the support substrate 12 to the drain region 6) is not greatly affected by electric field relaxation as long as this region is depleted. However, when the impurity concentration of the impurity region 14 is so high that the region is not depleted, it is necessary to widen the width and lower the volume concentration of the region.

  Note that as the edge of the impurity region 14 on the drain region 6 side is moved to the drain region 6 side, the effect of electric field relaxation is reduced, and the breakdown voltage of the semiconductor device is lowered. Further, the resistance of the drift region 3 is increased. For example, when the edge of the impurity region 14 on the drain region 6 side is moved from the position immediately below the edge of the gate electrode 8 on the drain region 6 side to the drain region 6 side by about 0.5 μm, the withstand voltage of 96 V may drop to 83 V. confirmed. From the calculation result of the electric field strength at this time, it is considered that the dimension of the drift region 3 is substantially shortened although there is an effect of relaxing the electric field strength. Accordingly, it is preferable that the drain region 6 side edge of the impurity region 14 does not protrude from the drain region 6 side edge of the gate electrode 8 to the drain region 6 side.

Next, a second embodiment will be described. In the first embodiment described above, the gate insulating film 7 is formed thick on the drain region 6 side. However, even when the thickness of the gate insulating film 7 is constant, the impurity region 14 of the present invention exhibits the effect of improving the breakdown voltage. When the thickness of the gate insulating film 7 is constant, the electric field concentrates on the drift region 3 immediately below the gate insulating film 7 at the edge of the gate electrode 8 on the drain region 6 side. FIG. 3 shows the calculation result of the electric field strength in the semiconductor device of this example. As shown in FIG. 3, the drain region at the edge of the gate electrode 8 on the drain region 6 side, immediately below the gate insulating film 7, the junction between the drain region 6 and the drift region 3, and the drain at the junction between the impurity region 14 and the drift region 3. It can be seen that the electric field is concentrated on the side. Thus, it was confirmed that the electric field strength is reduced in each portion where the electric field is concentrated by adopting a structure in which the electric field is concentrated in a plurality of portions. Specifically, the impurity concentration in the drift region 3 is 8 × 10 ¹⁵ cm ⁻³ , the dimension between the body region 4 and the drain region 6 is 7 μm, and boron ions are doped in an amount of 2.7 × 10 ¹² cm ^{−. When} the impurity region 14 was formed by ion implantation at ² , the breakdown voltage was 72 V (the impurity concentration of the drift region 3 was 3.2 × 10 ¹⁵ cm ⁻³ , and the breakdown voltage when there was no impurity region 14 was 50 V). . Thus, it was confirmed that a high breakdown voltage can be obtained even in a structure in which the thickness of the gate insulating film 7 is not increased.

  Also in the present embodiment, as in the first embodiment, the formation depth of the impurity region 14 does not depend greatly on the electric field strength distribution and the withstand voltage, and may be set as appropriate. Further, the width of the impurity region 14 is not greatly affected by electric field relaxation as long as this region is depleted. Similarly, it is preferable that the edge of the impurity region 14 on the drain region 6 side does not protrude from the edge of the gate electrode 8 on the drain region 6 side.

Next, a third embodiment will be described. This embodiment is a semiconductor device having a structure that does not use an SOI substrate as shown in FIG. The semiconductor device described in the conventional example is different in that the impurity region 14 is provided. Even when the SOI substrate is not used, the same effects as those of the above-described embodiments are exhibited. Specifically, the impurity concentration of the drift region 3 is 1.5 × 10 ¹⁶ cm ⁻³ , the dimension between the body region 4 and the drain region 6 is 7 μm, and boron ions are impurity dose amount of 2.0 × 10 ^12. When the impurity region 14 was formed by ion implantation at cm ⁻² , the breakdown voltage was 120V. This means that the breakdown voltage is increased 1.24 times as compared with a semiconductor device having a structure without the impurity region 14 (impurity concentration of drift region 3 is 1.1 × 10 ¹⁶ cm ⁻³ , breakdown voltage of 97 V). It was also confirmed that the on-resistance was reduced to 79%.

  In a semiconductor device having a similar structure, it was confirmed that when the dimension between the body region 4 and the drain region 6 was 6 μm, the breakdown voltage was 102 V and the on-resistance was reduced to 68%. Thus, it was confirmed that even when the SOI substrate was not used, a high breakdown voltage was obtained, and at the same time, the on-resistance was effective.

  Also in this embodiment, the depth of formation of the impurity region 14 does not depend greatly on the distribution of electric field strength and the withstand voltage as in the above-described embodiment, and may be set as appropriate. Further, the width of the impurity region 14 is not greatly affected by electric field relaxation as long as this region is depleted. Similarly, it is preferable that the edge of the impurity region 14 on the drain region 6 side does not protrude from the edge of the gate electrode 8 on the drain region 6 side.

  As mentioned above, although the Example of this invention was described, it cannot be overemphasized that this invention is not limited to these. For example, not only one impurity region 14 but also a structure in which a plurality of impurity regions 14 are arranged with a predetermined dimension away from the body region 4 may be employed. Even a DMOS transistor having a reversed conductivity type exhibits the same effect.

FIG. 3 is an explanatory diagram of the semiconductor device according to the first embodiment of this invention. It is a calculation result of the electric field strength of the semiconductor device of 1st Example of this invention. It is a calculation result of the electric field strength of the semiconductor device of 2nd Example of this invention. It is explanatory drawing of the semiconductor device of the 3rd Example of this invention. It is explanatory drawing of this kind of conventional semiconductor device. It is the calculation result of the electric field strength of the conventional semiconductor device. It is explanatory drawing of another conventional semiconductor device.

Explanation of symbols

1: p-type silicon substrate, 2: p-type semiconductor layer, 3: drift region, 4: body region, 5: source region, 6: drain region, 7: gate insulating film, 8: gate electrode, 9: source electrode, 10: drain electrode, 11: contact region, 12: silicon support substrate, 13: buried insulating film, 14: semiconductor region

Claims (2)

A one conductivity type body region and a reverse conductivity type drift region selectively formed on the surface of the one conductivity type semiconductor layer;
A reverse conductivity type source region selectively formed on the surface of the body region;
A reverse conductivity type drain region selectively formed on the surface of the drift region;
A gate electrode formed on the body region between the source region and the drift region and the drift region on the source region side through a gate insulating film;
A source electrode connected to the source region;
In a semiconductor device comprising a drain electrode connected to the drain region,
One conductivity type of a structure in which the periphery is surrounded by the drift region in the drift region immediately below the gate insulating film in which the gate electrode is stacked and does not protrude from the drain region side edge of the gate electrode to the drain region side With an impurity region of
The impurity concentration of the impurity region is such that the electric field strength at the electric field maximum point of the junction formed by the impurity region and the drift region is such that the thickness of the drift region portion or the gate insulating film immediately below the gate electrode edge increases. The electric field is dispersed in the impurity region by setting the electric field intensity at a field maximum point at any one of the drift region portion at the boundary and the junction between the drain region and the drift region to be smaller than or substantially coincident with each other. A semiconductor device characterized in that the maximum electric field is reduced .   2. The semiconductor device according to claim 1, wherein the one-conductivity-type semiconductor layer is replaced with a buried insulating film, and the drift region includes a support substrate and a semiconductor layer formed on the buried insulating film, and is selectively applied to the semiconductor layer. The body region is formed in a semiconductor device.

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