JP6381101B2 - Silicon carbide semiconductor device - Google Patents

Description

  The present invention relates to a silicon carbide semiconductor device.

2. Description of the Related Art Conventionally, an insulated gate field effect transistor (MOSFET) is known as a semiconductor device (hereinafter referred to as a silicon carbide semiconductor device) serving as a switching device using silicon carbide (SiC) as a semiconductor material. The structure of a conventional silicon carbide MOSFET will be described by taking an n-channel MOSFET as an example. FIG. 7 is a cross-sectional view showing the structure of a conventional silicon carbide MOSFET. FIG. 8 is a cross-sectional view showing another example of the structure of a conventional silicon carbide MOSFET. As shown in FIG. 7, n-type semiconductor substrate comprised of silicon carbide (hereinafter referred to as n-type SiC substrate) on the front surface of 101, n of silicon carbide ^- type semiconductor layer (hereinafter, n ^- -type SiC 102).

A plurality of p-type regions 103 are selectively provided on the surface layer of the n ⁻ -type SiC layer 102 opposite to the n-type SiC substrate 101 side. Inside the p-type region 103, an n ⁺ -type source region 104 and a p ⁺ -type contact region 105 are selectively provided. Gate insulating film 106 is provided from the surface of the portion of p type region 103 sandwiched between n ⁺ type source region 104 and n ⁻ type SiC layer 102 to the surface of n ⁻ type SiC layer 102. A gate electrode 107 is provided on the surface of the gate insulating film 106. Source electrode 108 is in contact with n ⁺ type source region 104 and p ⁺ type contact region 105. A drain electrode 109 is formed on the back surface of n-type SiC substrate 101.

As another example, as shown in FIG. 8, a p-type semiconductor layer (hereinafter, p-type) made of silicon carbide is formed on the surface of the n ⁻ -type SiC layer 102 opposite to the n-type SiC substrate 101 side. A MOSFET having a structure in which a SiC layer 111 is provided has also been proposed. Specifically, a plurality of p-type regions 110 are selectively provided on the surface layer of the n ⁻ -type SiC layer 102. The p-type SiC layer 111 is provided on the surfaces of the p-type region 110 and the n ⁻ -type SiC layer 102. The p-type SiC layer 111 on the n ⁻ -type SiC layer 102 in the portion where the p-type region 110 is not provided has an n ^- type that penetrates the p-type SiC layer 111 in the depth direction and reaches the n ⁻ -type SiC layer 102. Region 112 is provided.

Further, inside the p-type SiC layer 111 on the p-type region 110, an n ⁺ -type source region 104 and a p ⁺ -type contact region 105 are selectively provided apart from the n-type region 112. Gate insulating film 106 is provided from the surface of the portion of p-type SiC layer 111 sandwiched between n ⁺ -type source region 104 and n-type region 112 to the surface of n-type region 112. A gate electrode 107 is provided on the surface of the gate insulating film 106. Source electrode 108 is in contact with n ⁺ type source region 104 and p ⁺ type contact region 105. A drain electrode 109 is formed on the back surface of n-type SiC substrate 101.

In a state where a positive voltage relative to the source electrode 108 to the drain electrode 109 is applied, if the voltage applied to the gate electrode 107 was set to less gate threshold, the MOSFET shown in FIG. 7, p-type region 103 and n ^- -type Since the pn junction with the SiC layer 102 is in a reverse-biased state, no current flows. In the MOSFET shown in FIG. 8, no current flows because the pn junction between the p-type SiC layer 111 and the n-type region 112 is reverse-biased. That is, between the source and drain of the MOSFET is in an off state.

  On the other hand, when the voltage applied to the gate electrode 107 is equal to or higher than the gate threshold value, an n-type inversion layer is formed along the gate electrode 107 in the p-type region 103 immediately below the gate electrode 107 in the MOSFET shown in FIG. . In the MOSFET shown in FIG. 8, an n-type inversion layer (channel) is formed along the gate electrode 107 in the p-type SiC layer 111 immediately below the gate electrode 107. This n-type inversion layer becomes a current path, and the source and drain of the MOSFET are turned on. Thus, the switching operation of the MOSFET can be controlled by the voltage applied to the gate electrode 107.

  However, when the distance between the p-type base regions (between the p-type regions 103 in FIG. 7 and between the p-type SiC layers 111 in FIG. 8) just below the gate electrode is wide, the electric field applied to the gate insulating film becomes strong and the withstand voltage is increased. There is a problem of lowering. Further, when the interval between the p-type base regions immediately below the gate electrode is narrowed so as not to reduce the breakdown voltage, there is a problem that the on-resistance Ron increases. In order to solve this problem, a method has been proposed in which the n-type impurity concentration in the region sandwiched between the p-type base regions immediately below the gate electrode is increased, thereby suppressing a decrease in breakdown voltage and reducing the on-resistance Ron. Has been.

The following devices have been proposed as such conventional power semiconductor devices. The length of the JFET region that is the region sandwiched between the pair of p wells of the n-type semiconductor layer, that is, the distance between the pair of p wells is 3 μm or less, preferably 0.8 μm or more and 3 μm or less. Further, the impurity density of the JFET region is set to be not less than the impurity density of the drift layer and not less than 1 × 10 ¹⁶ / cm ³ . Preferably, the impurity density of the JFET region and the length of the JFET region satisfy the relationship of (impurity density of the JFET region) ≧ 6.5 × 10 ¹⁶ × (length of the JFET region) ^−1.7 (for example, the following patent document) 1).

JP 2011-159797 A

  However, in Patent Document 1, when the n-type impurity concentration in the region (JFET region) sandwiched between the p-type base regions immediately below the gate electrode is increased in order to achieve the low on-resistance Ron, the breakdown voltage is reduced to some extent. Although the decrease can be suppressed, there is a problem that the breakdown voltage decreases as the n-type impurity concentration increases.

  The present invention provides a silicon carbide semiconductor device capable of suppressing a decrease in breakdown voltage and suppressing an increase in on-resistance in order to eliminate the above-described problems caused by the prior art. Objective.

In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following characteristics. A first conductivity type silicon carbide layer having an impurity concentration lower than that of the silicon carbide substrate is provided on the front surface of the first conductivity type silicon carbide substrate. A base region of the second conductivity type is selectively provided on the surface layer of the first conductivity type silicon carbide layer opposite to the silicon carbide substrate side. A source region of a first conductivity type and a contact region of a second conductivity type are selectively provided inside the base region. A gate insulating film is provided from the surface of the base region between the source region and the first conductivity type silicon carbide layer to the surface of the first conductivity type silicon carbide layer. A gate electrode is provided on the gate insulating film. A source electrode in contact with the source region and the contact region is provided. A drain electrode is provided on the back surface of the silicon carbide substrate. Then, one of the first conductivity type silicon carbide layer, a first portion sandwiched between the adjacent base region, and a second portion along the surface of the silicon carbide substrate side of the base region, only, A first conductivity type semiconductor region having an impurity concentration higher than that of the first conductivity type silicon carbide layer is provided from the first portion to the second portion . The dielectric constant of silicon carbide is ε _s , the elementary charge is q, the built-in voltage of the pn junction between the base region and the first conductivity type semiconductor region is V _bi, and the majority carrier concentration of the base region is When N _A and the majority carrier concentration of the portion of the first conductivity type semiconductor region on the silicon carbide substrate side are N _D , the distance L between adjacent base regions is 2 × (2ε _s / q _{· V bi · N a / N} D / (N a + N D)) 1/2 satisfies the [μm] ≦ L ≦ 3 [ μm]. The first conductivity type semiconductor region includes a first conductivity type high concentration region and a first conductivity type low concentration having a lower impurity concentration than the first conductivity type high concentration region from the gate electrode side to the silicon carbide substrate side. Two sets of regions are alternately arranged. The first conductivity type low concentration region closest to the silicon carbide substrate covers the entire surface of the base region on the silicon carbide substrate side and corners on the silicon carbide substrate side .

  In the silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the base region has a lower impurity concentration on the gate electrode side than on the silicon carbide substrate side.

  In the silicon carbide semiconductor device according to the present invention, in the above-described invention, the first conductivity type semiconductor region is a region formed by ion implantation of a first conductivity type impurity into the first conductivity type silicon carbide layer. It is characterized by.

In order to solve the above-described problems and achieve the object of the present invention, a silicon carbide semiconductor device according to the present invention has the following characteristics. A first conductivity type silicon carbide layer having an impurity concentration lower than that of the silicon carbide substrate is provided on the front surface of the first conductivity type silicon carbide substrate. A first base region of the second conductivity type is selectively provided on the surface layer of the first conductivity type silicon carbide layer opposite to the silicon carbide substrate side. A second conductivity type silicon carbide layer is provided on the surface of the first conductivity type silicon carbide layer opposite to the silicon carbide substrate side. A first conductivity type well region that penetrates the second conductivity type silicon carbide layer in the depth direction and reaches the first conductivity type silicon carbide layer is provided in the second conductivity type silicon carbide layer. A region of the second conductivity type silicon carbide layer excluding the first conductivity type well region becomes a second conductivity type second base region. A source region of a first conductivity type and a contact region of a second conductivity type are selectively provided inside the second base region. A gate insulating film is provided from the surface of the portion of the second base region sandwiched between the source region and the first conductivity type well region to the surface of the second conductivity type silicon carbide layer. A gate electrode is provided on the gate insulating film. A source electrode in contact with the source region and the contact region is provided. A drain electrode is provided on the back surface of the silicon carbide substrate. Then, a first conductivity type well region, said one of the first conductivity type silicon carbide layer, a first portion sandwiched between the adjacent first base region, the silicon carbide substrate side of the first base region A first conductivity type having an impurity concentration higher than that of the first conductivity type silicon carbide layer from the first conductivity type well region to the first portion and the second portion only in the second portion along the surface of the first conductivity type. A semiconductor region is provided. The dielectric constant of silicon carbide is ε _s , the elementary charge is q, the built-in voltage of the pn junction between the first base region and the first conductivity type semiconductor region is V _bi, and the first base region When the majority carrier concentration is N _A and the majority carrier concentration of the first conductivity type semiconductor region on the silicon carbide substrate side is N _D , the distance L between the adjacent first base regions is 2 × meet _{(2ε s / q · V bi} · N a / N D / (N a + N D)) 1/2 [μm] ≦ L ≦ 3 [μm]. The first conductivity type semiconductor region includes a first conductivity type high concentration region and a first conductivity type low concentration having a lower impurity concentration than the first conductivity type high concentration region from the gate electrode side to the silicon carbide substrate side. Two sets of regions are alternately arranged. The first conductivity type low concentration region closest to the silicon carbide substrate covers the entire surface of the first base region on the silicon carbide substrate side and corners on the silicon carbide substrate side .

  In the silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the first conductivity type well region has a higher impurity concentration on the gate electrode side than on the silicon carbide substrate side.

  In the silicon carbide semiconductor device according to the present invention as set forth in the invention described above, the impurity concentration of the second base region is lower than the impurity concentration of the first base region.

The silicon carbide semiconductor device according to the present invention is the above-described invention, wherein the first conductivity type high concentration region and the first conductivity type low concentration region closest to the silicon carbide substrate are the first conductivity type silicon carbide. It is a region formed by ion-implanting a first conductivity type impurity into a layer.

  According to the above-described invention, the first conductivity type semiconductor region having an impurity concentration higher than that of the first conductivity type silicon carbide layer is provided between the adjacent base regions, and the impurity on the gate electrode side of the first conductivity type semiconductor region is provided. By making the concentration higher than the impurity concentration on the silicon carbide substrate side, the on-resistance Ron can be reduced and the breakdown voltage can be prevented from lowering. This reduces the distance between the base regions to 3 μm or less, relaxes the electric field to the gate insulating film, secures a predetermined breakdown voltage, improves the reliability of the gate insulating film, and increases the on-resistance. Can be suppressed.

  According to the silicon carbide semiconductor device of the present invention, it is possible to suppress a decrease in breakdown voltage and to suppress an increase in on-resistance.

1 is a cross sectional view showing a structure of a silicon carbide semiconductor device according to a first embodiment. FIG. 6 is a characteristic diagram showing a relationship between the breakdown voltage and the on-resistance of the MOSFET according to Example 1. FIG. 4 is a cross sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment. FIG. 6 is a cross sectional view showing a structure of a silicon carbide semiconductor device according to a third embodiment. FIG. 10 is a characteristic diagram showing the relationship between the breakdown voltage and on-resistance of a MOSFET according to Example 3; FIG. 6 is a cross sectional view showing a structure of a silicon carbide semiconductor device according to a fourth embodiment. It is sectional drawing which shows the structure of the conventional silicon carbide MOSFET. It is sectional drawing which shows another example of the structure of the conventional silicon carbide MOSFET.

  Hereinafter, preferred embodiments of a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + and − attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

(Embodiment 1)
The structure of the silicon carbide semiconductor device according to the first embodiment will be described by taking an n-channel vertical MOSFET as an example. FIG. 1 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the first embodiment. As shown in FIG. 1, in the silicon carbide semiconductor device according to the first embodiment, an n ⁻ type drift is formed on the front surface of an n-type semiconductor substrate (n-type SiC substrate: silicon carbide substrate) 1 made of silicon carbide. An n ⁻ type semiconductor layer (n ⁻ type SiC layer: first conductivity type silicon carbide layer) 2 made of silicon carbide serving as a region is laminated with a thickness of, for example, 10 μm. The n-type SiC substrate 1 is doped with nitrogen (N) with an impurity concentration of about 1.0 × 10 ¹⁹ / cm ³ , for example. The n ⁻ type SiC layer 2 is an epitaxial layer formed by doping nitrogen with an impurity concentration of, for example, about 1.0 × 10 ¹⁶ / cm ³ .

A plurality of p-type regions (base regions) 3 serving as p-type base regions are selectively provided on the surface layer of the n ⁻ -type SiC layer 2 opposite to the n-type SiC substrate 1 side. The p-type region 3 is doped with aluminum (Al) with an impurity concentration of about 3.0 × 10 ¹⁷ / cm ³ by ion implantation, for example. The interval L between adjacent p-type regions 3 preferably satisfies the following formula (1). In the following equation (1), ε _s is the dielectric constant of silicon carbide (SiC), q is the elementary charge, and V _bi is the pn junction between the p-type region 3 and an n-type region 21 described later. It is a built-in voltage (for example, about 2.5V). N _A is the majority carrier concentration in the p-type region 3, and N _D is the majority carrier concentration in the second n-type region 21b described later.

_{2 × (2ε s / q ·} V bi · N A / N D / (N A + N D)) 1/2 [μm] ≦ L ≦ 3 [μm] ··· (1)

The reason why the interval L between the adjacent p-type regions 3 is set within the range of the above expression (1) is as follows. The left side of the above equation (1) is the upper limit value of the width at which the second n-type region 21b is completely depleted when the applied voltage is 0V. In order to operate the MOS gate (insulated gate made of metal-oxide film-semiconductor) composed of the p-type region 3, the n ⁺ -type source region 4, the gate insulating film 6 and the gate electrode 7, between the adjacent p-type regions 3 Needs to be set to be equal to or larger than the value on the left side of the equation (1). Under the conditions of each region shown in the first embodiment, the lower limit value of the distance L between adjacent p-type regions 3 (that is, the value on the left side of the above equation (1)) is about 0.7 μm, for example. Further, in order to obtain a breakdown voltage of 1200 V or more, it is necessary to set the interval L between adjacent p-type regions 3 to 3 μm or less.

n ^- type SiC layer 2, in a region sandwiched between p-type region 3 adjacent, n ^- high n-type region impurity concentration (a first conductive type semiconductor region) 21 is also provided -type SiC layer 2 ing. By providing the n-type region 21, the n-type impurity concentration in the region sandwiched between the adjacent p-type regions 3 is higher than that of the n ⁻ -type SiC layer 2. Even if it is narrow enough to satisfy the above equation (1), it is possible to suppress an increase in the on-resistance Ron. The n-type region 21 is provided so as not to cover the corner (corner portion) 3a of the p-type region 3 on the n-type SiC substrate 1 side on which the electric field tends to concentrate. Thereby, a sufficiently high breakdown voltage can be maintained.

The n-type region 21 is an impurity of a portion (hereinafter referred to as a first n-type region) 21a on the gate electrode 7 side to be described later than a portion (hereinafter referred to as a second n-type region) 21b on the n-type SiC substrate 1 side. The concentration is high. As a result, the on-resistance Ron can be reduced and the breakdown voltage can be suppressed from decreasing. Specifically, the first n-type region 21a is doped with nitrogen at an impurity concentration of about 4.0 × 10 ¹⁶ / cm ³ by ion implantation, for example. The second n-type region 21b is doped with nitrogen with an impurity concentration of about 2.5 × 10 ¹⁶ / cm ³ by ion implantation, for example.

Further, the impurity concentration of the first n-type region 21a is preferably about 1.5 to 5 times the impurity concentration of the second n-type region 21b, for example. The average impurity concentration of the first n-type region 21a and the second n-type region 21b is preferably about 1.5 to 7.5 times the impurity concentration of the n ⁻ -type SiC layer 2, for example. The reason is that the on-resistance Ron can be reduced and the effect of suppressing the decrease in breakdown voltage can be further enhanced.

Inside the p-type region 3, an n ⁺ -type source region 4 and a p ⁺ -type contact region 5 are selectively provided. The n ⁺ type source region 4 is doped with phosphorus (P) with an impurity concentration of about 2.0 × 10 ²⁰ / cm ³ by ion implantation, for example. The p ⁺ type contact region 5 is arranged on the opposite side of the n ⁺ type source region 4 to the n type region 21 side. The p ⁺ -type contact region 5 is doped with aluminum with an impurity concentration of about 3.0 × 10 ²⁰ / cm ³ by ion implantation, for example.

A gate insulating film 6 is provided from the surface of the p-type region 3 between the n ⁺ -type source region 4 and the n ⁻ -type SiC layer 2 to the surface of the n-type region 21. A gate electrode 7 is provided on the surface. Source electrode 8 is in contact with n ⁺ type source region 4 and p ⁺ type contact region 5 and is electrically insulated from gate electrode 7 by an interlayer insulating film (not shown). A drain electrode 9 is formed on the back surface of the n-type SiC substrate 1 serving as an n-type drain region.

  Next, the operation of the silicon carbide semiconductor device according to the first embodiment will be described. The operation of the silicon carbide semiconductor device according to the first embodiment is the same as that of the conventional silicon carbide semiconductor device (see FIG. 7). That is, by applying a voltage equal to or higher than the threshold voltage to the gate electrode 7 and forming an n-type inversion layer along the gate electrode 7 in the p-type region 3 immediately below the gate electrode 7, Is turned on. On the other hand, by setting the voltage applied to the gate electrode 7 to be equal to or lower than the threshold value, the n-type inversion layer of the p-type region 3 is eliminated, and the source and drain of the vertical MOSFET are turned off.

FIG. 2 shows a simulation result for verifying the breakdown voltage and on-resistance Ron of the silicon carbide semiconductor device according to the first embodiment. Here, for the calculation of the on-resistance Ron, the area of the active part was calculated as 0.121 cm ² . FIG. 2 is a characteristic diagram illustrating the relationship between the breakdown voltage and the on-resistance of the MOSFET according to the first embodiment. FIG. 2 shows the breakdown voltage and on-resistance Ron of a MOSFET (hereinafter, referred to as Example 1) having the structure of the silicon carbide semiconductor device according to the first embodiment on the right side. In Example 1, the impurity concentration of the first n-type region 21a is 4.0 × 10 ¹⁶ / cm ^3, and the impurity concentration of the second n-type region 21b is 2.5 × 10 ¹⁶ / cm ³ . Further, as Comparative Example 1, the breakdown voltage and the on-resistance Ron when the impurity concentrations of the first n-type region 21a and the second n-type region 21b are both 2.5 × 10 ¹⁶ / cm ³ are shown on the left side. As Comparative Example 2, the breakdown voltage and the on-resistance Ron are shown in the center when the impurity concentrations of the first n-type region 21a and the second n-type region 21b are both 3.5 × 10 ¹⁶ / cm ³ . The configuration other than the impurity concentration of the first and second n-type regions 21a and 21b in Comparative Examples 1 and 2 is the same as that in Example 1.

  From the results shown in FIG. 2, in Comparative Example 2 in which the impurity concentrations of the first and second n-type regions 21a and 21b are both higher than those in Comparative Example 1, the on-resistance Ron is reduced by about 10% compared to Comparative Example 1. It has been confirmed that the breakdown voltage is reduced by about 30V. That is, it was confirmed that the breakdown voltage decreases when the impurity concentrations of the first and second n-type regions 21a and 21b are both increased in order to reduce the on-resistance Ron. On the other hand, in Example 1 in which only the impurity concentration of the first n-type region 21a (portion on the gate electrode 7 side of the n-type region 21) is higher than that in Comparative Example 1, the breakdown voltage is maintained at the same level as in Comparative Example 1. However, it was confirmed that the on-resistance Ron can be reduced by about 10% compared to the comparative example 1.

  As described above, according to the first embodiment, the impurity concentration of the portion on the gate electrode side (first n-type region) of the n-type region provided between the p-type base regions is set on the n-type SiC substrate side. By making it higher than the impurity concentration of the portion (second n-type region), it is possible to reduce the on-resistance Ron and to suppress the breakdown voltage from decreasing. As a result, the interval between the p-type base regions is narrowed to a predetermined interval satisfying the above expression (1), the electric field is relaxed to the gate insulating film, and the reliability of the gate insulating film is improved by ensuring a predetermined breakdown voltage. In addition, an increase in on-resistance can be suppressed. Accordingly, even during a switching operation in which a high voltage is applied to the drain electrode, a sufficient breakdown voltage can be secured and an increase in on-resistance can be suppressed.

(Embodiment 2)
Next, the structure of the silicon carbide semiconductor device according to the second embodiment will be described. FIG. 3 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the second embodiment. The silicon carbide semiconductor device according to the second embodiment differs from the silicon carbide semiconductor device according to the first embodiment in that the impurity concentration on the source electrode 8 side in the p-type base region is higher than the impurity concentration on the n-type SiC substrate 1 side. Is also a low point.

Specifically, as shown in FIG. 3, a plurality of p-type regions (first base regions) 10 are formed on the surface layer of the n ⁻ -type SiC layer 2 opposite to the n-type SiC substrate 1 side. It is provided selectively. The p-type region 10 functions as a p-type base region. The p-type region 10 is doped with aluminum at an impurity concentration of about 3.0 × 10 ¹⁸ / cm ³ by ion implantation, for example. An interval L between adjacent p-type regions 10 (a width of a region sandwiched between the p-type regions 10 immediately below the gate electrode 7) L preferably satisfies the above formula (1). The reason is the same as in the first embodiment.

n ^- type SiC layer 2, in a region sandwiched between p-type region 10 adjacent, n ^- a high impurity concentration n-type region (the first conductivity type semiconductor region) 22 is provided than type SiC layer 2 ing. The n-type region 22 is provided so as not to cover the corner 10a of the p-type region 10 on the n-type SiC substrate 1 side where the electric field tends to concentrate. As a result, a sufficiently high breakdown voltage can be maintained as in the first embodiment.

On the surface of p-type region 10 and n-type region 22 (that is, the portion of n ⁻ -type SiC layer 2 where p-type region 10 is not provided), a p-type semiconductor layer (p-type SiC layer: first) made of silicon carbide is formed. 2 conductivity type silicon carbide layer) 11 is laminated with a thickness of 0.5 μm, for example. The impurity concentration of p-type SiC layer 11 is lower than the impurity concentration of p-type region 10. Specifically, the p-type SiC layer 11 is an epitaxial layer formed by doping aluminum with an impurity concentration of, for example, 5.0 × 10 ¹⁵ / cm ³ .

An n-type region (first conductivity type well region) 12 that penetrates the p-type SiC layer 11 in the depth direction and reaches the n-type region 22 is provided in a portion on the n-type region 22 of the p-type SiC layer 11. ing. The n-type region 12 has a higher impurity concentration in the gate electrode 7 side portion (hereinafter referred to as the third n-type region) 12a than in the n ⁻ type SiC layer 2 side portion (hereinafter referred to as the fourth n-type region) 12b. May be. In the n-type region 22, the impurity concentration of the portion (first n-type region) 22 a on the gate electrode 7 side may be higher than the portion (second n-type region) 22 b on the n-type SiC substrate 1 side. If the above conditions are satisfied, the relationship between the impurity concentrations of the fourth n-type region 12b and the first n-type region 22a in contact with each other may be equal or different.

Specifically, the third n-type region 12a is doped with nitrogen at an impurity concentration of about 4.0 × 10 ¹⁶ / cm ³ by, for example, ion implantation, and the fourth n-type region 12b has a 1.. Nitrogen is doped with an impurity concentration of about 5 × 10 ¹⁶ / cm ³ , and the first n-type region 22a is doped with nitrogen with an impurity concentration of about 2.5 × 10 ¹⁶ / cm ³ by ion implantation, for example. The second n-type region 22b is doped with nitrogen with an impurity concentration of about 2.0 × 10 ¹⁶ / cm ³ by ion implantation, for example.

  The first to fourth n-type regions 22a, 22b, 12a, and 12b can be variously changed as long as the above conditions are satisfied. For example, the first to fourth n-type regions 22a, 22b, 12a, and 12b may have different impurity concentrations. The same impurity concentration may be used. Specifically, the impurity concentrations of the first to fourth n-type regions 22a, 22b, 12a, and 12b can be variously changed in accordance with design conditions (such as a balance between a desired breakdown voltage and on-resistance Ron). For example, the first, third, and fourth n-type regions 22a, 12a, and 12b may have the same impurity concentration and a higher impurity concentration than the second n-type region 22b. The first and second n-type regions 22a and 22b have the same impurity concentration and a higher impurity concentration than the fourth n-type region 12b, and the third n-type region 12a has a higher impurity concentration than the fourth n-type region 12b. Is also possible.

In addition, the impurity concentration of any one region or a plurality of regions among the first, third, and fourth n-type regions 22a, 12a, and 12b is about 1.5 to 5 times the impurity concentration of the second n-type region 22b. It is desirable that In addition, the average impurity concentration of the first to fourth n-type regions 22a, 22b, 12a, and 12b is preferably about 1.5 to 7.5 times the impurity concentration of the n ⁻ -type SiC layer 2. The reason is that the on-resistance Ron can be reduced and the effect of suppressing the decrease in breakdown voltage can be further enhanced.

A portion of the p-type SiC layer 11 other than the n-type region 12 (a portion on the p-type region 10 of the p-type SiC layer 11: a second base region) functions as a p-type base region together with the p-type region 10. An n ⁺ type source region 4 and a p ⁺ type contact region 5 are selectively provided in the p type SiC layer 11 apart from the n type region 12. A gate insulating film 6 is provided from the surface of the portion of the p-type SiC layer 11 sandwiched between the n ⁺ -type source region 4 and the n-type region 12 to the surface of the n-type region 12. A gate electrode 7 is provided on the surface. The configuration of n ⁺ type source region 4, p ⁺ type contact region 5, source electrode 8 and drain electrode 9 is the same as that in the first embodiment.

  Next, the operation of the silicon carbide semiconductor device according to the second embodiment will be described. The operation of the silicon carbide semiconductor device according to the second embodiment is the same as that of the conventional silicon carbide semiconductor device (see FIG. 8). That is, by applying a voltage equal to or higher than the threshold voltage to the gate electrode 7 and forming an n-type inversion layer along the gate electrode 7 in the p-type SiC layer 11 immediately below the gate electrode 7, the source / drain of the vertical MOSFET The interval is turned on. On the other hand, by setting the voltage applied to the gate electrode 7 to be equal to or lower than the threshold value, the n-type inversion layer of the p-type SiC layer 11 is eliminated, and the source and drain of the vertical MOSFET are turned off.

  The breakdown voltage and on-resistance Ron of the MOSFET (hereinafter, referred to as Example 2) having the structure of the silicon carbide semiconductor device according to the second embodiment described above were verified. As a result, it was confirmed that Example 2 also showed the same characteristics as Example 1.

  As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, according to the second embodiment, the p-type base region is provided by providing the p-type SiC layer having a lower impurity concentration than the p-type region on the p-type region serving as the p-type base region. Therefore, the allowable range of the impurity concentration of the p-type base region can be made wider than when the impurity concentration is uniform in the depth direction. Specifically, when the impurity concentration of the p-type base region is uniform in the depth direction, when the desired impurity concentration corresponding to the electrical characteristics of the p-type base region is low, the entire p-type base region is applied when a high voltage is applied. Will be depleted and the breakdown voltage will be reduced. Also, when the desired impurity concentration corresponding to the electrical characteristics of the p-type base region is high, no current flows between the source and drain even when a gate voltage is applied, and the MOS gate does not operate. That is, when operating the MOS gate while maintaining the breakdown voltage, the allowable range of the impurity concentration of the p-type base region is narrowed. On the other hand, according to the second embodiment, the impurity concentration of the p-type base region on the n-type SiC substrate side is made higher than the impurity concentration on the gate electrode-side portion. Even when the desired impurity concentration corresponding to the electrical characteristics is low, depletion of the entire p-type base region can be suppressed. In addition, by making the impurity concentration of the p-type base region on the gate electrode side lower than the impurity concentration on the n-type SiC substrate side, the desired impurity concentration corresponding to the electrical characteristics of the p-type base region can be obtained. Even in a high case, the MOS gate can be operated. Therefore, the allowable range of the impurity concentration of the p-type base region can be widened, and the degree of freedom in design can be improved.

(Embodiment 3)
Next, the structure of the silicon carbide semiconductor device according to the third embodiment will be described. FIG. 4 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the third embodiment. The silicon carbide semiconductor device according to the third embodiment is different from the silicon carbide semiconductor device according to the first embodiment in that the n-type region 23 provided between the adjacent p-type regions 3 is changed to the n-type of the p-type region 3. It is the point provided so that the corner | angular part 3a by the side of the SiC substrate 1 may be covered.

  Specifically, as shown in FIG. 4, the depth of the n-type region 23 provided between the adjacent p-type regions 3 (the depth from the interface between the p-type region 3 and the gate insulating film 6, hereinafter, Is simply deeper than the depth of the p-type region 3. For example, the entire p-type region 3 on the n-type SiC substrate 1 side including the corner 3 a on the n-type SiC substrate 1 side of the p-type region 3 is covered with the n-type region 23. In FIG. 4, reference numeral 23 a is a portion of the n-type region 23 on the gate electrode 7 side (first n-type region), and reference symbol 23 b is a portion of the n-type region 23 on the n-type SiC substrate 1 side (second n-type region). ). The configuration other than the depth of n-type region 23 is the same as that of the first embodiment (the n-type region provided between the p-type regions serving as the p-type base region).

FIG. 5 shows a simulation result for verifying the breakdown voltage and on-resistance Ron of the silicon carbide semiconductor device according to the third embodiment. Here, for the calculation of the on-resistance Ron, the area of the active part was calculated as 0.121 cm ² . FIG. 5 is a characteristic diagram illustrating the relationship between the breakdown voltage and the on-resistance of the MOSFET according to the third embodiment. FIG. 5 shows the breakdown voltage and on-resistance Ron of a MOSFET (hereinafter referred to as Example 3) having the structure of the silicon carbide semiconductor device according to the third embodiment on the right side. In Example 3, the impurity concentration of the first n-type region 23a is 4.0 × 10 ¹⁶ / cm ^3, and the impurity concentration of the second n-type region 23b is 2.5 × 10 ¹⁶ / cm ³ . As Comparative Example 3, the breakdown voltage and the on-resistance Ron when the impurity concentrations of the first n-type region 23a and the second n-type region 23b are both 2.5 × 10 ¹⁶ / cm ³ are shown on the left side. As Comparative Example 4, the breakdown voltage and the on-resistance Ron are shown in the center when the impurity concentrations of the first n-type region 23a and the second n-type region 23b are both 3.5 × 10 ¹⁶ / cm ³ . The configuration other than the impurity concentration of the first and second n-type regions 23a and 23b in Comparative Examples 3 and 4 is the same as that in Example 3.

  As shown in FIG. 5, in Comparative Example 4 in which the impurity concentrations of the first and second n-type regions 23a and 23b are both higher than those in Comparative Example 3, the on-resistance Ron is reduced by about 10% compared to Comparative Example 3. It has been confirmed that the breakdown voltage is reduced by about 50V. On the other hand, in Example 3 in which only the impurity concentration of the first n-type region 23a (portion on the gate electrode 7 side of the n-type region 23) is higher than that in Comparative Example 3, the breakdown voltage is maintained at the same level as in Comparative Example 3. However, it was confirmed that the on-resistance Ron can be reduced by about 10% compared to the comparative example 3. Therefore, it was confirmed that Example 3 showed the same characteristics as Example 1. In Example 3, it was confirmed that the on-resistance Ron can be reduced, although the breakdown voltage is slightly lower than that in Example 1 (FIG. 2).

  As described above, according to the third embodiment, the same effect as in the first embodiment can be obtained. Further, according to the third embodiment, the n-type region provided between the adjacent p-type base regions covers the corner of the p-type base region on the n-type SiC substrate side, thereby maintaining the breakdown voltage. However, the on-resistance can be further reduced.

(Embodiment 4)
Next, the structure of the silicon carbide semiconductor device according to the fourth embodiment will be described. FIG. 6 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the fourth embodiment. The silicon carbide semiconductor device according to the fourth embodiment is different from the silicon carbide semiconductor device according to the second embodiment in that the n-type region 24 provided between adjacent p-type regions 10 is replaced with the n-type of the p-type region 10. It is the point provided so that the corner | angular part 10a by the side of the SiC substrate 1 may be covered. That is, the silicon carbide semiconductor device according to the fourth embodiment has a configuration in which the third embodiment is applied to the silicon carbide semiconductor device according to the second embodiment.

  Specifically, as shown in FIG. 6, the depth of the n-type region 24 provided between the adjacent p-type regions 10 (the depth from the interface between the p-type region 10 and the p-type SiC layer 11, below). Is simply deeper than the depth of the p-type region 10. For example, the entire p-type region 10 side including the corner 10 a of the p-type region 10 on the n-type SiC substrate 1 side is covered with the n-type region 24. In FIG. 6, reference numeral 24 a is a portion of the n-type region 24 on the gate electrode 7 side (first n-type region), and reference symbol 24 b is a portion of the n-type region 24 on the n-type SiC substrate 1 side (second n-type region). ). The configuration other than the depth of n-type region 24 is the same as that of the second embodiment (the n-type region provided between the p-type regions serving as the p-type base region).

  The breakdown voltage and on-resistance Ron of the MOSFET (hereinafter referred to as Example 4) having the structure of the silicon carbide semiconductor device according to the fourth embodiment described above were verified. As a result, it was confirmed that Example 4 also showed the same characteristics as Example 3.

  As described above, according to the fourth embodiment, the allowable range of the impurity concentration of the p-type base region can be expanded as in the second embodiment. Further, according to the fourth embodiment, the same effects as those of the third embodiment can be obtained with respect to the dielectric breakdown resistance and reliability of the gate insulating film.

  As described above, the present invention can be variously changed. In each of the above-described embodiments, for example, the dimensions and surface concentration of each part are variously set according to required specifications. Further, in the first and third embodiments described above, the p-type base region is configured such that the impurity concentration on the gate electrode side is lower than the impurity concentration on the n-type SiC substrate side. An effect is obtained. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the silicon carbide semiconductor device according to the present invention is useful for a semiconductor device such as a vertical MOSFET formed on a silicon carbide substrate and used as a switching device.

DESCRIPTION OF SYMBOLS 1 n-type SiC substrate 2 n ^- type SiC layer 3 p-type area | region 3a, 10a The corner | angular part by the side of the n-type SiC substrate of a p-type area | region 4 n ⁺ type source region 5 p ⁺ type contact area 6 Gate insulating film 7 Gate electrode 8 Source electrode 9 Drain electrode 10 P-type region 11 P-type SiC layer 12a Third n-type region 12b Fourth n-type region 21, 22, 23, 24 n-type region 21a, 22a, 23a, 24a First n-type region 21b, 22b, 23b 24b Second n-type region L. Spacing between adjacent p-type regions

Claims (7)

A first conductivity type silicon carbide substrate;
A first conductivity type silicon carbide layer having an impurity concentration lower than that of the silicon carbide substrate, provided on the front surface of the silicon carbide substrate;
A second conductivity type base region selectively provided on a surface layer of the first conductivity type silicon carbide layer opposite to the silicon carbide substrate side;
A first conductivity type source region selectively provided in the base region;
A contact region of a second conductivity type selectively provided inside the base region;
A gate insulating film provided from the surface of the portion of the base region sandwiched between the source region and the first conductivity type silicon carbide layer to the surface of the first conductivity type silicon carbide layer;
A gate electrode provided on the gate insulating film;
A source electrode in contact with the source region and the contact region;
A drain electrode provided on the back surface of the silicon carbide substrate;
Equipped with a,
Among pre Symbol first conductivity type silicon carbide layer, a first portion sandwiched between the adjacent base region, and a second portion along the surface of the silicon carbide substrate side of the base region, only the A first conductivity type semiconductor region having an impurity concentration higher than that of the first conductivity type silicon carbide layer is provided from the first portion to the second portion ,
The dielectric constant of silicon carbide is ε _s , the elementary charge is q, the built-in voltage of the pn junction between the base region and the first conductivity type semiconductor region is V _bi, and the majority carrier concentration of the base region is N _A, and when the majority carrier concentration of the portion of the first conductivity type semiconductor region on the silicon carbide substrate side is N _D ,
An interval L between adjacent base regions is:
_{2 × (2ε s / q ·} V bi · N A / N D / (N A + N D)) 1/2 [μm] ≦ L ≦ 3 [μm]
The filling,
The first conductivity type semiconductor region includes a first conductivity type high concentration region and a first conductivity type low concentration having a lower impurity concentration than the first conductivity type high concentration region from the gate electrode side to the silicon carbide substrate side. Two sets of areas are alternately repeated ,
The first conductivity type low concentration region closest to the silicon carbide substrate covers the entire surface of the base region on the silicon carbide substrate side and a corner portion on the silicon carbide substrate side. .   2. The silicon carbide semiconductor device according to claim 1, wherein the base region has a lower impurity concentration on the gate electrode side than on the silicon carbide substrate side. The first conductive type semiconductor region, the silicon carbide semiconductor device according to claim 1 or 2, a first conductivity type impurity, characterized in that an area formed by ion implantation on the first conductive type silicon carbide layer. A first conductivity type silicon carbide substrate;
A first conductivity type silicon carbide layer having an impurity concentration lower than that of the silicon carbide substrate, provided on the front surface of the silicon carbide substrate;
A first base region of a second conductivity type selectively provided on a surface layer of the first conductivity type silicon carbide layer opposite to the silicon carbide substrate side;
A second conductivity type silicon carbide layer provided on a surface of the first conductivity type silicon carbide layer opposite to the silicon carbide substrate side;
A first conductivity type well region that penetrates the second conductivity type silicon carbide layer in a depth direction and reaches the first conductivity type silicon carbide layer;
A second base region of a second conductivity type that is a region of the second conductivity type silicon carbide layer excluding the first conductivity type well region;
A first conductivity type source region selectively provided in the second base region;
A contact region of a second conductivity type selectively provided in the second base region;
A gate insulating film provided over a surface of a portion of the second base region sandwiched between the source region and the first conductivity type well region and a surface of the second conductivity type silicon carbide layer;
A gate electrode provided on the gate insulating film;
A source electrode in contact with the source region and the contact region;
A drain electrode provided on the back surface of the silicon carbide substrate;
Equipped with a,
Wherein the first conductivity type well region, said one of the first conductivity type silicon carbide layer, a first portion sandwiched between the adjacent first base region, a surface of said silicon carbide substrate side of the first base region A first conductive type semiconductor region having an impurity concentration higher than that of the first conductive type silicon carbide layer from the first conductive type well region to the first portion and the second portion only in the second portion along Is provided,
The dielectric constant of silicon carbide is ε _s , the elementary charge is q, the built-in voltage of the pn junction between the first base region and the first conductivity type semiconductor region is V _bi, and the first base region When the majority carrier concentration is N _A and the majority carrier concentration of the portion on the silicon carbide substrate side of the first conductivity type semiconductor region is N _D ,
An interval L between the adjacent first base regions is:
_{2 × (2ε s / q ·} V bi · N A / N D / (N A + N D)) 1/2 [μm] ≦ L ≦ 3 [μm]
The filling,
The first conductivity type semiconductor region includes a first conductivity type high concentration region and a first conductivity type low concentration having a lower impurity concentration than the first conductivity type high concentration region from the gate electrode side to the silicon carbide substrate side. Two sets of areas are alternately repeated ,
The first conductivity type low concentration region closest to the silicon carbide substrate covers the entire surface of the first base region on the silicon carbide substrate side and the corners on the silicon carbide substrate side. Semiconductor device. The silicon carbide semiconductor device according to claim 4 , wherein the first conductivity type well region has a higher impurity concentration on the gate electrode side than on the silicon carbide substrate side. 6. The silicon carbide semiconductor device according to claim 4 , wherein an impurity concentration of the second base region is lower than an impurity concentration of the first base region. The first conductivity type high concentration region and the first conductivity type low concentration region closest to the silicon carbide substrate are regions formed by ion implantation of a first conductivity type impurity into the first conductivity type silicon carbide layer. The silicon carbide semiconductor device according to claim 4 , wherein the silicon carbide semiconductor device is a silicon carbide semiconductor device.

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