JP2019125621A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of reducing on-resistance.SOLUTION: A semiconductor device comprises: a first electrode; a first region of a first conductivity type disposed above the first electrode; a second region of a second conductivity type having a first thickness, the second region provided on a surface layer part of the first region; a specific region, a region on the surface layer part of the first region, existing while having a thickness equal to or larger than the first thickness so as to be adjacent to the second region; a third region of the first conductivity type having a second thickness thinner than the first thickness, the third region provided on a surface layer part of the second region, where the third region and the specific region are separated by the second region; and a gate electrode disposed on surfaces of the specific region, the second region, and the third region via an insulation film, where at least part of the specific region has a concentration gradient of impurity concentration that is higher as a distance from a boundary surface between the specific region and the second region is greater.SELECTED DRAWING: Figure 1

Description

  The technology disclosed herein relates to a semiconductor device.

  Power MOSFETs designed to handle high power are known. In the power MOSFET, for example, the drift region is disposed above the drain electrode, the body region having the first thickness is disposed in the surface layer portion of the drift region, and the first thickness is provided in the surface portion of the body region Also, the source region having a thin second thickness is disposed, and the source electrode is disposed on a part of the surface of the source region. Patent Document 1 discloses an example of such a power MOSFET.

JP, 2017-005208, A

  In power MOSFETs, it is desirable to reduce the on-resistance. An object of the present specification is to provide a semiconductor device capable of reducing on-resistance.

  The semiconductor device disclosed in the present specification includes a first electrode. The semiconductor device includes a first region which is a semiconductor of a first conductivity type disposed above the first electrode. The semiconductor device is provided in the surface layer portion of the first region, and includes a second region which is a semiconductor of a second conductivity type having a first thickness. The semiconductor device is a region of the surface layer portion of the first region, and includes a specific region which has a thickness equal to or greater than the first thickness and is adjacent to the second region. The semiconductor device is provided in the surface layer portion of the second region, and includes a third region which is a semiconductor of the first conductivity type having a second thickness thinner than the first thickness. The third area and the specific area are separated by the second area. The semiconductor device includes a gate electrode disposed on the surface of the specific region, the surface of the second region, and the surface of the third region via an insulating film. The semiconductor device includes a second electrode disposed on part of the surface of the third region. At least a part of the specific region is provided with a concentration gradient such that the impurity concentration is increased as the distance from the interface between the specific region and the second region is increased.

  The specific region is provided with a concentration gradient such that the impurity concentration is increased as the distance from the interface with the second region is increased. When such a concentration gradient is not provided, current may concentrate and flow in a region near the interface with the second region in the specific region when the semiconductor device is turned on. On the other hand, the semiconductor device disclosed in this specification can form a current path through a region with higher impurity concentration by providing a concentration gradient. That is, the current path can be formed also in the area away from the interface with the second area in the specific area. Since the current concentration can be alleviated, the on-resistance can be reduced.

FIG. 2 schematically shows a cross-sectional view of main parts of the semiconductor device of Example 1; It is a figure which shows the current pathway of the semiconductor device of a comparative example. FIG. 2 is a diagram showing a current path of the semiconductor device of Example 1; 7 schematically shows a cross-sectional view of main parts of the semiconductor device in the first embodiment during the manufacturing process thereof. FIG. 7 schematically shows a cross-sectional view of main parts of the semiconductor device in the first embodiment during the manufacturing process thereof. FIG. 7 schematically shows a cross-sectional view of main parts of the semiconductor device in the first embodiment during the manufacturing process thereof. FIG. 7 schematically shows a cross-sectional view of main parts of the semiconductor device in the first embodiment during the manufacturing process thereof. FIG. 7 schematically shows a cross-sectional view of main parts of the semiconductor device in the first embodiment during the manufacturing process thereof. FIG. 7 schematically shows a cross-sectional view of main parts of the semiconductor device in the first embodiment during the manufacturing process thereof. FIG. 12 schematically shows a cross-sectional view of main parts of the semiconductor device of Example 2; FIG. 12 schematically shows a cross-sectional view of essential parts in the process of manufacturing a semiconductor device in Example 2. FIG. 12 schematically shows a cross-sectional view of essential parts in the process of manufacturing a semiconductor device in Example 2. FIG. 12 schematically shows a cross-sectional view of essential parts in the process of manufacturing a semiconductor device in Example 2. FIG.

  As shown in FIG. 1, the semiconductor device 1 is a semiconductor device of a type called MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device 1 includes a nitride semiconductor layer 10, a drain electrode 22 covering the back surface of the nitride semiconductor layer 10, a source electrode 24 covering a part of the surface of the nitride semiconductor layer 10, and the nitride semiconductor layer 10. A planar gate 30 is provided on part of the surface. The nitride semiconductor layer 10 includes an N-type substrate 11 of N + -type GaN (gallium nitride), a drift region 12 of N-type GaN, a body region 14 of P-type GaN, and a source region 16 of N + -type GaN. A JFET region 13 is disposed in the surface layer portion of drift region 12.

  The drift region 12 is disposed above the drain electrode 22 and the N-type substrate 11. Body region 14 is provided in the surface layer portion of drift region 12 and has a first thickness T1.

  JFET region 13 is adjacent to body region 14 and has a thickness greater than or equal to a first thickness T1. JFET region 13 is disposed between adjacent body regions 14 and exposed to the surface of nitride semiconductor layer 10. The JFET region 13 is a portion protruding from the drift region 12 in a convex shape, and can be said to be a part of the drift region 12.

  The JFET region 13 includes a first layer 13a to a fourth layer 13d. The first layer 13 a is formed on the top surface of the drift region 12 and the side surface of the body region 14. The second layer 13 b is formed on the bottom and the side of the groove formed by the first layer 13 a. The third layer 13c is formed on the bottom and the side of the groove formed by the second layer 13b. The fourth layer 13d is formed inside the groove formed by the third layer 13c.

  The first layer 13a is N-type GaN. The second layer 13 b is N-type GaN. The third layer 13c is N + -type GaN. The fourth layer 13d is N ++-type GaN. That is, the impurity concentration increases as the first layer 13a to the fourth layer 13d are reached. Notations such as N−, N +, N ++, etc. in the first layer 13 a to the fourth layer 13 d indicate relative impurity concentrations in the JFET region 13. It does not show the concentration difference in comparison with the impurity concentration of the N-type substrate 11 or the drift region 12.

  The source region 16 is provided in the surface layer portion of the body region 14 and has a second thickness T2 thinner than the first thickness T1. Source region 16 and JFET region 13 are separated by a distance D 1 by body region 14 in a direction parallel to the surface of nitride semiconductor layer 10. Also, source region 16 is separated from drift region 12 by body region 14 in the depth direction. The planar gate 30 includes a gate insulating film 34 and a gate electrode 32. Gate electrode 32 is disposed on the surface of JFET region 13, the surface of body region 14, and the surface of source region 16 with gate insulating film 34 interposed therebetween. Source electrode 24 is disposed on part of the surface of source region 16. The source electrode 24 is made of, for example, a single or a combination of metal materials such as Pt, Au, Pd, Ni and the like.

(Operation of semiconductor device 1)
The operation at turn-off of the semiconductor device 1 will be described. In the state where the gate electrode 32 and the source electrode 24 are grounded, the semiconductor device 1 is in the turn-off state. At this time, a depletion layer extends from body region 14 into JFET region 13. In the JFET region 13, depletion layers extending from both sides are connected to be in a pinch-off state. Thereby, the electric field applied to the gate insulating film 34 is alleviated, and the dielectric breakdown of the gate insulating film 34 is suppressed, so that the semiconductor device 1 can have a high withstand voltage.

  The turn-on operation of the semiconductor device 1 will be described with reference to FIGS. 2 and 3. FIG. 2 is a diagram showing a current path of the semiconductor device 100 of the comparative example. The semiconductor device 100 of the comparative example is a device in which the impurity concentration of the JFET region 130 is constant. In the semiconductor device 100 of the comparative example, the same components as those of the semiconductor device 1 of this embodiment are denoted by the same reference numerals. FIG. 3 is a diagram showing a current path of the semiconductor device 1 according to the present embodiment. When a positive voltage is applied to drain electrode 22, source electrode 24 is grounded, and a positive voltage higher than the gate threshold is applied to gate electrode 32, an inversion layer is formed in a region of body region 14 facing planar gate 30. IL is formed, and the semiconductor device 1 is turned on. Further, the depletion layer DL extending from the body region 14 into the JFET region 13 is shrunk to release the pinch off state. Thereby, the drain electrode 22 and the source electrode 24 conduct.

  In the semiconductor device 100 of FIG. 2, the impurity concentration of the JFET region 130 and the drift region 120 is low in order to secure the off breakdown voltage. That is, the entire JFET region 130 has a high resistance. Therefore, when the semiconductor device 100 is turned on, current concentrates in the vicinity of the interface F1 between the JFET region 130 and the body region 14 as shown by the current Ion1 in FIG. As a result, the on resistance of the semiconductor device 100 is increased.

  On the other hand, in the semiconductor device 1 of FIG. 3, the region A1 which is at least a partial region of the JFET region 13 has an impurity concentration according to the distance from the interface F2 between the JFET region 13 and the body region 14 in the horizontal direction of FIG. Have a concentration gradient such that That is, in the JFET region 13, there is a current path that has a resistance that decreases with distance from the interface F2. Therefore, when the semiconductor device 1 is turned on, as shown by the current Ion2 in FIG. 3, it is possible to form a current path passing through a region having a higher impurity concentration. That is, compared to the current Ion1 of FIG. 2, the current Ion2 of FIG. 3 can be distributed and flowed in the entire JFET region 13. Since concentration of current in the JFET region 13 can be alleviated, the on-resistance of the semiconductor device 1 can be reduced.

  Further, an electric field is concentrated in the area E1 which is an end portion of the lower surface B1 of the body area 14 when the semiconductor device 1 is turned off. In the semiconductor device 1 of the present embodiment, in the JFET region 13, the second layer 13 b to the fourth layer 13 d having the impurity concentration higher than that of the first layer 13 a having the lowest impurity concentration are above the lower surface B 1 of the body region 14. Is located in Further, only the first layer 13 a having the lowest impurity concentration is in contact with the body region 14. Thus, since the depletion layer in the vicinity of the region E1 can be expanded by forming the low concentration PN junction, electric field concentration in the region E1 can be alleviated. It is possible to secure the withstand voltage of the semiconductor device 1.

(Method of Manufacturing Semiconductor Device 1)
The method of manufacturing the semiconductor device 1 will be described with reference to FIGS. 4 to 9. First, as shown in FIG. 4, the nitride semiconductor layer 10 in which the drift region 12 and the body region 14 are epitaxially grown on the N-type substrate 11 is prepared.

  As shown in FIG. 5, the mask 40 is formed using a known photolithographic technique. A trench TR1 extending in the depth direction from the surface of the nitride semiconductor layer 10 is formed by dry etching. Trench TR1 is formed at a position corresponding to JFET region 13 (see FIG. 1).

  As shown in FIG. 6, the first layer 13 a is epitaxially grown on the surface of the nitride semiconductor layer 10. Thereby, the first layer 13a is formed on the bottom and the side wall of the trench TR1. The impurity concentration of the first layer 13 a is equal to or less than the impurity concentration of the drift region 12. The first layer 13a may be epitaxially grown by MOCVD (Metal Organic Chemical Vapor Deposition) method.

  As shown in FIG. 7, second to fourth layers 13 b to 13 d are epitaxially grown in order on the surface of nitride semiconductor layer 10. The impurity concentration increases as the first layer 13a to the fourth layer 13d are reached. The first layer 13a to the fourth layer 13d can be formed by discontinuously increasing the concentration of impurities contained in the source gas in a stepwise manner. Therefore, additional steps for forming the first layer 13a to the fourth layer 13d are unnecessary, so no additional cost occurs. The first layer 13a to the fourth layer 13d may be continuously grown without opening the chamber of the CVD apparatus.

  As shown in FIG. 8, the first layer 13a to the fourth layer 13d are removed using CMP technology until the surface of the body region 14 is exposed. Thereby, the first layer 13a to the third layer 13c are processed to have a concaved cross section in the trench TR1. The fourth layer 13d is processed into a shape embedded in the groove formed by the third layer 13c. Thereby, a JFET region 13 is formed.

  As shown in FIG. 9, silicon (Si) is implanted into a portion of the body region 14 to form a source region 16 using known photolithography technology and ion implantation technology. The source region 16 is activated by annealing. Next, the gate insulating film 34 is formed and post-annealed using known photolithography technology and dry etching technology.

  Finally, the gate electrode 32 and the source electrode 24 are formed on the upper surface side of the nitride semiconductor layer 10, and the drain electrode 22 is formed on the lower surface side. Thereby, the semiconductor device 1 shown in FIG. 1 is completed.

  FIG. 10 schematically shows a cross-sectional view of main parts of the semiconductor device 1a of the second embodiment. The components substantially similar to those of the semiconductor device 1 of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted. In contrast to the semiconductor device 1 of the first embodiment, the semiconductor device 1a of the second embodiment is characterized in that the JFET region 13 is provided with the low concentration region 13e.

  The effect of the low concentration region 13e will be described. As described above, a high electric field is applied to the region E2 of the lower end portion of the body region 14 when the semiconductor device 1a is off. In the semiconductor device 1a of the second embodiment, the low concentration region 13e is disposed in the region E2. The low concentration region 13 e is GaN having a lower concentration of N-type impurities than the first layer 13 a and the drift region 12. Therefore, it is possible to form a PN junction having a lower concentration than that of the PN junction formed in the region E1 of the first embodiment in the region E2 of the second embodiment. Since the depletion layer in the vicinity of the region E2 can be further spread, it is possible to further increase the breakdown voltage of the semiconductor device 1a.

  The low concentration region 13 e is a layer higher in resistance than the first layer 13 a and the drift region 12. However, by setting the width W1 in the direction parallel to the surface of the nitride semiconductor layer 10 in the low concentration region 13e smaller than the width W2 (see FIG. 3) of the depletion layer DL when the semiconductor device 1a is on, the low concentration A current path can be formed to avoid the region 13e. As a result, the on resistance of the semiconductor device 1a does not increase.

(Method of Manufacturing Semiconductor Device 1a)
A method of manufacturing the semiconductor device 1a will be described with reference to FIGS. The description of the steps substantially common to those of the semiconductor device 1 of the first embodiment will be omitted. After forming the trench TR1 shown in FIG. 5, the process proceeds to FIG.

  As shown in FIG. 11, the low concentration layer 13E is epitaxially grown on the surface of the nitride semiconductor layer 10. Next, as shown in FIG. 12, the low concentration layer 13E is isotropically etched. Thus, low concentration region 13e can be formed in a self-aligned manner at the bottom corner of trench TR1 having a low etching rate.

  As shown in FIG. 13, the first layer 13 a is epitaxially grown on the surface of the nitride semiconductor layer 10. Thereafter, the steps after FIG. 7 of the first embodiment are performed. Thereby, the semiconductor device 1a shown in FIG. 10 is completed.

  As mentioned above, although the specific example of this invention was described in detail, these are only an illustration and do not limit a claim. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings can simultaneously achieve a plurality of purposes, and achieving one of the purposes itself has technical utility.

(Modification)
In the step of forming the JFET region 13 having the concentration gradient (FIG. 6, FIG. 7), the form in which the N-type impurity concentration is discontinuously increased has been described, but the present invention is not limited to this form. The JFET region may be formed while continuously increasing the impurity concentration. As a result, the gradation is continuously provided according to the distance from the interface between the JFET region and the body region, the impurity concentration is increased, and the distance from the interface between the JFET region and the drift region in the vertical upward direction is increased. It is possible to form a JFET region which has gradation continuously and high impurity concentration. Since the interface between layers having different impurity concentrations can be eliminated, it is possible to further disperse the entire JFET region and to flow the on current as compared with the case where the interface of the concentration difference exists.

  Although the case where the JFET region 13 is formed by four layers of the first layer 13a to the fourth layer 13d has been described in this embodiment, the present invention is not limited to this form. Even with three layers or less or five layers or more, it is possible to obtain the effects described in the present specification.

  In this embodiment, the drift region 12, the body region 14, the source region 16, and the JFET region 13 are all made of GaN, but if necessary, some layers and / or regions are made of different semiconductors. It may be done. Examples of different semiconductors include SiC, GaAs, Si, and the like.

  The drain electrode 22 is an example of a first electrode. The N-type is an example of the first conductivity type. The drift region 12 is an example of a first region. The P type is an example of the second conductivity type. The body area 14 is an example of a second area. The JFET region 13 is an example of a specific region. The source region 16 is an example of a third region. The source electrode 24 is an example of a second electrode.

1, 1a: semiconductor device 10: nitride semiconductor layer 12: drift region 13: JFET region 13a: first layer 13b: second layer 13c: third layer 13d: fourth layer 13e: low concentration region 14: body region 16 Source region 22: Drain electrode 24: Source electrode 32: Gate electrode 34: Gate insulating film

Claims (1)

A first electrode,
A first region that is a semiconductor of a first conductivity type disposed above the first electrode;
A second region which is a semiconductor of a second conductivity type provided in the surface layer portion of the first region and having a first thickness;
A specific area which is an area of a surface layer portion of the first area, the specific area having a thickness equal to or greater than the first thickness so as to be adjacent to the second area;
A third region which is a semiconductor of the first conductivity type and is provided in the surface layer portion of the second region and has a second thickness thinner than the first thickness, wherein the third region and the specific region And the third area separated by the second area;
A gate electrode disposed on the surface of the specific region, the surface of the second region, and the surface of the third region via an insulating film;
A second electrode disposed on a part of the surface of the third region;
Equipped with
The semiconductor device according to claim 1, wherein at least a part of the specific region has a concentration gradient such that the impurity concentration is increased as the distance from the interface between the specific region and the second region is increased.

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