JP7073872B2 - Switching element and its manufacturing method - Google Patents

Description

The techniques disclosed herein relate to switching devices and methods of manufacturing them.

The switching element disclosed in Patent Document 1 includes a trench-type gate electrode. The upper surface of the gate electrode is covered with an interlayer insulating layer. The upper surface of the interlayer insulating layer is arranged below the upper surface of the semiconductor substrate. The upper surface of the semiconductor substrate is covered with an upper electrode made of metal. The upper electrode is also arranged in the trench above the interlayer insulating layer. The upper electrode is in contact with the semiconductor substrate on the upper surface of the semiconductor substrate and the side surface of the trench (more specifically, the side surface of the trench located above the interlayer insulating layer). Since the upper electrode is in contact with the semiconductor substrate not only on the upper surface of the semiconductor substrate but also on the side surface of the trench, the contact resistance between the upper electrode and the semiconductor substrate is reduced.

Japanese Unexamined Patent Publication No. 2007-48769

This specification proposes a technique for further reducing the contact resistance of the upper electrode as compared with Patent Document 1.

A semiconductor substrate having a trench on the upper surface thereof, a side insulating layer covering the side surface of the trench, and a bottom insulating layer covering the bottom surface of the trench, which are switching elements, are arranged in the trench and described above. The gate electrode insulated from the semiconductor substrate by the side insulating layer and the bottom insulating layer, the interlayer insulating layer covering the upper surface of the gate electrode, and the side surface of the trench located above the interlayer insulating layer. A side metal compound layer that is in contact with the semiconductor substrate and is composed of a compound of an element and a metal contained in the semiconductor substrate, and is in contact with the semiconductor substrate on the upper surface of the semiconductor substrate and is included in the semiconductor substrate. It has a top metal compound layer composed of a compound of an element and a metal. The semiconductor substrate is in contact with the first conductive type first region in contact with the upper surface metal compound layer, the side metal compound layer, and the side surface insulating layer, and the side surface insulating layer below the first region. It has a second region of the second conductive type, and a third region of the first conductive type that is in contact with the side insulating layer below the second region.

In this switching element, the side metal compound layer and the top metal compound layer form an upper electrode (or a part of the upper electrode). The side metal compound layer is in contact with the semiconductor substrate on the side surface of the trench located above the interlayer insulating layer. The upper surface metal compound layer is in contact with the semiconductor substrate on the upper surface of the semiconductor substrate. That is, the upper electrode is in contact with the semiconductor substrate (particularly, the first region) on the side surface of the trench and the upper surface of the semiconductor substrate. Further, the side metal compound layer and the top metal compound layer are composed of a compound of an element and a metal contained in the semiconductor substrate. Therefore, the contact resistance of the side metal compound layer and the top metal compound layer to the semiconductor substrate is extremely low. Therefore, according to the structure of this switching element, the contact resistance of the upper electrode to the semiconductor substrate (particularly, the first region) can be reduced as compared with the conventional case.

The perspective view of the MOSFET of Example 1. FIG. FIG. 2 is a cross-sectional view taken along the plane II of FIG. FIG. 1 is a cross-sectional view taken along the plane III of FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. The explanatory view of the manufacturing method of the MOSFET of Example 1. FIG. FIG. 2 is a cross-sectional view corresponding to FIG. 2 of the MOSFET of the second embodiment. The explanatory view of the manufacturing method of the MOSFET of Example 2. The explanatory view of the manufacturing method of the MOSFET of Example 2. The explanatory view of the manufacturing method of the MOSFET of Example 2. The explanatory view of the manufacturing method of the MOSFET of Example 2. The explanatory view of the manufacturing method of the MOSFET of Example 2. FIG. 2 is a cross-sectional view corresponding to FIG. 2 of the MOSFET of the third embodiment. The perspective view corresponding to FIG. 1 of the MOSFET of Example 4. FIG. FIG. 2 is a cross-sectional view corresponding to FIG. 2 of the MOSFET of the fourth embodiment.

1 to 3 show the MOSFET (metal-oxide-semiconductor field effect transistor) 10 of the first embodiment. The MOSFET 10 has a semiconductor substrate 12. In the following, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is referred to as the x direction, the direction parallel to the upper surface 12a and orthogonal to the x direction is referred to as the y direction, and the thickness direction of the semiconductor substrate 12 is referred to as the z direction. FIG. 2 is a cross-sectional view taken along the plane II of FIG. 1, and FIG. 3 is a cross-sectional view taken along the plane III of FIG. As shown in FIGS. 2 and 3, a source electrode 70 is provided on the upper surface 12a of the semiconductor substrate 12. In FIG. 1, the source electrode 70 is not shown for the sake of explanation.

The semiconductor substrate 12 is made of silicon carbide (SiC). A plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. As shown in FIG. 1, the plurality of trenches 22 extend parallel to each other on the upper surface 12a. The plurality of trenches 22 extend linearly long in the y direction on the upper surface 12a. The plurality of trenches 22 are arranged at intervals in the x direction. A gate insulating layer 24, a gate electrode 26, and an interlayer insulating layer 28 are arranged inside each trench 22.

The gate insulating layer 24 covers the inner surface of the trench 22. The gate insulating layer 24 has a side insulating layer 24a that covers the side surface of the trench 22 and a bottom insulating layer 24b that covers the bottom surface of the trench 22. The gate insulating layer 24 is made of silicon oxide.

The gate electrode 26 is arranged in the trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating layer 24. The gate electrode 26 is made of polysilicon.

The interlayer insulating layer 28 covers the upper surface of the gate electrode 26. The interlayer insulating layer 28 is made of silicon oxide.

A drain electrode 80 is arranged on the lower surface 12b of the semiconductor substrate 12. The drain electrode 80 is in contact with substantially the entire lower surface 12b of the semiconductor substrate 12.

As shown in FIGS. 2 and 3, a source electrode 70 is arranged on the upper surface 12a of the semiconductor substrate 12. The source electrodes 70 are distributed from the upper surface 12a to the inside of the trench 22. The source electrode 70 covers the upper surface 12a of the semiconductor substrate 12, the side surface of the trench 22 above the interlayer insulating layer 28, and the upper surface of the interlayer insulating layer 28. The source electrode 70 is insulated from the gate electrode 26 by an interlayer insulating layer 28. The source electrode 70 has a nickel silicide layer 72, a titanium silicide layer 74, a barrier metal layer 76, and an aluminum layer 78.

The titanium silicide layer 74 is arranged above the interlayer insulating layer 28. The titanium silicide layer 74 covers the side surface of the trench 22 at a position adjacent to the interlayer insulating layer 28 on the upper side. The titanium silicide layer 74 is composed of a compound of titanium and silicon.

The nickel silicide layer 72 extends from the upper surface 12a of the semiconductor substrate 12 to the inside of the trench 22. The nickel silicide layer 72 is composed of a compound of nickel and silicon. The nickel silicide layer 72 has an upper surface nickel silicide layer 72b that covers the upper surface 12a of the semiconductor substrate 12 and a side surface nickel silicide layer 72a that covers the side surface of the trench 22. The side nickel silicide layer 72a is arranged above the titanium silicide layer 74. The side nickel silicide layer 72a covers the side surface of the trench 22 at a position adjacent to the titanium silicide layer 74 on the upper side. The thickness of the side nickel silicide layer 72a is thinner than the thickness of the top surface nickel silicide layer 72b.

The barrier metal layer 76 extends from the upper surface nickel silicide layer 72b to the inside of the trench 22. The barrier metal layer 76 covers the surfaces of the nickel silicide layer 72, the titanium silicide layer 74, and the interlayer insulating layer 28. The barrier metal layer 76 is made of a metal containing titanium (for example, titanium alone or titanium and aluminum).

The aluminum layer 78 extends from the upper portion of the upper surface 12a of the semiconductor substrate 12 to the inside of the trench 22. The aluminum layer 78 covers the surface of the barrier metal layer 76.

As shown in FIGS. 1 to 3, a plurality of source regions 30, body regions 32, drift regions 34, and drain regions 35 are provided inside the semiconductor substrate 12.

Each source area 30 is an n-type area. As shown in FIGS. 1 and 2, a plurality of source regions 30 are arranged in each of the semiconductor regions (hereinafter referred to as inter-trench regions) sandwiched between two adjacent trenches 22. As shown in FIG. 1, in each inter-trench region, a plurality of source regions 30 are arranged at intervals in the y direction. As shown in FIG. 2, each source region 30 is arranged in a range facing the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the source electrode 70. More specifically, each source region 30 is in ohmic contact with the titanium silicide layer 74, the side nickel silicide layer 72a, and the top surface nickel silicide layer 72b. The contact resistance of the nickel silicide layer 72 to the source region 30 is smaller than the contact resistance of the titanium silicide layer 74 to the source region 30. Each source region 30 is in contact with the side insulating layer 24a on the lower side of the titanium silicide layer 74.

The body region 32 is a p-type region. As shown in FIGS. 1 and 3, the body region 32 has a plurality of body contact regions 32a and a low concentration body region 32b.

Each body contact region 32a is a p-type region having a high concentration of p-type impurities. As shown in FIGS. 1 and 3, each body contact region 32a is provided in the inter-trench region. Each body contact region 32a is arranged in a range facing the upper surface 12a of the semiconductor substrate 12. A plurality of body contact regions 32a are arranged in each inter-trench region. In each trench region, the source region 30 and the body contact region 32a are alternately arranged in the y direction. As shown in FIG. 3, each body contact region 32a is in ohmic contact with the source electrode 70. More specifically, each body contact region 32a is in ohmic contact with the titanium silicide layer 74, the side nickel silicide layer 72a, and the top surface nickel silicide layer 72b. The contact resistance of the titanium silicide layer 74 to the body contact region 32a is smaller than the contact resistance of the nickel silicide layer 72 to the body contact region 32a. Each body contact region 32a is in contact with the side insulating layer 24a under the titanium silicide layer 74.

The low-concentration body region 32b is a p-type region having a lower p-type impurity concentration than each body contact region 32a. As shown in FIGS. 1 to 3, the low-concentration body region 32b is arranged below each source region 30 and each body contact region 32a. The low-concentration body region 32b is in contact with each source region 30 and each body contact region 32a from below. The low-concentration body region 32b is distributed over the entire area below each source region 30 and each body contact region 32a. As shown in FIGS. 2 and 3, the low-concentration body region 32b is in contact with the side insulating layer 24a below each source region 30 and each body contact region 32a. The lower end of the low concentration body region 32b is arranged above the lower end of the gate electrode 26.

The drift region 34 is an n-type region having a low n-type impurity concentration. As shown in FIGS. 1 to 3, the drift region 34 is arranged below the body region 32 (more specifically, the low-concentration body region 32b). The drift region 34 is in contact with the low concentration body region 32b from below. The drift region 34 is separated from each source region 30 by a low concentration body region 32b. The drift region 34 is distributed from the inter-trench region to the region below each trench 22. The drift region 34 is in contact with the side insulating layer 24a below the low concentration body region 32b. Further, the drift region 34 is in contact with the bottom insulating layer 24b.

The drain region 35 is an n-type region having a higher n-type impurity concentration than the drift region 34. As shown in FIGS. 1 to 3, the drain region 35 is arranged below the drift region 34. The drain region 35 is in contact with the drift region 34 from below. The drain region 35 is provided in a range facing the lower surface 12b of the semiconductor substrate 12, and is in ohmic contact with the drain electrode 80.

Next, the operation of the MOSFET 10 will be described. When the MOSFET 10 is used, the potential of the drain electrode 80 is higher than the potential of the source electrode 70. When a potential equal to or higher than the threshold value is applied to the gate electrode 26, a channel is formed in the low concentration body region 32b in the range adjacent to the side insulating layer 24a. Then, electrons flow from the source electrode 70 to the drain electrode 80 via the source region 30, the channel, the drift region 34, and the drain region 35. That is, the MOSFET 10 is turned on. Since the source region 30 is in ohmic contact with the source electrode 70 not only on the upper surface 12a of the semiconductor substrate 12 but also on the side surface of the trench 22, the contact resistance between the source region 30 and the source electrode 70 is small. In particular, since the silicide layer (that is, the titanium silicide layer 74 and the nickel silicide layer 72) is provided at the interface between the source region 30 and the source electrode 70 over the upper surface 12a of the semiconductor substrate 12 and the side surface of the trench 22, the source The contact resistance between the region 30 and the source electrode 70 is extremely small. Further, since the thickness of the side surface nickel silicide layer 72a is thinner than the thickness of the top surface nickel silicide layer 72b, the contact resistance between the source region 30 and the source electrode 70 is further reduced by the side surface nickel silicide layer 72a. Therefore, the MOSFET 10 has a small on-resistance.

Further, in this MOSFET 10, the body contact region 32a is in ohmic contact with the source electrode 70. That is, the low-concentration body region 32b is connected to the source electrode 70 via the body contact region 32a. Therefore, the potential of the low-concentration body region 32b is stable, and the MOSFET 10 can operate stably. In particular, since the body contact region 32a is in ohmic contact with the source electrode 70 not only on the upper surface 12a of the semiconductor substrate 12 but also on the side surface of the trench 22, the contact resistance between the body contact region 32a and the source electrode 70 is small. In particular, since the silicide layer (that is, the titanium silicide layer 74 and the nickel silicide layer 72) is provided at the interface between the body contact region 32a and the source electrode 70 over the upper surface 12a of the semiconductor substrate 12 and the side surface of the trench 22. The contact resistance between the body contact region 32a and the source electrode 70 is extremely small. Therefore, in the MOSFET 10, the loss generated when the carrier moves between the body contact region 32a and the source electrode 70 is small.

Further, in this MOSFET 10, a titanium silicide layer 74 and a side nickel silicide layer 72a are provided on the side surface of the trench 22. Further, the source region 30 and the body contact region 32a are alternately and repeatedly provided along the longitudinal direction of the trench 22. Therefore, the source region 30 and the body contact region 32a are in contact with the titanium silicide layer 74 and the side nickel silicide layer 72a. The titanium silicide layer 74 has a particularly low contact resistance with respect to the body contact region 32a, and the nickel silicide layer 72 has a particularly low contact resistance with respect to the source region 30. Therefore, according to this configuration, the source region 30 and the body contact region 32a can be brought into contact with the source electrode 70 with extremely low contact resistance.

Next, a method for manufacturing the MOSFET 10 will be described with reference to FIGS. 4 to 16. 4 to 16 show a cross section corresponding to FIG. 2. The MOSFET 10 is manufactured from the semiconductor substrate 12 (semiconductor substrate 12 before processing) configured by the drift region 34. First, as shown in FIG. 4, a low-concentration body region 32b and a source region 30 are formed in the semiconductor substrate 12. Further, although not shown, the body contact region 32a is formed at a position corresponding to the cross section of FIG. The body contact region 32a, the low concentration body region 32b, and the source region 30 can be formed by epitaxial growth, ion implantation, or the like.

Next, as shown in FIG. 5, the trench 22 is formed by selectively etching the upper surface 12a of the semiconductor substrate 12. Here, the trench 22 is formed so that the trench 22 penetrates the source region 30, the body contact region 32a, and the low-concentration body region 32b and reaches the drift region 34.

Next, as shown in FIG. 6, an insulating layer 90 made of silicon oxide is formed so as to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the trench 22. The insulating layer 90 covering the bottom surface of the trench 22 is the bottom surface insulating layer 24b, and the insulating layer 90 covering the side surface of the trench 22 is the side surface insulating layer 24a.

Next, as shown in FIG. 6, polysilicon is deposited on the surface of the insulating layer 90. As a result, the gate electrode 26 is formed. The gate electrode 26 is formed above the upper surface 12a of the semiconductor substrate 12 and in the trench 22.

Next, the gate electrode 26 is etched. As a result, as shown in FIG. 7, the gate electrode 26 on the upper surface 12a of the semiconductor substrate 12 is removed. Further, the gate electrode 26 is left in the trench 22. Here, the gate electrode 26 is etched so that the upper surface of the remaining gate electrode 26 is located below the upper surface 12a of the semiconductor substrate 12. Further, the gate electrode 26 is etched so that the upper surface of the remaining gate electrode 26 is located above the lower end of the source region 30.

Next, as shown in FIG. 8, an insulating layer 92 made of silicon oxide is deposited on the surface of the insulating layer 90 and the upper surface of the gate electrode 26. That is, the insulating layer 92 is deposited inside the trench 22 and above the upper surface 12a of the semiconductor substrate 12. Hereinafter, the insulating layer in which the insulating layer 92 and the insulating layer 90 are integrated is referred to as an insulating layer 94.

Next, the insulating layer 94 is etched. As a result, as shown in FIG. 9, the insulating layer 94 on the upper surface 12a of the semiconductor substrate 12 is removed. Further, the insulating layer 94 remains in the trench 22 (that is, on the gate electrode 26). The insulating layer 94 remaining in the trench 22 is the interlayer insulating layer 28. Here, the insulating layer 94 is etched so that the upper surface of the interlayer insulating layer 28 is located below the upper surface 12a of the semiconductor substrate 12. Here, the insulating layer 94 is etched by reactive ion etching (RIE). When etching the insulating layer 94, the insulating layer 94 in the trench 22 is etched after the insulating layer 94 on the upper surface 12a of the semiconductor substrate 12 is removed. Therefore, when the insulating layer 94 in the trench 22 is etched, ions collide with the exposed upper surface 12a of the semiconductor substrate 12, and crystal defects are formed in the semiconductor layer near the upper surface 12a.

Next, as shown in FIG. 10, the nickel layer 96 is deposited on the surface of the semiconductor substrate 12 and the upper surface of the interlayer insulating layer 28. Here, the nickel layer 96 is deposited with a thickness of 50 to 100 nm. The nickel layer 96 is formed so as to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the trench 22 (more specifically, the inner surface of the trench 22 above the upper surface of the interlayer insulating layer 28).

Next, the semiconductor substrate 12 is heated. Here, the semiconductor substrate 12 is heat-treated at a temperature of 700 to 1100 ° C. Then, the nickel in the nickel layer 96 reacts with the silicon in the semiconductor substrate 12. As a result, as shown in FIG. 11, the nickel silicide layer 72 is formed at the interface between the nickel layer 96 and the semiconductor substrate 12. As described above, in the step of etching the insulating layer 94, crystal defects are formed in the semiconductor layer near the upper surface 12a. Therefore, the thickness of the upper surface nickel silicide layer 72b is thicker than the thickness of the side surface nickel silicide layer 72a. Since there is a large manufacturing variation in the amount of crystal defects formed in the semiconductor layer near the upper surface 12a, the manufacturing variation in the thickness of the upper surface nickel silicide layer 72b is large. On the other hand, since crystal defects are not so much formed in the semiconductor layer near the side surface of the trench 22, the manufacturing variation in the thickness of the side surface nickel silicide layer 72a is small. Therefore, the side nickel silicide layer 72a can be formed with a more stable and thinner thickness than the upper surface nickel silicide layer 72b.

Next, as shown in FIG. 12, the nickel layer 96 that has not been silicated is removed by etching.

Next, as shown in FIG. 13, the upper surface of the interlayer insulating layer 28 is moved downward by etching the upper surface of the interlayer insulating layer 28. As a result, the semiconductor substrate 12 (that is, the SiC layer) is exposed in the range 60 of the side surface of the trench 22 which is above the interlayer insulating layer 28 and below the side nickel silicide layer 72a.

Next, as shown in FIG. 14, the barrier metal layer 76 (the barrier metal layer 76) covers the upper surface of the interlayer insulating layer 28, the side surface of the trench 22 above the upper surface of the interlayer insulating layer 28, and the upper surface of the upper surface nickel silicide layer 72b. A layer of metal containing titanium) is deposited. Therefore, the surface of the semiconductor substrate 12 within the range 60 is covered with the barrier metal layer 76. Here, the barrier metal layer 76 is formed with a thickness of 50 to 100 nm.

Next, the semiconductor substrate 12 is heated. Here, the semiconductor substrate 12 is heat-treated at a temperature of 700 to 950 ° C. Then, within the range 60, the titanium in the barrier metal layer 76 and the silicon in the semiconductor substrate 12 react with each other. As a result, as shown in FIG. 15, the titanium silicide layer 74 is formed at the interface between the barrier metal layer 76 and the semiconductor substrate 12.

Next, as shown in FIG. 16, the aluminum layer 78 is deposited on the surface of the barrier metal layer 76 (that is, the upper part of the upper surface 12a and the inside of the trench 22). This completes the source electrode 70.

After that, by forming the drain region 35 and the drain electrode 80, the MOSFET 10 shown in FIGS. 1 to 3 is completed.

As described above, according to this manufacturing method, a silicide layer (nickel silicide layer 72 and titanium silicide layer 74) is provided on the side surface of the trench 22 above the interlayer insulating layer 28 and the upper surface 12a of the semiconductor substrate 12. The MOSFET 10 can be manufactured. Therefore, the source electrode 70 can be brought into contact with the source region 30 and the body contact region 32a with low contact resistance. In particular, since the nickel silicide layer 72 can be brought into contact with the source region 30 and the titanium silicide layer 74 can be brought into contact with the body contact region 32a, the source electrode has a low contact resistance with respect to both the source region 30 and the body contact region 32a. 70 can be brought into contact.

Further, in this manufacturing method, the side surface nickel silicide layer 72a can be formed more stably and thinner than the upper surface nickel silicide layer 72b. Therefore, on the side surface of the trench 22, the source electrode 70 can be brought into contact with the source region 30 with an extremely low contact resistance, and the manufacturing variation of the contact resistance with respect to the source region 30 of the source electrode 70 can be suppressed.

Further, in the semiconductor substrate 12 made of SiC, when the source region 30 is formed by ion implantation of n-type impurities, the n-type impurity concentration on the upper surface 12a is lower than the n-type impurity concentration at the deep position. Therefore, when the source region 30 comes into contact with the source electrode 70 on the side surface of the trench 22, the source region 30 comes into contact with the source electrode 70 at a portion where the concentration of n-type impurities is higher than that of the upper surface 12a. This also reduces the contact resistance of the source electrode 70 to the source region 30.

FIG. 17 shows a cross-sectional view corresponding to FIG. 2 of the MOSFET of the second embodiment. The MOSFET of the second embodiment is different from the MOSFET 10 of the first embodiment in that it does not have the barrier metal layer 76 and the positions of the nickel silicide layer 72 and the titanium silicide layer 74 are interchanged. Other configurations of the MOSFET of the second embodiment are equal to the MOSFET 10 of the first embodiment.

In the MOSFET of the second embodiment, the nickel silicide layer 72 covers the side surface of the trench 22 at a position adjacent to the interlayer insulating layer 28 on the upper side. Further, in the MOSFET of the second embodiment, the titanium silicide layer 74 covers the side surface of the trench 22 at a position adjacent to the nickel silicide layer 72 on the upper side. The titanium silicide layer 74 also covers the upper surface 12a of the semiconductor substrate 12.

Also in the configuration of the second embodiment, the source region 30 and the body contact region 32a can come into contact with the source electrode 70 with a low contact resistance.

In the MOSFET manufacturing process of the second embodiment, processing is performed up to the stage shown in FIG. 9 by the same method as the manufacturing method of the first embodiment. Next, as shown in FIG. 18, a metal layer 62 made of a metal containing titanium is deposited. Here, the metal layer 62 is formed so as to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the trench 22. Here, the metal layer 62 is formed with a thickness of 50 to 100 nm.

Next, the semiconductor substrate 12 is heated. Here, the semiconductor substrate 12 is heat-treated at a temperature of 700 to 1100 ° C. Then, the titanium in the metal layer 62 and the silicon in the semiconductor substrate 12 react with each other. As a result, as shown in FIG. 19, the titanium silicide layer 74 is formed at the interface between the metal layer 62 and the semiconductor substrate 12. Here, since there are few crystal defects existing in the semiconductor layer near the side surface of the trench 22, the thickness of the side surface titanium silicide layer 74a is thinner than the thickness of the upper surface titanium silicide layer 74b. Therefore, the resistance of the side titanium silicide layer 74a can be reduced. Then, the unreacted metal layer 62 is removed by etching.

Next, as shown in FIG. 20, the upper surface of the interlayer insulating layer 28 is moved downward by etching the upper surface of the interlayer insulating layer 28. Then, the semiconductor substrate 12 is exposed in the range 64 between the interlayer insulating layer 28 and the side titanium silicide layer 74a on the side surface of the trench 22.

Next, as shown in FIG. 21, a nickel layer 98 is deposited so as to cover the upper surface of the interlayer insulating layer 28, the side surface of the trench 22 above the upper surface of the interlayer insulating layer 28, and the upper surface of the upper surface titanium silicide layer 74b. Let me. Here, the nickel layer 98 is formed with a thickness of 50 to 100 nm.

Next, the semiconductor substrate 12 is heated. Here, the semiconductor substrate 12 is heat-treated at a temperature of 700 to 950 ° C. Then, within the range 64, the nickel in the nickel layer 98 reacts with the silicon in the semiconductor substrate 12. As a result, as shown in FIG. 22, the nickel silicide layer 72 is formed at the interface between the nickel layer 98 and the semiconductor substrate 12. Next, the unreacted nickel layer 98 is removed. After that, the MOSFET shown in FIG. 17 is completed by forming the aluminum layer 78, the drain region 35, and the drain electrode 80.

FIG. 23 shows the MOSFET of the third embodiment. The MOSFETs of Examples 1 and 2 had a nickel silicide layer 72 and a titanium silicide layer 74. On the other hand, the MOSFET of the third embodiment has the nickel silicide layer 72, but does not have the titanium silicide layer 74. Further, the MOSFET of the third embodiment does not have the barrier metal layer 76. The other configurations of the MOSFET of the third embodiment are the same as those of the MOSFET of the first embodiment.

In the MOSFET of the third embodiment, the nickel silicide layer 72 is provided on the entire interface between the source electrode 70 and the semiconductor substrate 12. The nickel silicide layer 72 has an extremely low contact resistance with respect to the n-type source region 30, while having a relatively low contact resistance with respect to the p-type body contact region 32a. In the MOSFET of the third embodiment, the source electrode 70 contacts the source region 30 and the body contact region 32a with a low contact resistance not only on the upper surface 12a of the semiconductor substrate 12 but also on the inner surface of the trench 22. Therefore, even with the MOSFET of the third embodiment, loss is unlikely to occur.

In the MOSFET manufacturing process of the third embodiment, processing is performed up to the stage shown in FIG. 12 by the same method as the manufacturing method of the first embodiment. Next, the source electrode 70 shown in FIG. 23 is completed by forming the aluminum layer 78 so as to cover the surface of the nickel silicide layer 72 and the upper surface of the interlayer insulating layer 28. After that, the MOSFET shown in FIG. 23 is completed by forming the drain region 35 and the drain electrode 80.

24 and 25 show the MOSFET of the fourth embodiment. In FIG. 24, the source electrode 70 is not shown. As shown in FIG. 25, the source electrode 70 of the MOSFET of the fourth embodiment has the same structure as the source electrode 70 of the MOSFET of the third embodiment. In the MOSFET of the fourth embodiment, the source electrode 70 can be formed by the same manufacturing method as the MOSFET of the third embodiment. As shown in FIGS. 24 and 25, in the MOSFET of the fourth embodiment, the arrangement of the source region 30 and the body contact region 32a is different from that of the MOSFET of the third embodiment. The other configurations of the MOSFET of the fourth embodiment are the same as those of the MOSFET of the third embodiment.

In the MOSFET of the third embodiment, as shown in FIG. 1, the source region 30 and the body contact region 32a are alternately and repeatedly provided in the y direction. On the other hand, in the MOSFET of the fourth embodiment, as shown in FIG. 24, the source region 30 extends long in the y direction along the side surface of the trench 22. The body contact region 32a is arranged at a position not in contact with the side surface of the trench 22. Therefore, the source electrode 70 (that is, the side nickel silicide layer 72a) comes into contact with the source region 30 in substantially the entire area of the side surface of the trench 22 above the interlayer insulating layer 28. According to this configuration, the source electrode 70 can be brought into contact with the source region 30 with a lower contact resistance.

In the above-mentioned Examples 1 to 4, the semiconductor substrate 12 is made of SiC, but the semiconductor substrate may be made of another material. For example, when the semiconductor substrate is made of a gallium-based material (GaN, GaAs, GaP, etc.), the material (for example, gallium) and the metal (for example, gallium) constituting the semiconductor substrate are present at the interface between the source electrode and the semiconductor substrate. , Titanium) compound) can be provided.

Further, in Examples 1 to 4 described above, the source region 30, the body contact region 32a, and the low-concentration body region 32b were formed before the trench 22 was formed. However, at least one of the source region 30, the body contact region 32a, and the low concentration body region 32b may be formed after the trench 22 is formed.

Further, although the MOSFET has been described in Examples 1 to 4 described above, the technique disclosed in the present specification may be applied to a switching element other than the MOSFET (for example, an IGBT (insulated gate bipolar transistor) or the like).

The relationship between the components of the embodiment and the components of the claims will be described below. The side surface nickel silicide layer 72a of the embodiment is an example of the side surface metal compound layer of the claim. The side surface nickel silicide layer 72a of Example 1 is an example of the first side surface metal compound layer according to the claim. The upper surface nickel silicide layer 72b of Example 1 is an example of the upper surface metal compound layer of the claim. The titanium silicide layer 74 of Example 1 is an example of the second side surface metal compound layer of the claim. The side surface titanium silicide layer 74a of Example 2 is an example of the first side surface metal compound layer according to the claim. The upper surface titanium silicide layer 74b of Example 2 is an example of the upper surface metal compound layer of the claim. The nickel silicide layer 72 of Example 2 is an example of the second side surface metal compound layer of the claim. The side surface nickel silicide layer 72a of Examples 3 and 4 is an example of the side surface metal compound layer according to the claim. The upper surface nickel silicide layer 72b of Examples 3 and 4 is an example of the upper surface metal compound layer of the claim. The source area 30 of Examples 1 to 4 is an example of the first area of the claim . The drift region 34 of Examples 1 to 4 is an example of the third region of the claim. The body contact area 32a of Examples 1 to 4 is an example of the contact area of the claim. The low-concentration body region 32b of Examples 1 to 4 is an example of the low-concentration region of the claim. The nickel layer 96 of the first embodiment is an example of the upper surface metal layer and the first side surface metal layer according to the claim. The metal layer 62 of the second embodiment is an example of the upper surface metal layer and the first side surface metal layer according to the claim. The barrier metal layer 76 of the first embodiment is an example of the second side metal layer of the claim. The nickel layer 98 of Example 2 is an example of the second side metal layer of the claim.

The technical elements disclosed herein are listed below. The following technical elements are useful independently.

In the switching element of the example disclosed herein, the thickness of the side metal compound layer may be thinner than the thickness of the upper surface metal compound layer.

By making the thickness of the side metal compound layer thinner than the thickness of the upper surface metal compound layer, the resistance of the side metal compound layer can be reduced. According to this structure, the resistance of the upper electrode can be further reduced.

In the example switching element disclosed herein, the semiconductor substrate may contain silicon. Further, the side metal compound layer and the top metal compound layer may be composed of silicide.

According to silicide, the contact resistance of the side metal compound layer and the top metal compound layer to the semiconductor substrate can be reduced.

In the switching element of the example disclosed in the present specification, the side metal compound layer is a first side metal compound layer composed of a compound of an element contained in a semiconductor substrate and a first metal, and an element contained in the semiconductor substrate. It may have a second side metal compound layer composed of a compound of a second metal different from that of the first metal. The second region may have a contact region and a low concentration region in contact with the contact region and having a lower concentration of the second conductive impurity than the contact region. The first region may be in contact with the first side metal compound layer. The contact region may be in contact with the second side surface metal compound layer. The low concentration region may be in contact with the side insulating layer below the first region.

According to this configuration, the first side surface metal compound layer can be composed of a metal compound having a low contact resistance to the first region, and the second side surface metal compound layer can be composed of a metal compound having a low contact resistance to the contact region. Low contact resistance can be achieved for both the first region and the contact region.

In the switching element of the example disclosed herein, the second side surface metal compound layer may be arranged below the first side surface metal compound layer.

In the switching element of the example disclosed in the present specification, the semiconductor substrate may be made of SiC. The first side surface metal compound layer and the top surface metal compound layer may be composed of nickel silicide. The second side surface metal compound layer may be made of titanium silicide.

According to this configuration, low contact resistance can be realized for both the first region and the contact region.

In the switching element of the example disclosed in the present specification, the first region and the contact region may be alternately and repeatedly provided along the longitudinal direction of the trench on the upper surface of the semiconductor substrate.

This specification proposes a new method for manufacturing a switching element. This manufacturing method includes a step of forming a trench on the upper surface of the semiconductor substrate, a step of forming a side insulating layer covering the side surface of the trench and a bottom insulating layer covering the bottom surface of the trench, and a step of forming the inside of the trench and the semiconductor substrate. In the step of depositing the gate electrode on the upper part of the upper surface and the step of etching the gate electrode, the gate electrode on the upper part of the upper surface of the semiconductor substrate is removed, and the gate electrode remaining in the trench is used. The step of leaving the gate electrode in the trench so that the upper surface is located below the upper surface of the semiconductor substrate, and the upper part of the upper surface of the gate electrode remaining in the trench and the semiconductor substrate. In the step of depositing the interlayer insulating layer on the upper part of the upper surface and the step of etching the interlayer insulating layer, the interlayer insulating layer on the upper part of the upper surface of the semiconductor substrate is removed and the interlayer remaining in the trench is removed. The step of leaving the interlayer insulating layer in the trench so that the upper surface of the insulating layer is located below the upper surface of the semiconductor substrate, and in the upper surface metal layer covering the upper surface of the semiconductor substrate and in the trench. A step of forming a first side surface metal layer covering the side surface of the trench above the upper surface of the remaining interlayer insulating layer, and a step of heating the semiconductor substrate, wherein the first side surface metal layer and the said. It has a step of forming a first side surface metal compound layer by reacting with a semiconductor substrate and forming a top surface metal compound layer by reacting the upper surface metal layer with the semiconductor substrate. The switching element forms a first conductive type first region in contact with the upper surface metal compound layer, the first side surface metal compound layer, and the side surface insulating layer, and the side surface insulating layer below the first region. It has a second region of the second conductive type that is in contact with the second region, and a third region of the first conductive type that is in contact with the side surface insulating layer below the second region.

The first region, the second region, and the third region may be formed at any timing. For example, a part or all of the first region, the second region, and the third region may be formed before the trench, or may be formed after the gate electrode is formed.

According to this manufacturing method, a switching element having a side metal compound layer and a top metal compound layer can be manufactured.

In the manufacturing method of the example disclosed in the present specification, in the step of etching the interlayer insulating layer, the interlayer insulating layer may be etched by reactive ion etching. Further, the thickness of the first side surface metal compound layer may be thinner than the thickness of the top surface metal compound layer.

In this manufacturing method, in the step of etching the interlayer insulating film, the upper surface of the semiconductor substrate is damaged, while the side surface of the trench is hardly damaged. Therefore, in the step of forming the first side surface metal compound layer and the upper surface metal compound layer, the first side surface metal layer is formed thinner than the upper surface metal compound layer. By making the thickness of the first side surface metal compound layer thinner than the thickness of the upper surface metal compound layer, the resistance of the side surface metal compound layer can be reduced.

In the manufacturing method of the example disclosed in the present specification, the semiconductor substrate may contain silicon, and the first side surface metal compound layer and the top surface metal compound layer may be composed of silicide.

According to silicide, the contact resistance of the side metal compound layer and the top metal compound layer to the semiconductor substrate can be reduced.

In the manufacturing method of one example disclosed in the present specification, the upper surface of the interlayer insulating layer is lowered by etching the interlayer insulating layer remaining in the trench after the step of forming the first side metal compound layer and the upper surface metal compound layer. The second side surface is composed of a metal different from the first side metal layer while covering the surface of the semiconductor substrate exposed on the side surface of the trench by moving the upper surface of the interlayer insulating layer to the lower side. It may further have a step of forming the metal layer and a step of forming the second side surface metal compound layer by heating the semiconductor substrate and reacting the second side surface metal layer with the semiconductor substrate. The second region may have a contact region and a low concentration region in contact with the contact region and having a lower concentration of the second conductive impurity than the contact region. The contact region may be in contact with the second side surface metal compound layer. The low concentration region may be in contact with the side insulating layer below the first region.

According to this configuration, the first side surface metal compound layer can be composed of a metal compound having a low contact resistance to the first region, and the second side surface metal compound layer can be composed of a metal compound having a low contact resistance to the contact region. Low contact resistance can be achieved for both the first region and the contact region.

In the manufacturing method of the example disclosed in the present specification, the semiconductor substrate is made of SiC, the first side metal compound layer and the top metal compound layer are made of nickel silicide, and the second side metal compound layer is made of nickel silicide. It may be composed of titanium silicide.

According to this configuration, low contact resistance can be realized for both the first region and the contact region.

In the manufacturing method of the example disclosed in the present specification, the first region and the contact region may be alternately and repeatedly provided along the longitudinal direction of the trench on the upper surface of the semiconductor substrate.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples exemplified above. The technical elements described herein or in the drawings exhibit their technical usefulness, either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in the present specification or the drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

12: Semiconductor substrate 22: Trench 24: Gate insulating layer 24a: Side insulating layer 24b: Bottom insulating layer 26: Gate electrode 28: Interlayer insulating layer 30: Source region 32: Body region 32a: Body contact region 32b: Low concentration body region 34: Drift region 35: Drain region 70: Source electrode 72: Nickel silicide layer 72a: Side nickel silicide layer 72b: Top surface nickel silicide layer 74: Titanium silicide layer 76: Barrier metal layer 78: Aluminum layer 80: Drain electrode

Claims (7)

It is a switching element
A semiconductor substrate with a trench on the top surface and
A side insulating layer covering the side surface of the trench and
A bottom insulating layer that covers the bottom of the trench and
A gate electrode arranged in the trench and insulated from the semiconductor substrate by the side insulating layer and the bottom insulating layer.
An interlayer insulating layer covering the upper surface of the gate electrode and
A side metal compound layer that is in contact with the semiconductor substrate at the side surface of the trench located above the interlayer insulating layer and is composed of a compound of an element and a metal contained in the semiconductor substrate.
An upper surface metal compound layer that is in contact with the semiconductor substrate on the upper surface of the semiconductor substrate and is composed of a compound of an element and a metal contained in the semiconductor substrate.
Have,
The semiconductor substrate is
The first region of the first conductive type in contact with the upper surface metal compound layer, the side surface metal compound layer, and the side surface insulating layer,
The second region of the second conductive type, which is in contact with the side insulating layer on the lower side of the first region,
The third region of the first conductive type, which is in contact with the side insulating layer on the lower side of the second region ,
Second conductive type contact area,
Have,
The first side metal compound layer in which the side metal compound layer is composed of a compound of an element contained in the semiconductor substrate and the first metal, and the element contained in the semiconductor substrate and the first metal are different from each other. It has a second side metal compound layer composed of a compound with two metals,
The second region has a low concentration region that is in contact with the contact region and has a lower concentration of the second conductive impurity than the contact region.
The first region is in contact with the first side metal compound layer, and the first region is in contact with the first side metal compound layer.
The contact region is in contact with the second side surface metal compound layer, and the contact region is in contact with the second side surface metal compound layer.
The low concentration region is in contact with the side insulating layer below the first region.
Switching element. The switching element according to claim 1 , wherein the second side surface metal compound layer is arranged below the first side surface metal compound layer. The semiconductor substrate is made of SiC (silicon carbide).
The first side surface metal compound layer and the top surface metal compound layer are composed of nickel silicide.
The second side surface metal compound layer is made of titanium silicide.
The switching element according to claim 1 or 2 . The switching element according to any one of claims 1 to 3 , wherein the first region and the contact region are alternately and repeatedly provided along the longitudinal direction of the trench on the upper surface of the semiconductor substrate. It is a manufacturing method of switching elements.
The process of forming a trench on the upper surface of the semiconductor substrate and
A step of forming a side insulating layer covering the side surface of the trench and a bottom insulating layer covering the bottom surface of the trench.
A step of depositing a gate electrode in the trench and on the upper surface of the semiconductor substrate.
In the step of etching the gate electrode, the gate electrode on the upper surface of the semiconductor substrate is removed, and the upper surface of the gate electrode remaining in the trench is lower than the upper surface of the semiconductor substrate. The step of leaving the gate electrode in the trench so that it is located, and
A step of depositing an interlayer insulating layer on the upper surface of the upper surface of the gate electrode and the upper surface of the semiconductor substrate remaining in the trench.
In the step of etching the interlayer insulating layer, the interlayer insulating layer above the upper surface of the semiconductor substrate is removed, and the upper surface of the interlayer insulating layer remaining in the trench is larger than the upper surface of the semiconductor substrate. The step of leaving the interlayer insulating layer in the trench so as to be located on the lower side, and
A step of forming a top metal layer covering the upper surface of the semiconductor substrate and a first side metal layer covering the side surface of the trench above the upper surface of the interlayer insulating layer remaining in the trench.
In the step of heating the semiconductor substrate, the first side surface metal layer and the semiconductor substrate are reacted to form a first side surface metal compound layer, and the top surface metal layer and the semiconductor substrate are reacted. The process of forming the upper surface metal compound layer by
A step of moving the upper surface of the interlayer insulating layer downward by etching the interlayer insulating layer remaining in the trench after the step of forming the first side surface metal compound layer and the upper surface metal compound layer. ,
A second side metal that covers the surface of the semiconductor substrate exposed on the side surface of the trench by moving the upper surface of the interlayer insulating layer downward, and is made of a metal different from the first side metal layer. The process of forming the layer and
A step of forming a second side surface metal compound layer by heating the semiconductor substrate and reacting the second side surface metal layer with the semiconductor substrate.
Have,
The switching element
The first region of the first conductive type in contact with the upper surface metal compound layer, the first side surface metal compound layer, and the side surface insulating layer,
The second region of the second conductive type, which is in contact with the side insulating layer on the lower side of the first region,
The third region of the first conductive type, which is in contact with the side insulating layer on the lower side of the second region ,
Second conductive type contact area,
Have,
The second region has a low concentration region that is in contact with the contact region and has a lower concentration of the second conductive impurity than the contact region.
The contact region is in contact with the second side surface metal compound layer, and the contact region is in contact with the second side surface metal compound layer.
The low concentration region is in contact with the side insulating layer below the first region.
Manufacturing method of switching element. The semiconductor substrate is made of SiC (silicon carbide).
The first side surface metal compound layer and the top surface metal compound layer are composed of nickel silicide.
The second side surface metal compound layer is made of titanium silicide.
The method for manufacturing a switching element according to claim 5 . On the upper surface of the semiconductor substrate, the first region and the contact region are alternately and repeatedly provided along the longitudinal direction of the trench.
The method for manufacturing a switching element according to claim 5 or 6 , wherein the switching element is manufactured.

Images