JP2021082713A - Semiconductor device - Google Patents

Abstract

To provide a technique for further improving the withstand voltage of a semiconductor device having a groove formed at a terminal part by further reducing electric field concentration at an end part of a pn junction surface.SOLUTION: A semiconductor device comprises a semiconductor layer which has an element part having an element structure formed and a terminal part enclosing the element part, the semiconductor layer having an inclined surface formed from an outer peripheral end of the element part to the terminal part of the semiconductor layer with a groove formed on one principal surface of the terminal part. The semiconductor layer has a drift region of a first conductivity type, a body region of a second conductivity type provided on the drift region, and an electric field relaxing region of the second conductivity type, wherein the groove is deeper than a pn junction surface between the drift region and body region, and the electric field relaxing region is arranged extending from a position which is nearby an end part of the pn junction surface between the drift region and body region and in contact with a part of the inclined surface to a position deeper than the pn junction surface.SELECTED DRAWING: Figure 1

Description

The techniques disclosed herein relate to semiconductor devices.

Development of a vertical semiconductor device in which a current flows through a semiconductor layer along the thickness direction is underway. The semiconductor layer of this type of semiconductor device has a structure in which an n-type drift region and a p-type body region are laminated.

In this type of semiconductor device, a technique is known in which a groove is formed at the end portion of a semiconductor layer and an inclined surface is formed from the outer peripheral end of the element portion toward the end portion, and an example thereof is disclosed in Patent Document 1. ing. The groove formed at the end portion is formed deeper than the pn junction surface of the drift region and the body region. When such a groove is formed, the pn junction surface of the drift region and the body region is exposed to the inclined surface of the groove, the electric field concentration near the end of the pn junction surface is relaxed, and the withstand voltage is improved. It is said that.

Patent Document 2 discloses a technique for further improving the pressure resistance by reducing the inclination angle of the inclined surface to 45 ° or less.

Japanese Unexamined Patent Publication No. 11-74524 Japanese Unexamined Patent Publication No. 2003-68768

In a semiconductor device having a groove formed at the end portion, there is a need for a technique for further relaxing the electric field concentration near the end portion of the pn junction surface and further improving the withstand voltage.

The semiconductor device disclosed in the present specification can include a semiconductor layer having an element portion on which an element structure is formed and a terminal portion surrounding the element portion. In the semiconductor layer, an inclined surface is formed from the outer peripheral end of the element portion toward the terminal portion by a groove formed on one main surface of the terminal portion of the semiconductor layer. The semiconductor device disclosed in the present specification further includes a first main electrode in contact with the one main surface of the element portion of the semiconductor layer and a second main electrode in contact with the other main surface of the semiconductor layer. be able to. The semiconductor layer can have a first conductive type drift region, a second conductive type body region provided on the drift region, and a second conductive type electric field relaxation region. The groove is deeper than the pn junction surface of the drift region and the body region. Further, the electric field relaxation region is arranged so as to extend from a position near the end of the pn junction surface of the drift region and the body region and in contact with a part of the inclined surface to a position deeper than the pn junction surface. ing. Here, the type of the semiconductor device is not particularly limited, and examples thereof include a MOSFET (Metal Oxside Semiconductor Field Effect Transistor), an IGBT (Insulated Gate Bipolar Transistor), and a diode.

In the semiconductor device, an electric field relaxation region is provided near the end of the pn junction surface between the drift region and the body region. Therefore, in the vicinity of the end portion of the pn junction surface, the depletion layer spreads on the drift region side, the electric field concentration in this portion is relaxed, and the withstand voltage is improved. Further, the electric field relaxation region is provided so as to be in contact with a part of the inclined surface, and is not provided so as to be in contact with the entire surface of the inclined surface. Therefore, the damage for forming the electric field relaxation region is limited to a part of the inclined surface, so that the leakage current can be suppressed.

In the semiconductor device, the drift region may have a first drift region and a second drift region. The first drift region is provided in the element portion. The second drift region is provided in at least a part of the terminal portion and is in contact with the electric field relaxation region. The impurity concentration in the second drift region is lower than the impurity concentration in the first drift region.

In the semiconductor device, in the vicinity of the end of the pn junction surface between the drift region and the body region, the depletion layer further spreads toward the drift region side, the electric field concentration in this portion is further relaxed, and the withstand voltage is further improved. ..

The cross-sectional view of the main part of the semiconductor device is schematically shown. A cross-sectional view of a main part in one step of manufacturing the semiconductor device shown in FIG. 1 is schematically shown. A cross-sectional view of a main part in one step of manufacturing the semiconductor device shown in FIG. 1 is schematically shown. A cross-sectional view of a main part in one step of manufacturing the semiconductor device shown in FIG. 1 is schematically shown. A cross-sectional view of a main part in one step of manufacturing the semiconductor device shown in FIG. 1 is schematically shown. The cross-sectional view of the main part of the semiconductor device of the modified example is schematically shown. The cross-sectional view of the main part of the semiconductor device of another modification is schematically shown. The cross-sectional view of the main part of the semiconductor device of another modification is schematically shown. The cross-sectional view of the main part in one step of manufacturing the semiconductor device shown in FIG. 8 is schematically shown. The cross-sectional view of the main part in one step of manufacturing the semiconductor device shown in FIG. 8 is schematically shown. The cross-sectional view of the main part in one step of manufacturing the semiconductor device shown in FIG. 8 is schematically shown. The cross-sectional view of the main part in one step of manufacturing the semiconductor device shown in FIG. 8 is schematically shown. The cross-sectional view of the main part in one step of manufacturing the semiconductor device shown in FIG. 8 is schematically shown. The cross-sectional view of the main part in one step of manufacturing the semiconductor device shown in FIG. 8 is schematically shown. The cross-sectional view of the main part in one step of manufacturing the semiconductor device shown in FIG. 8 is schematically shown.

Hereinafter, a type of semiconductor device called a vertical MOSFET will be illustrated, and the technology disclosed in the present specification will be described. However, the techniques disclosed herein are not only useful for vertical MOSFETs, but also for other types of semiconductor devices.

FIG. 1 schematically shows a cross-sectional view of a main part of the semiconductor device 1. As shown in FIG. 1, the semiconductor device 1 includes a nitride semiconductor layer 10 partitioned by an element portion 10A and a terminal portion 10B. The element portion 10A is a region in which the element structure is formed, and is arranged in the central portion of the nitride semiconductor layer 10. The terminal portion 10B is a region provided so as to surround the element portion 10A, and is arranged on the outer peripheral portion of the nitride semiconductor layer 10.

A groove 100 is formed on the surface of the terminal portion 10B of the nitride semiconductor layer 10, and an inclined surface 102 is formed from the outer peripheral end of the element portion 10A toward the terminal portion 10B. The inclination angle θ of the inclined surface 102 (an acute angle formed by the inclined surface 102 of the groove 100 and the bottom surface) is 45 ° or less. In this example, the inclination angle θ of the inclined surface 102 is 10 °.

Further, the semiconductor device 1 further includes a drain electrode 22 in contact with the back surface of the nitride semiconductor layer 10, a source electrode 24 in contact with a part of the surface of the element portion 10A of the nitride semiconductor layer 10, and a surface of the element portion 10A of the nitride semiconductor layer 10. It is provided with a planar type insulating gate 30 provided on a part of the above. The source electrode 24 extends from the outer peripheral end of the element portion 10A beyond the inclined surface 102 to the terminal portion 10B and faces the surface of the nitride semiconductor layer 10 via an interlayer insulating film. The source electrode 24 provided in a part of the terminal portion 10B can function as a field plate electrode.

The nitride semiconductor layer 10 is, for example, gallium nitride (GaN). The nitride semiconductor layer 10 includes an n ⁺ type drain region 11, an n-type drift region 12, a p-type body region 13, a p ⁺ type body contact region 14, an n ⁺ type source region 15, and a p-type electric field. It has a relaxation region 16. The drain region 11, the drift region 12, the body region 13, and the source region 15 are arranged in this order along the thickness direction of the nitride semiconductor layer 10. If necessary, other semiconductor regions may intervene between these semiconductor regions.

The drain region 11 is arranged on the back layer portion of the nitride semiconductor layer 10, and is provided at a position exposed on the entire back surface of the nitride semiconductor layer 10. The drain region 11 is provided in both the element portion 10A and the terminal portion 10B. The drain region 11 is a GaN substrate, and is also a base substrate for epitaxially growing the drift region 12. The drain region 11 may be a silicon substrate or a silicon carbide substrate, for example, instead of the GaN substrate, as long as the drift region 12 is made of a material having a composition capable of crystal growth. The drain region 11 is in ohmic contact with the drain electrode 22.

The drift region 12 is provided on the surface of the drain region 11 and is arranged on the surface layer portion of the nitride semiconductor layer 10. The drift region 12 is provided in both the element portion 10A and the terminal portion 10B. A part of the drift region 12 is provided at a position where it penetrates the body region 13 and is exposed on the surface of the nitride semiconductor layer 10. A part of this drift region 12 is referred to as a JFET region 12J. The drift region 12 is formed by crystal growth from the surface of the drain region 11 by utilizing an epitaxial growth technique.

The body region 13 is provided on the surface of the drift region 12, and is arranged on the surface layer portion of the nitride semiconductor layer 10. The body region 13 is provided in the element portion 10A and also in a part of the terminal portion 10B. The body region 13 is provided between the drift region 12 and the source region 15 and separates the drift region 12 and the source region 15. The pn junction surface between the body region 13 and the drift region 12 is exposed on the inclined surface 102. The body region 13 is formed by crystal growth from the surface of the drift region 12 by utilizing an epitaxial growth technique.

The body contact region 14 is provided on the surface of the body region 13, and is provided at a position exposed on the surface of the nitride semiconductor layer 10. The body contact region 14 is provided in the element portion 10A. The body contact region 14 is formed on a part of the surface of the nitride semiconductor layer 10 by utilizing an ion implantation technique. The body contact region 14 is in ohmic contact with the source electrode 24.

The source region 15 is provided on the surface of the body region 13 and is provided at a position exposed on the surface of the nitride semiconductor layer 10. The source region 15 is provided in the element unit 10A. The source region 15 is formed on a part of the surface of the nitride semiconductor layer 10 by utilizing an ion implantation technique. The source region 15 is in ohmic contact with the source electrode 24.

The electric field relaxation region 16 is provided at a position where the pn junction surface of the drift region 12 and the body region 13 is exposed on the inclined surface 102, that is, in the vicinity of the end portion of the pn junction surface so as to include the end portion of the pn junction surface. .. Further, the electric field relaxation region 16 is provided so as to be in contact with a part of the inclined surface 102, and is not provided so as to be in contact with the entire surface of the inclined surface 102. Further, the electric field relaxation region 16 extends downward from a position in contact with the inclined surface 102, and is provided so as to extend to a position deeper than the pn junction surface of the drift region 12 and the body region 13. In this example, the electric field relaxation region 16 is further extended to a position deeper than the bottom surface of the groove 100. The p-type impurity concentration in the electric field relaxation region 16 is lower than the p-type impurity concentration in the body region 13.

The insulating gate 30 is configured as a planar type insulating gate, and is provided on the surface of the nitride semiconductor layer 10. The insulating gate 30 has a gate electrode 32 and a gate insulating film 34. The gate electrode 32 faces the JFET region 12J via the gate insulating film 34, and also faces the body region 13 that separates the JFET region 12J and the source region 15 via the gate insulating film 34. A channel of the inversion layer is formed in the body region 13 that separates the JFET region 12J and the source region 15.

Next, the operation of the semiconductor device 1 will be described. When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and a voltage that is more positive than the source electrode 24 is applied to the gate electrode 32 of the insulated gate 30, the semiconductor device 1 is turned on. At this time, in the semiconductor device 1, a channel is formed in the body region 13 located between the JFET region 12J and the source region 15, and electrons are injected from the source region 15 toward the JFET region 12J through the channel. The electrons injected into the JFET region 12J flow in the drift region 12 in the thickness direction. As a result, the drain electrode 22 and the source electrode 24 become conductive.

When a positive voltage is applied to the drain electrode 22, the source electrode 24 is grounded, and the gate electrode 32 of the insulated gate 30 is grounded, the semiconductor device 1 is turned off. At this time, in the semiconductor device 1, the depletion layer spreads from the pn junction surface of the drift region 12 and the body region 13, and the potential difference between the drain electrode 22 and the source electrode 24 can be maintained.

Here, consider the case where the electric field relaxation region 16 is not provided. The thickness of the body region 13 decreases from the element portion 10A side toward the terminal portion 10B side along the inclined surface 102. Therefore, the thickness of the body region 13 is thin in the vicinity of the end of the pn junction surface between the drift region 12 and the body region 13. In particular, the smaller the inclination angle θ of the inclined surface 102, the thinner the thickness of the body region 13. Therefore, in the vicinity of the end of the pn junction surface, the spread of the depletion layer is suppressed and the electric field is concentrated.

In the semiconductor device 1, an electric field relaxation region 16 is provided corresponding to the vicinity of the end of the pn junction surface where the electric field is concentrated. Therefore, in the vicinity of the end of the pn junction surface, the depletion layer spreads on the drift region 12 side, the electric field concentration in this portion is relaxed, and the withstand voltage is improved. Further, the electric field relaxation region 16 is in contact with the body region 13, and the potential is not floating. Therefore, when the semiconductor device 1 is turned off, the depletion layer can be quickly expanded.

It is desirable that the depletion layer spreads in the vicinity of the end of the body region 13 in the depth direction. Therefore, it is desirable that the electric field relaxation region 16 is formed deeply. In this example, the electric field relaxation region 16 is formed deeper than the bottom surface of the groove 100. As a result, the electric field near the end of the body region 13 can be effectively relaxed.

Further, if the concentration of p-type impurities in the electric field relaxation region 16 is high, the effect of relaxing the electric field is reduced. In this example, the p-type impurity concentration in the electric field relaxation region 16 is lower than the p-type impurity concentration in the body region 13. As a result, the electric field near the end of the body region 13 can be effectively relaxed.

Further, in the semiconductor device 1, the electric field relaxation region 16 is provided only on a part of the inclined surface 102. As will be described later, the electric field relaxation region 16 is formed by utilizing an ion implantation technique. Therefore, if the electric field relaxation region 16 is formed on the entire surface of the inclined surface 102, damage during ion implantation is formed on the entire surface of the inclined surface 102. In this case, there is a concern that a leak current may flow between the drift region 12 and the source region 15 via damage. On the other hand, in the semiconductor device 1, since the electric field relaxation region 16 is provided only in a part of the inclined surface 102, such a leakage current can be suppressed.

Next, a method of manufacturing the electric field relaxation region 16 of the semiconductor device 1 shown in FIG. 1 will be described with reference to FIGS. 2 to 5. In the manufacturing method of the semiconductor device 1, conventionally known steps can be adopted for steps other than the manufacturing step of the electric field relaxation region 16. Therefore, in the following, only the method of manufacturing the electric field relaxation region 16 of the semiconductor device 1 will be described, and the description of other steps will be omitted.

First, as shown in FIG. 2, a nitride semiconductor layer 10 in which a drain region 11, a drift region 12, and a body region 13 are laminated is prepared. The drift region 12 and the body region 13 are formed by crystal growth from the surface of the drain region 11 by utilizing an epitaxial growth technique. In this example, the body contact region 14 and the source region 15 are not formed, but they may be formed in the previous step if necessary.

Next, as shown in FIG. 3, using a dry etching technique, the depth of penetrating the body region 13 from the surface of the terminal portion 10B of the nitride semiconductor layer 10 and penetrating a part of the drift region 12 is determined. The groove 100 to have is formed. This dry etching step is carried out so that the inclination angle θ of the inclined surface 102 of the groove 100 is 45 ° or less. This dry etching step is carried out so that the inclination angle θ of the inclined surface 102 of the groove 100 is 40 ° or less, 35 ° or less, 30 ° or less, 25 ° or less, 20 ° or less, or 15 ° or less. You may.

Next, as shown in FIG. 4, a resist film 52 is formed on the surface of the nitride semiconductor layer 10 by using a photolithography technique. The resist film 52 has a pattern in which a part of the inclined surface 102, particularly a part of the inclined surface 102 in which the end portion of the pn junction surface of the drift region 12 and the body region 13 is exposed is exposed.

Next, as shown in FIG. 5, a p-type impurity (magnesium in this example) is implanted toward the surface of the nitride semiconductor layer 10 exposed from the opening of the resist film 52 by using an ion implantation technique. , The electric field relaxation region 16 is formed.

As described above, according to this manufacturing method, the electric field relaxation region 16 can be selectively formed in the vicinity of the end portion of the pn junction surface which is a part of the inclined surface 102.

FIG. 6 is an example of a modification of the semiconductor device 1. In this example, the electric field relaxation region 16 is provided on the element portion 10A side of the end portion of the pn junction surface. Reference numeral 17 indicates an end portion of the pn junction surface, that is, a position where the pn junction surface is exposed on the inclined surface 102. The electric field relaxation region 16 is arranged in a range of 0.7 μm or less in the plane direction of the nitride semiconductor layer 10 with reference to the end portion 17 of the pn junction surface. If the electric field relaxation region 16 is provided in such a positional relationship, the electric field near the end of the pn junction surface is relaxed and the withstand voltage is improved.

FIG. 7 is another example of a modification of the semiconductor device 1. In this example, the electric field relaxation region 16 is provided on the terminal portion 10B side of the end portion of the pn junction surface. Even in this example, the electric field relaxation region 16 is arranged in a range of 1.2 μm or less in the plane direction of the nitride semiconductor layer 10 when the end 17 of the pn junction surface is used as a reference. If the electric field relaxation region 16 is provided in such a positional relationship, the electric field near the end of the pn junction surface is relaxed and the withstand voltage is improved.

FIG. 8 is another example of a modification of the semiconductor device 1. In this example, the drift region 12 has a first drift region 12a and a second drift region 12b. The first drift region 12a is provided in the element portion 10A, and the second drift region 12b is provided in the terminal portion 10B. The second drift region 12b is in contact with the electric field relaxation region 16 and separates the electric field relaxation region 16 from the first drift region 12a. The impurity concentration in the second drift region 12b is lower than the impurity concentration in the first drift region 12a. In the semiconductor device 1, the depletion layer further spreads toward the second drift region 12b in the vicinity of the end of the pn junction surface, the electric field concentration in this portion is further relaxed, and the withstand voltage is further improved.

The second drift region 12b may be provided at a position in contact with the electric field relaxation region 16, and may not be provided on the entire end portion 10B. For example, the boundary between the first drift region 12a and the second drift region 12b may be closer to the terminal portion 10B than the boundary between the element portion 10A and the terminal portion 10B. Further, the second drift region 12b may be provided only on the surface side of the terminal portion 10B.

Next, a method of manufacturing the drift region 12, the body region 13, and the electric field relaxation region 16 of the semiconductor device 1 shown in FIG. 8 will be described with reference to FIGS. 9 to 15. In the manufacturing method of the semiconductor device 1, conventionally known steps can be adopted for steps other than the manufacturing steps in these regions. Therefore, in the following, only the manufacturing method of the drift region 12, the body region 13, and the electric field relaxation region 16 of the semiconductor device 1 will be described, and the description of other steps will be omitted.

First, as shown in FIG. 9, a nitride semiconductor layer in which the drain region 11 and the n-type semiconductor region 112 are laminated is prepared. The n-type semiconductor region 112 is formed by crystal growth from the surface of the drain region 11 using an epitaxial growth technique.

Next, as shown in FIG. 10, a resist film 54 is formed on the surface of the nitride semiconductor layer by using a photolithography technique. The resist film 54 has a pattern in which the surface of the nitride semiconductor layer at the position corresponding to the element portion 10A is covered and the surface of the nitride semiconductor layer at the position corresponding to the terminal portion 10B is exposed.

Next, as shown in FIG. 11, the n-type semiconductor region 112 of the terminal portion 10B of the nitride semiconductor layer 10 is removed by using a dry etching technique. A part of the n-type semiconductor region 112 may remain on the surface of the drain region 11.

Next, as shown in FIG. 12, the n-type epi layer 114 is crystal-grown from the surfaces of the drain region 11 and the n-type semiconductor region 112 by using an epitaxial growth technique. The impurity concentration of the n-type epi layer 114 is lower than the n-type impurity concentration of the n-type semiconductor region 112.

Next, as shown in FIG. 13, a chemical mechanical polishing technique is used to etch back the n-type epi layer 114 until the surface of the n-type semiconductor region 112 is exposed. As a result, the first drift region 12a is formed in the element portion 10A, and the second drift region 12b is formed in the terminal portion 10B.

Next, as shown in FIG. 14, the body region 13 is crystal-grown from the surface of the drift region 12 by using an epitaxial growth technique. As a result, the nitride semiconductor layer 10 in which the drain region 11, the drift region 12, and the body region 13 are laminated is formed.

Next, as shown in FIG. 15, a depth that penetrates a part of the second drift region 12b from the surface of the terminal portion 10B of the nitride semiconductor layer 10 through the body region 13 by using a dry etching technique. A groove 100 having an etching is formed. This dry etching step is carried out so that the inclination angle θ of the inclined surface 102 of the groove 100 is 45 ° or less. This dry etching step is carried out so that the inclination angle θ of the inclined surface 102 of the groove 100 is 40 ° or less, 35 ° or less, 30 ° or less, 25 ° or less, 20 ° or less, or 15 ° or less. You may.

As for the subsequent steps, the electric field relaxation region 16 can be formed by carrying out the same steps as those in FIGS. 4 and 5.

Although specific examples of the disclosed techniques have been described in detail in the present specification, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. In addition, the technical elements described in the present specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

1: Semiconductor device 10: Nitride semiconductor layer 10A: Element portion 10B: Termination portion 11: Drain region 12: Drift region 13: Body region 14: Body contact region 15: Source region 16: Electric field relaxation region 22: Drain electrode 24: Source electrode 30: Insulated gate 32: Gate electrode 34: Gate insulating film 100: Groove 102: Inclined surface

Claims (2)

A semiconductor layer having an element portion on which an element structure is formed and a terminal portion surrounding the element portion, and the element portion is formed by a groove formed on one main surface of the terminal portion of the semiconductor layer. A semiconductor layer having an inclined surface formed from the outer peripheral end toward the end portion,
A first main electrode in contact with the one main surface of the element portion of the semiconductor layer,
A second main electrode in contact with the other main surface of the semiconductor layer is provided.
The semiconductor layer is
The first conductive type drift region and
The second conductive type body region provided on the drift region and
It has a second conductive type electric field relaxation region and
The groove is deeper than the pn junction surface of the drift region and the body region.
The electric field relaxation region is arranged so as to extend from a position near the end of the pn junction surface of the drift region and the body region and in contact with a part of the inclined surface to a position deeper than the pn junction surface. , Semiconductor device. The drift region has a first drift region and a second drift region.
The first drift region is provided in the element portion, and is provided in the element portion.
The second drift region is provided in at least a part of the terminal portion and is in contact with the electric field relaxation region.
The semiconductor device according to claim 1, wherein the impurity concentration in the second drift region is lower than the impurity concentration in the first drift region.

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