JP2010283366A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device with a lateral field-effect transistor, which has uniform characteristics, even if increasing an element area. <P>SOLUTION: The semiconductor device includes: a first conductivity type semiconductor layer 11; a second conductivity type deep well 12; a first conductivity type well 13; a second conductivity type source layer 15 formed within the well; a second conductivity type drain layer 17; a second conductivity type contact layer 19 which is formed in an upper layer portion of the deep well and is connected to the rain layer; a gate electrode 21 provided in an area right above a region between the source and the drain; and a second conductivity type drift layer 18. While a reverse bias voltage is applied between the source layer and the drain layer, punch-through does not occur between the source layer and the drain layer and a first depletion layer between the drain layer and the well and a second depletion layer between the well and the deep well are connected with a junction breakdown voltage between the well and the drain layer or lower. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a lateral field effect transistor.

  When an N-type LDMOS (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) is used as a high-side transistor of a DC-DC converter, a deep N well ( A technique for forming an N-type LDMOS in the DNW by forming a DNW), forming a P-well in an upper layer portion of the DNW, and forming an N-type source layer and a drain layer in the P-well is known. (For example, refer to Patent Document 1). By doing so, it becomes possible to surround the entire LDMOS with DNW and to electrically isolate the LDMOS from the semiconductor substrate.

However, in general, a buried N ⁺ layer is formed instead of the DNW, and a well formation region is formed by an epitaxial growth method. On the other hand, when the DNW is formed by the implantation method and the diffusion method as described above, it is formed by the buried N ⁺ layer. As a result, the impurity concentration is lowered and the resistivity is increased.

  Therefore, when the area of the N-type LDMOS is increased by alternately arranging the source layer and the drain layer or the like, the DNW has a high resistance. There is a problem that it is difficult to obtain uniform characteristics.

JP 2006-245482 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device including a lateral field effect transistor, which has uniform characteristics in the element even when the element area is increased.

  According to one aspect of the present invention, a first conductivity type semiconductor layer, a second conductivity type deep well formed in a part of the upper layer portion of the semiconductor layer, and a part of the upper layer portion of the deep well are formed. A first conductivity type well formed, a second conductivity type source layer formed in the well, and the same potential as the deep well, and formed in the well and separated from the source layer. A second conductivity type drain layer, a second conductivity type contact layer formed outside the well in the upper layer portion of the deep well and connected to the drain layer, and the source layer and the drain layer. A gate electrode provided immediately above the region between the gate electrode, a gate insulating film provided between the well and the gate electrode, and the drain layer in the upper layer portion of the well and the region immediately below the gate electrode. And a second conductivity type drift layer having an effective impurity dose lower than the effective impurity dose of the drain layer, and a reverse bias voltage between the source layer and the drain layer. Is applied, a first depletion layer is formed between the drain layer and the well, a second depletion layer is formed between the well and the deep well, and the source layer and the well There is provided a semiconductor device characterized in that punch-through does not occur between the drain layer and the first depletion layer and the second depletion layer are connected below the junction breakdown voltage between the well and the drain layer. The

  According to the present invention, it is possible to realize a semiconductor device including a lateral field effect transistor, which has uniform characteristics in the element even when the element area is increased.

1 is a cross-sectional view illustrating a semiconductor device according to a first embodiment of the invention. It is sectional drawing which expands and shows the area | region R shown in FIG. 6 is a cross-sectional view illustrating the operation of the semiconductor device according to the first embodiment; FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an example of a first embodiment; FIGS. 4A and 4B are graphs illustrating an impurity concentration profile in a semiconductor device, with the position on the horizontal axis and the impurity concentration on the vertical axis, and FIG. The profile along the line 'is shown, and (b) shows the profile along the line BB' shown in FIG. (A) thru | or (c) is a figure which illustrates the simulation result of the electric field distribution in the semiconductor device based on the Example of 1st Embodiment, (a) shows the case where SD voltage is 0V, b) shows a case where the SD voltage is a normal drive voltage, and (c) shows a case where a high voltage near the device withstand voltage is applied. 6 is a cross-sectional view illustrating a semiconductor device according to a first comparative example of the first embodiment; FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a second comparative example of the first embodiment; FIG. FIG. 5 is a cross-sectional view illustrating a semiconductor device according to a second embodiment of the invention, and shows an N-type LDMOS different from the N-type LDMOS shown in FIG. FIG. 10 is a cross-sectional view illustrating a semiconductor device according to a modification of the second embodiment, and shows an N-type LDMOS serving as a low-side transistor. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a third embodiment of the invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to a fourth embodiment of the invention. 10 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to a fourth embodiment; FIG. FIG. 7 is a cross-sectional view illustrating a semiconductor device according to a fifth embodiment of the invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, a first embodiment of the present invention will be described.
FIG. 1 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
FIG. 2 is an enlarged cross-sectional view of the region R shown in FIG.

As shown in FIGS. 1 and 2, in the semiconductor device 1 according to the present embodiment, a P-type substrate 11 having a P-type conductivity is provided. The P-type substrate 11 may be formed of a uniform semiconductor layer as a whole, or only the upper layer portion may be a P-type semiconductor layer. In FIGS. 1 and 2, the P-type substrate 11 is indicated as “P-Sub”. A deep N well (DNW) 12 whose conductivity type is N ⁺ type is formed in a part of the upper layer portion of the P type substrate 11. A P well (PW) 13 is selectively formed in a part of the upper layer portion of the DNW 12. Both the DNW 12 and the P well 13 are formed by impurity implantation and diffusion. The effective dose in the P well 13 is, for example, 1 × 10 ¹³ cm ⁻² or less. The “effective dose amount” refers to a dose amount of impurities that substantially contribute to conduction by removing the offset amount between the acceptor and the donor from the implanted dose amount.

  A channel implantation region 14 (first conductivity type region) having a conductivity type of P type is formed in a part of the upper layer portion of the P well 13. The effective impurity dose of the channel implant region 14 is higher than the effective impurity dose of the P well 13. For example, as shown in FIG. 1, channel implantation regions 14 are formed in two places in one P well 13, and the shape thereof is a stripe shape extending in a direction perpendicular to the paper surface of FIG.

As shown in FIGS. 1 and 2, a source layer 15 whose conductivity type is N ⁺ type is formed in a part of the upper layer portion of each channel implantation region 14. In addition, a contact layer 16 having a conductivity type of P ⁺ is formed in another part of the upper layer portion of the channel implant region 14. The source layer 15 and the contact layer 16 are connected to a common source electrode (not shown), and are in contact with each other, for example.

On the other hand, a drain layer 17 having a conductivity type of N ⁺ type is formed in the upper layer portion of the P well 13 and in a region separated from the channel implantation region 14. For example, as shown in FIG. 1, the drain layer 17 is disposed between the pair of channel implantation regions 14 and extends in a stripe shape along a direction perpendicular to the paper surface of FIG.

  Further, a drift layer 18 having an N conductivity type is formed in a part of the upper layer portion of the P well 13 and in a region on the source layer 15 side when viewed from the drain layer 17. In the example shown in FIG. 1, the drift layer 18 is in contact with the drain layer 17 but is not in contact with the channel implantation region 14, and the P well 13 is interposed between the drift layer 18 and the channel implantation region 14. is doing. The drift layer 18 may be in contact with the channel implantation region 14. The effective impurity dose of the drift layer 18 is lower than the effective impurity dose of the drain layer 17. On the other hand, an LDD (Lightly Doped Drain) region (not shown) is provided in a portion of the source layer 15 on the drain layer 17 side.

On the outer side of the P well 13 in the upper layer portion of the deep N well (DNW) 12, a contact layer 19 having an N ⁺ type conductivity is formed. The effective impurity concentration of the contact layer 19 is higher than the effective impurity concentration of the DNW 12. Further, assuming the high-side specification of the DC-DC converter, the contact layer 19 is connected to the drain layer 17 via a wiring. Further, a contact layer 20 for applying a predetermined potential to the P-type substrate 11 is formed outside the DNW 12 in the P-type substrate 11. The contact layer 20 has a P ⁺ conductivity type, and its effective acceptor concentration is higher than the effective acceptor concentration of the P-type substrate 11.

  Further, on the P-type substrate 11, directly above the region between the source layer 15 and the drain layer 17, more specifically, directly above the region between the source layer 15 and the drift layer 18. A gate electrode 21 is provided. The shape of the gate electrode 21 is also a stripe shape extending in the same direction as the source layer 15 and the drain layer 17. In the example shown in FIG. 1, the outer edge of the channel implant region 14 on the drift layer 18 side is located immediately below the gate electrode 21. As described above, when the drift layer 18 is brought into contact with the channel implantation region 14, the channel implantation region 14 may be formed in the entire region immediately below the gate electrode 21. Further, a gate insulating film 22 is provided between the P well 13 and the gate electrode 21.

  The P-type well 13, the channel implantation region 14, the source layer 15, the contact layer 16, the drain layer 17, the drift layer 18, the contact layer 19, the gate electrode 21 and the gate insulating film 22 constitute an N-type LDMOS 26. The N-type LDMOS 26 is surrounded by the DNW 12 and is electrically isolated from other regions in the P-type substrate 11.

Next, the operation of the semiconductor device according to this embodiment will be described.
FIG. 3 is a cross-sectional view illustrating the operation of the semiconductor device according to this embodiment.
As shown in FIG. 3, a potential lower than the threshold voltage of the N-type LDMOS 26 is applied to the gate electrode 21 to turn off the N-type LDMOS 26, a negative source potential is applied to the source layer 15, and a positive electrode is applied to the drain layer 17. The source potential is also applied to the channel implant region 14 and the P well 13 through the contact layer 16 when the drain potential is applied, that is, when the reverse bias voltage is applied. A drain potential is also applied to the end of the DNW 12 via the contact layer 19. Note that the above-mentioned “negative electrode” and “positive electrode” indicate a relative potential relationship, and the “negative electrode” is not necessarily a potential lower than the ground potential, and may be a ground potential (zero potential), for example.

In this way, the positive drain potential is applied to the N ⁺ -type drain layer 17 and the DNW 12, and the negative source potential is applied to the P well 13, whereby the interface between the drain layer 17 and the P well 13 is applied. Although the depletion layer extends vertically, the depletion layer (first depletion layer) extends mainly inside the P well 13 having a relatively low impurity concentration, that is, downward. On the other hand, although the depletion layer also extends vertically from the interface between DNW 12 and P well 13, a depletion layer (second depletion layer) mainly exists inside P well 13 having a relatively low impurity concentration, that is, upward. extend. The depletion layers come into contact with each other and are connected to each other, whereby the drain layer 17 and the DNW 12 are electrically connected through the P well 13. At this time, the drain layer 17 and the DNW 12 are at the same potential and no current flows. However, in this specification, this state is referred to as “punch-through between the drain layer 17 and the DNW 12 (“ vertical punch ”). It is also called “through”).

As a result, a drain potential is applied to a portion corresponding to the region immediately below the drain layer 17 in the DNW 12. As a means for generating punch-through between the drain layer 17 and the DNW 12, for example, there is a method of reducing the effective impurity concentration of the P well 13. As a result, the depletion layer easily extends in the P well 13 and vertical punch-through is likely to occur. For example, as described above, and an effective dose of the P well 13 1 × ¹⁰ 13 ^{cm -2} or less.

A source region of LDMOS26, i.e., in the region of the source layer 15 and its vicinity, the source layer 15 of the N ⁺ type for the source potential of the negative electrode is applied, the depletion from the interface between the source layer 15 and the channel implantation region 14 The layer does not extend, and the depletion layer extends vertically only from the interface between the DNW 12 and the P well 13, but the source layer 15 is formed by the P-type channel implant region 14 having an effective impurity concentration higher than the impurity concentration of the P well 13. The P-type region immediately below the source layer 15, that is, the P well 13 and the channel implantation region 14 are not completely depleted because they are surrounded. That is, the P well 13 is completely depleted in the drain region and is not depleted in the source region. On the other hand, the drift layer 18 is designed to be depleted when a reverse bias is applied by setting the impurity concentration appropriately in order to maintain the lateral breakdown voltage of the element. Due to these relationships, the end of the depletion layer in the P-well 13 often comes in the middle of the drift region 18. A curve shown in FIG. 3 schematically shows the equipotential surface in this state. Further, due to the above-described mechanism, a continuous depletion layer is not formed between the source layer 15 and the drain layer 17, and punch-through (hereinafter, also referred to as “lateral punch-through”) does not occur.

  On the other hand, as described above, the normal breakdown voltage of the LDMOS is that the drift region 18 is depleted and the source-drain voltage is appropriately shared in the depleted region to achieve a desired device breakdown voltage. This is the pressure resistance design. However, when a CMOS P-well and drain layer are used, the impurity concentration is often high, and a phenomenon occurs in which the device breakdown voltage is determined by the junction breakdown voltage of the P-well 13 and the drain layer 17 immediately below the drain layer 17. In this case, even if the drift region 18 is designed to have an appropriate impurity concentration and length, it becomes impossible to generate a breakdown voltage higher than the junction breakdown voltage between the P well 13 and the drain layer 17.

However, if punch-through occurs between the drain layer 17 and the DNW 12 below the junction breakdown voltage of the P well 13 and the drain layer 17, the element breakdown voltage is not affected by the junction breakdown voltage. Therefore, the element breakdown voltage can be determined by the design of the drift region 18.
One method is to reduce the concentration of the P-well 13 so that the junction breakdown voltage with the drain layer 17 is increased. However, this method requires a separate process from the existing CMOS P-well 13. This leads to an increase in processes and costs.
Therefore, in order to form a high breakdown voltage LDMOS while suppressing an increase in the number of processes as much as possible, the operation as in this embodiment is required.

  In the present embodiment, the vertical layer punch-through portion in the drift layer 18, the drain layer 17, and the P well 13 and the DNW 12 have the same potential, so that the equipotential surface E is in these regions. Curves along the outer edge of Thereby, the electric field concentration is relaxed between the drain layer 17 and the P well 13. As a result, the junction breakdown voltage between the drain layer 17 and the P well 13 is further improved.

Next, the effect of this embodiment will be described.
In the present embodiment, when a punch-through in the vertical direction occurs between the drain layer 17 and the DNW 12, a drain potential can be applied to a portion corresponding to the region immediately below the drain layer 17 in the DNW 12. As a result, even if the area of the DNW 12 is increased, the potential in the DNW 12 can be prevented from varying depending on the position, and the potential of the DNW 12 can be made uniform. Uniform characteristics can be obtained as a whole. For example, even if the current driving capability of the N-type LDMOS 26 is increased by arranging a large number of source layers 15 and drain layers 17 alternately, the DNW 12 includes not only the contact layer 19 but also the drain layer 17 through the depletion layer. However, since the drain potential can be applied, the potential can be made uniform over the entire DNW 12.

  In the present embodiment, as a method for generating only the vertical punch-through without generating the horizontal punch-through, the effective acceptor concentration of the P well 13 is kept low and the source layer 15 is surrounded. Although a method of providing a high concentration channel implantation region 14 that does not surround the drain layer 17 is adopted, the present invention is not limited to this. For example, the distance between the source layer 15 and the drain layer 17 may be increased without providing the channel implantation region 14. This also prevents horizontal punch-through when a predetermined drive voltage is applied between the source and drain. In other words, in the present embodiment, a voltage that does not cause punch-through between the source layer 15 and the drain layer 17 and causes punch-through between the drain layer 17 and the DNW 12 is applied to the source. Applied between the layer 15 and the drain layer 17, the N-type LDMOS 26 is driven.

  In the present embodiment, by providing the drift layer 18, the electric field concentration can be relaxed and the breakdown voltage between the drain layer 17 and the P well 13 can be improved. Thereby, vertical punch-through can be generated by a voltage lower than the withstand voltage.

  Furthermore, in the present embodiment, in order to generate punch-through in the vertical direction, no special structure is provided between the drain layer 17 and the DNW 12, so that the mask position for forming such a structure is not displaced. As a result, there is no problem that the characteristics of the N-type LDMOS 26 vary.

Hereinafter, examples and comparative examples of this embodiment will be described in order to more specifically show the effects of the above-described embodiment.
First, examples of the present embodiment will be described.
FIG. 4 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
FIGS. 5A and 5B are graphs illustrating an impurity concentration profile in a semiconductor device, where the horizontal axis represents the position in the element depth direction and the vertical axis represents the impurity concentration, and FIG. The profile along the AA 'line shown in FIG. 4 is shown, (b) shows the profile along the BB' line shown in FIG.
5A and 5B, the broken line indicates the acceptor concentration, the alternate long and short dash line indicates the donor concentration, and the solid line indicates the effective impurity concentration.

  As shown in FIG. 4 and FIGS. 5A and 5B, in the semiconductor device 31 according to the present embodiment, the acceptor is injected so as to overlap the DNW 12, and the P well 13 is formed. The effective amount of impurities in the subsequent P-well 13 is reduced. Further, in the region on the source layer 15 side, the acceptor is overlapped on the P-well 13 to form the channel implant region 14, so that the acceptor concentration is further reinforced and it is possible to counter defects such as latch-up. It becomes.

5A and 5B, in the semiconductor device 31, the effective impurity concentration of the P-type substrate 11 is about 3 × 10 ¹⁵ cm ⁻³ , and the DNW 12 and the P well 13 are effective. The peak value of the impurity concentration is about 5 × 10 ¹⁶ cm ⁻³ , the effective impurity concentration of the channel implantation region 14 is about 3 × 10 ¹⁷ cm ⁻³ , and the effective density of the source layer 15 and the drain layer 17 is The impurity concentration is about 2 × 10 ²⁰ cm ⁻³ .

Next, the operation of this embodiment will be described.
6A to 6C are diagrams illustrating the simulation results of the electric field distribution in the semiconductor device according to the present embodiment. FIG. 6A is a voltage between the source and the drain (hereinafter referred to as “SD voltage”). ) Shows a case where the voltage is 0 V, (b) shows a case where the SD voltage is a normal driving voltage, and (c) shows a case where the SD voltage is a high voltage near the device breakdown voltage.
Note that the regions shown in FIGS. 6A to 6C substantially correspond to the regions shown in FIG.

  As shown in FIG. 6A, when the SD voltage is 0V, the potential in the semiconductor device 31 is uniform. On the other hand, as shown in FIG. 6B, when the SD voltage is applied, vertical punch-through occurs between the drain layer 17 and the DNW 12 shown in FIG. The drain layer 17 is electrically connected to the DNW 12 through the depletion layer generated in step. As a result, an equipotential surface is formed so as to connect the drift layer 18, the drain layer 17, the depletion layer formation region of the P well 13 and the DNW 12. As shown in FIG. 6C, even if the SD voltage is increased to the vicinity of the breakdown voltage of the element, the density of the equipotential surface increases, but the shape of the equipotential surface does not change much. For this reason, a region where the equipotential surface is particularly dense does not appear, and a high breakdown voltage can be obtained. Further, since the length of the drift layer 18 can be set to the minimum necessary with respect to the target breakdown voltage, the on-resistance can be lowered.

  As described above, in the semiconductor device 31 according to this embodiment, when a driving voltage is applied between the source and the drain, vertical punch-through occurs, and this punch-through stably exists up to the vicinity of the limit of the element breakdown voltage. Thus, according to the present example, the effects described in the above-described embodiments can be stably obtained.

Next, a first comparative example of this embodiment will be described.
FIG. 7 is a cross-sectional view illustrating a semiconductor device according to this comparative example.
As shown in FIG. 7, the layer structure of the semiconductor device 101 according to this comparative example is the same as the layer structure of the semiconductor device 1 according to the above-described embodiment, but the P well 13 in the semiconductor device 101 is effective. The impurity concentration is higher than that in the semiconductor device 1. For this reason, when the N-type LDMOS 26 is turned off, no vertical punch-through occurs between the drain layer 17 and the DNW 12.

  In such a semiconductor device 101, the drain potential is applied to the DNW 12 only through the contact layer 19 formed at the end of the DNW 12. For this reason, the end portion D and the central portion C of the DNW 12 have different potentials. For this reason, the characteristics of the N-type LDMOS 26 vary depending on the position. This tendency becomes more prominent as the effective impurity concentration of the DNW 12 is lower and the resistivity is higher, and becomes more prominent as the width of the DNW 12 is larger.

  In the semiconductor device 101, the drain layer 17 and the DNW 12 are not connected by vertical punch-through, and therefore the equipotential surface E is formed along the surfaces of the drift layer 18 and the drain layer 17. For this reason, the electric field concentrates at the corner of the drift layer 18 and the breakdown voltage of this portion is reduced.

Next, a second comparative example of the present embodiment will be described.
FIG. 8 is a cross-sectional view illustrating a semiconductor device according to this comparative example.
As shown in FIG. 8, in the semiconductor device 102 according to this comparative example, the P well 13 is not formed in the entire region of the drain layer 17 and the region immediately below the portion of the drift layer 18 on the drain layer 17 side. Extends upward. Thereby, the DNW 12 is in contact with the entire drain layer 17 and the portion of the drift layer 18 on the drain layer 17 side.

  In the semiconductor device 102 according to this comparative example, since the drain layer 17 is in contact with the DNW 12, this portion becomes conductive, and a drain potential can be applied to the DNW 12 through the drain layer 17. Thereby, the electric potential of DNW12 can be made uniform. Further, since an equipotential surface curved so as to bypass the P well 13 from the drain layer 17 to the DNW 12 is formed, the electric field concentration is relaxed and the breakdown voltage is improved.

  However, since the donor included in the drift layer 18 is canceled by the acceptor included in the P well 13, the effective dose amount of the drift layer 18 depends on the length of the overlapping portion between the drift layer 18 and the P well 13. . In this comparative example, since the interface between the extended portion of the DNW 12 and the P well 13 is located immediately below the drift layer 18, if the mask for forming the P well 13 is displaced, the length of the overlapping portion Fluctuates, and the effective dose of the drift layer 18 fluctuates. As a result, device characteristics such as breakdown voltage and on-resistance vary.

  For this reason, when designing the semiconductor device 102, it is necessary to allow for a mask position shift. In other words, it is necessary to set a high specification in anticipation of variations in element characteristics, or to design a large element size in order to provide a margin at the mask alignment position. As a result, the N-type LDMOS 26 becomes over-spec or the area of the element increases and the on-resistance increases.

  On the other hand, according to the example of this embodiment, since the drain layer 17 is electrically connected to the DNW 12 by punch-through, it is not necessary to cut the P well 13 immediately below the drift layer 18. There is no variation due to mask misalignment during formation. For this reason, when designing a semiconductor device, it is not necessary to overspecify or increase the size of the element.

Next, a second embodiment of the present invention will be described.
FIG. 9 is a cross-sectional view illustrating the semiconductor device according to this embodiment, and shows an N-type LDMOS different from the N-type LDMOS shown in FIG.
In the semiconductor device 2 according to the present embodiment, the N-type LDMOS 26 shown in FIG. 1 is provided in a partial region of the P-type substrate 11, and the other partial region of the P-type substrate 11 is shown in FIG. An N-type LDMOS 46 is provided. The N-type LDMOS 26 constitutes a high-side transistor of the DC-DC converter, and the N-type LDMOS 46 constitutes a low-side transistor of the DC-DC converter.

  As shown in FIG. 9, in the N-type LDMOS 46, the contact layer 19 (see FIG. 1) for applying the drain potential to the DNW 12 is not provided. The DNW 12 shown in FIG. 9 is continuous with the DNW 12 shown in FIG. 1, and the drain potential of the N-type LDMOS 26 is applied to the DNW 12. The other configuration of the N-type LDMOS 46 is the same as that of the N-type LDMOS 26 shown in FIG. That is, the P well 13, the channel implantation region 14, the source layer 15, the contact layer 16, the drain layer 17, and the drift layer 18 shown in FIG. 9 are separate from these components shown in FIG. 1. These components are formed at the same time, and the depth and the dose are the same.

Next, the operation of this embodiment will be described.
For the N-type LDMOS 26 that is a high-side transistor of the DC-DC converter, an input potential of the DC-DC converter, for example, a positive potential of + 5V is applied to the drain layer 17 as a drain potential. At this time, an input potential of +5 V is also applied to the DNW 12 through the contact layer 19. On the other hand, for the N-type LDMOS 46 that is a low-side transistor of the DC-DC converter, a reference potential of the DC-DC converter, for example, a ground potential of 0 V, is applied to the source layer 15 as a source potential. The source layer 15 of the N-type LDMOS 26 is connected to the drain layer 17 of the N-type LDMOS 46.

  When the N-type LDMOS 26 that is a high-side transistor is in an OFF state and the N-type LDMOS 46 that is a low-side transistor is in an ON state, an operation similar to that in the first embodiment is performed in the N-type LDMOS 26. Vertical punch-through occurs, and a drain potential (input potential) is applied to the DNW 12. At this time, in the N-type LDMOS 46, since the drain potential is almost 0 V, vertical punch-through does not occur.

  On the other hand, when the N-type LDMOS 26 that is a high-side transistor is in an on state and the N-type LDMOS 46 that is a low-side transistor is in an off state, the source potential of the N-type LDMOS 26 is approximately + 5V and the SD voltage is approximately 0V. Therefore, the state shown in FIG. 6A is obtained, and vertical punch-through does not occur. In the N-type LDMOS 46, the drain potential is approximately + 5V and the source potential is 0V. However, the DNW 12 has a drain potential only through the contact layer 19 (see FIG. 1) formed in the formation region of the N-type LDMOS 26. Is applied, the potential of the region where the N-type LDMOS 46 is formed in the DNW 12 is considerably lowered from + 5V. For this reason, vertical punch-through does not occur.

  According to the present embodiment, a high-side transistor and a low-side transistor can be formed on a single P-type substrate 11 using a deep N well (DNW) 12 and a P well 13 that have common specifications. . Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, a modification of the second embodiment will be described.
FIG. 10 is a cross-sectional view illustrating a semiconductor device according to this variation, and shows an N-type LDMOS serving as a low-side transistor.

  As shown in FIG. 10, in the semiconductor device 2a according to this modification, in the N-type LDMOS 46 constituting the low-side transistor, a deep region is formed directly below the entire drain layer 17 and the portion of the drift layer 18 on the drain layer 17 side. An N well (DNW) 52 is formed, and a deep P well (DPW) 53 is formed immediately below the N well. The DPW 53 is in contact with the DNW 12. Configurations, operations, and effects other than those described above in the present modification are the same as those in the second embodiment described above.

Next, a third embodiment of the present invention will be described.
FIG. 11 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
As shown in FIG. 11, in the semiconductor device 3 according to the present embodiment, in addition to the configuration of the semiconductor device 1 according to the first embodiment (see FIGS. 1 and 2), a channel in the P well 13 is formed. A P well 63 is additionally formed in a part of the region immediately below the implantation region 14 so as to be in contact with the channel implantation region 14. The conductivity type of the P well 63 is P type, and the effective impurity concentration of the P well 63 is higher than the effective impurity concentration of the P well 13.

  According to the present embodiment, by forming the P well 63 in the P well 13 in addition to the P well 13, the effective acceptor concentration in the source side region of the P well 13 is reinforced. Thereby, defects such as latch-up can be avoided more reliably. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

Next, a fourth embodiment of the present invention will be described.
FIG. 12 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
As shown in FIG. 12, in the semiconductor device 4 according to the present embodiment, the DNW 12 is divided into a drain side region 12d and a source side region 12s, and the effective impurity concentration of the drain side region 12d is It is higher than the effective impurity concentration of the source-side region 12s. The P well 13 is also divided into a drain side region 13d and a source side region 13s, and the effective impurity concentration of the drain side region 13d is lower than the effective impurity concentration of the source side region 13s. . For this reason, the effective impurity concentration of the portion corresponding to the region immediately below the drain layer 17 in the P well 13 is lower than the effective impurity concentration of the portion corresponding to the region immediately below the source layer 15 in the P well 13. In the present embodiment, the configuration other than the above is the same as that of the semiconductor device 1 according to the first embodiment described above (see FIGS. 1 and 2).

Next, a method for manufacturing the semiconductor device according to the present embodiment will be described.
FIG. 13 is a process cross-sectional view illustrating a method for manufacturing a semiconductor device according to this embodiment.
As shown in FIG. 13, a P-type substrate 11 made of, for example, single crystal silicon (Si) is prepared, and a slit-like resist block 71 is formed only on a source-side region on the upper surface of the P-type substrate 11. Next, using this resist block 71 as a mask, a donor, for example, phosphorus (P) is ion-implanted into the upper layer portion of the P-type substrate 11. Thereby, the dose amount of the donor implanted into the source side region becomes smaller than the dose amount of the donor implanted into the drain side region.

  Thereafter, the resist block 71 is removed and heat treatment is performed to diffuse the implanted donor, and the donor concentration is made uniform in each of the source side region and the drain side region. At this time, since the arrangement period of the resist blocks 71 is made sufficiently small, the arrangement period of the resist blocks 71 is not reflected in the donor concentration distribution in the region 12s after the thermal diffusion process. As a result, the DNW 12 is formed in the upper layer portion of the P-type substrate 11, but the donor concentration in the source side region 12s of the DNW 12 is lower than the donor concentration in the drain side region 12d.

  Next, an acceptor is ion-implanted into the upper layer portion of the DNW 12 to form a P well 13. At this time, the dose amount of the acceptor is the same in the source-side region and the drain-side region, but in the drain-side region, the injected acceptor is canceled by the donor included in the DNW 12 than in the source-side region. As a result, the effective impurity concentration of the drain-side region 13d in the P-well 13 is lower than the effective impurity concentration of the source-side region 13s.

  Thereafter, as shown in FIG. 12, each region and each layer are formed by a normal method, and the gate insulating film 22, the gate electrode 21 and the like are formed, whereby the semiconductor device 4 according to this embodiment is manufactured.

  In this embodiment, since the effective impurity concentration in the drain-side region 13d of the P well 13 is lower than the effective impurity concentration in the source-side region 13s, the drain layer 17 and the drain-side region 12d of the DNW 12 are used. In between, vertical punch-through is likely to occur. As a result, it is possible to widen the range of thickness, impurity concentration, and the like allowed for the P well 13. In the semiconductor device 4, when the N-type LDMOS 26 is mixedly mounted with another CMOS, the thickness and impurity concentration of the P well are often determined by the CMOS design, so that the degree of freedom in designing the P well is improved. As a result, the degree of freedom in designing the entire semiconductor device is improved. Operations and effects other than those described above in the present embodiment are the same as those in the first embodiment described above.

Next, a fifth embodiment of the present invention will be described.
FIG. 14 is a cross-sectional view illustrating a semiconductor device according to this embodiment.
As shown in FIG. 14, in the semiconductor device 5 according to the present embodiment, in addition to the configuration of the semiconductor device 1 according to the first embodiment described above (see FIGS. 1 and 2), the entire drain layer 17 and An N-type region 81 having an N-type conductivity is provided between a portion of the drift layer 18 on the drain layer 17 side and the DNW 12. The N-type region 81 is surrounded by the P well 13 and is not in contact with the drain layer 17, the drift layer 18, and the DNW 12, and is in a floating state.

  The N-type region 81 may be formed by forming a resist block using a dedicated mask and implanting donor ions using the resist block as a mask. Further, the drift layer 18 has a two-stage structure in which the drain side portion and the source side portion are divided, the impurity concentration of the drain layer side portion is relatively high, and the impurity concentration of the source side portion is relatively high. In the case of lowering, the N-type region 81 may be formed using a mask for implanting donor ions into the drain side portion.

  According to the present embodiment, by providing the N-type region 81 in the P well 13, the depletion layer easily extends between the drain layer 17 and the DNW 12, and vertical punch-through is likely to occur. As a result, the allowable range of the P well 13 such as thickness and impurity concentration can be widened, and the degree of freedom in designing the semiconductor device is improved. Other configurations, operations, and effects of the present embodiment are the same as those of the first embodiment.

  While the present invention has been described with reference to the embodiments, the present invention is not limited to these embodiments. Those in which those skilled in the art appropriately added, deleted, or changed the design of the above-described embodiments are also included in the scope of the present invention as long as they have the gist of the present invention. For example, in each of the above-described embodiments, an example in which the LDMOS is an N-channel type is shown, but the present invention can also be applied to a P-channel type LDMOS. Further, the semiconductor device according to the present invention is not limited to a DC-DC converter.

1, 2, 2a, 3, 4, 5, 31, 101, 102 Semiconductor device, 11 P-type substrate, 12 Deep N well (DNW), 12d, 13d Drain side region, 12s, 13s Source side region, 13 63 P well, 14 channel implantation region, 15 source layer, 16, 19, 20 contact layer, 17 drain layer, 18 drift layer, 21 gate electrode, 22 gate insulating film, 26, 46 N-type LDMOS, 52 deep N well (DNW), 53 deep P well (DPW), 71 resist block, 81 N-type region, C central portion, D end portion, E equipotential surface, R region

Claims (5)

A first conductivity type semiconductor layer;
A second conductivity type deep well formed in a part of the upper layer portion of the semiconductor layer;
A first conductivity type well formed in a part of an upper layer portion of the deep well;
A second conductivity type source layer formed in the well;
A drain layer of the second conductivity type having the same potential as the deep well and formed in the well and spaced apart from the source layer;
A second conductive type contact layer formed outside the well in the upper layer portion of the deep well and connected to the drain layer;
A gate electrode provided immediately above the region between the source layer and the drain layer;
A gate insulating film provided between the well and the gate electrode;
A drift layer of a second conductivity type formed between the drain layer in the upper layer portion of the well and a region directly under the gate electrode, and having an effective impurity dose amount lower than an effective impurity dose amount of the drain layer. When,
With
In a state where a reverse bias voltage is applied between the source layer and the drain layer, a first depletion layer is formed between the drain layer and the well, and between the well and the deep well. A second depletion layer is formed, punch-through does not occur between the source layer and the drain layer, and the first depletion layer and the second depletion are below the junction breakdown voltage of the well and the drain layer. A semiconductor device characterized by being connected to a layer.   A first conductivity type region formed in a part of an upper layer portion of the well, surrounding the source layer, not surrounding the drain layer, and having an effective impurity dose amount higher than an effective impurity dose amount of the well; The semiconductor device according to claim 1, further comprising:   3. The semiconductor according to claim 1, wherein a voltage at which the drain layer and the deep well are electrically connected is a voltage lower than a junction breakdown voltage between the drain layer and the well. 4. apparatus.   An effective impurity dose in a portion of the well corresponding to a region immediately below the drain layer is lower than an effective impurity dose in a portion of the well corresponding to a region immediately below the source layer. The semiconductor device according to claim 1.   The semiconductor device further includes a second conductivity type region provided between the drain layer and the deep well, surrounded by the well, and not in contact with the drain layer and the deep well. The semiconductor device according to claim 1.

Images