JP2005085959A - Semiconductor device, and its driving and manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for driving a semiconductor device capable of suppressing the occurrence of a leakage current even for a well depth to the extent to a depletion when a high voltage is applied to a high withstand voltage MOSFET, and capable of decreasing the number of manufacturing processes of the semiconductor device. <P>SOLUTION: In driving the semiconductor device, a voltage having the equivalent sign as a drain voltage applied to a drain region 8 of a transistor is applied to a region 2 existing in the vicinity of the well and having the same conductive type as the drain region. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for driving a semiconductor device, and more particularly to a method for driving a semiconductor device in which a transistor is formed on a semiconductor substrate.

  High breakdown voltage MOSFETs are often used as drivers for liquid crystal displays. In recent years, liquid crystal displays have been developed with higher definition, lower power consumption, and larger screens. As a result, drivers used for the liquid crystal display are increasingly required to have a high breakdown voltage and low power consumption.

  Here, as a driver as described above, there is a semiconductor device in which a low breakdown voltage MOSFET and a high breakdown voltage MOSFET are provided on the same semiconductor substrate. The high breakdown voltage MOSFET constitutes a CMOS and is used for a peripheral circuit connected to the inside and outside of the semiconductor chip. The low breakdown voltage MOSFET constitutes a CMOS and is used in a circuit for controlling the high breakdown voltage MOSFET. Hereinafter, the configuration of the high voltage MOSFET and the low voltage MOSFET used in the semiconductor chip will be described with reference to the drawings. FIG. 6A is a diagram showing a cross-sectional structure of the high voltage MOSFET. FIG. 6B is a diagram showing a cross-sectional structure of the low breakdown voltage MOSFET. In FIG. 6, the high breakdown voltage MOSFET and the low breakdown voltage MOSFET are described separately, but these are formed on the same semiconductor substrate.

  The transistor shown in FIG. 6A is a CMOS in which a high breakdown voltage Nch MOSFET and a high breakdown voltage Pch MOSFET are arranged side by side. Here, the right transistor in FIG. 6A is a high breakdown voltage PchMOSFET, and the left transistor in FIG. 6A is a high breakdown voltage NchMOSFET.

  An N-type well 102 is formed on the surface of the P-type semiconductor substrate 101. On the surface of the N-type well 102, a high breakdown voltage Nch MOSFET and a high breakdown voltage Pch MOSFET are formed. First, the high breakdown voltage Nch MOSFET will be described.

  A P-type well 103 is formed in the left half of the N-type well 102. Furthermore, an N-type source diffusion 107a, an N-type drain diffusion 107b, a guard band P-type diffusion layer 108, and LOCOS oxide films 109a to 109f are formed on the surface of the P-type well 103. Further, an N-type offset diffusion layer 104, a P-type channel stop diffusion layer 105, and an N-type channel stop diffusion layer 106 are formed under the LOCOS oxide films 109a to 109f. Here, the N-type offset diffusion layer 104 is formed on both sides of the N-type source diffusion 107a and the N-type drain diffusion 107b. Gate electrode polysilicon 110 is formed so as to cover part of LOCOS oxide films 109c and 109d and gate oxide film 111. A P-type channel stop diffusion layer 105 is formed so as to be in contact with the N-type offset diffusion layer 104.

  Next, a high voltage PchMOSFET will be described. An N-type well 203 is formed in the right half of the N-type well 102. Further, a P-type source diffusion 207a, a P-type drain diffusion 207b, a guard band N-type diffusion layer 208, and LOCOS oxide films 209a to 209e are formed on the surface of the N-type well 203. Further, a P-type offset diffusion layer 204, an N-type channel stop diffusion layer 205, and a P-type channel stop diffusion layer 206 are formed under the LOCOS oxide films 209a to 209e. Here, the P-type offset diffusion layer 204 is formed around the P-type source diffusion 207a and the P-type drain diffusion 207b. In addition, gate electrode polysilicon 210 is formed so as to cover part of LOCOS oxide films 209 b and c and gate oxide film 211. An N-type channel stop diffusion layer 205 is formed so as to be in contact with the P-type offset diffusion layer 204. The high breakdown voltage NchMOSFET and the high breakdown voltage PchMOSFET have the configuration as described above.

  On the other hand, the transistor shown in FIG. 6B is a CMOS in which a low breakdown voltage Nch MOSFET and a low breakdown voltage Pch MOSFET are arranged side by side. Here, the right transistor in FIG. 6B is a low breakdown voltage PchMOSFET, and the left transistor in FIG. 6B is a low breakdown voltage NchMOSFET.

  An N-type well 302 is formed on the surface of the semiconductor substrate 101. On the surface of the N-type well 302, a low breakdown voltage Nch MOSFET and a low breakdown voltage Pch MOSFET are formed. First, the low breakdown voltage Nch MOSFET will be described.

  A P-type well 303 is formed in the left half of the N-type well 302. Further, an N-type source diffusion 306a, an N-type drain diffusion 306b, and LOCOS oxide films 307a and b are formed on the surface of the P-type well 303. Further, a P-type channel stop diffusion layer 304 and an N-type channel stop diffusion layer 305 are formed under the LOCOS oxide films 307a and 307b. A gate electrode polysilicon 308 is formed on the gate oxide film 311.

  Next, the low breakdown voltage Pch MOSFET will be described. In the right half of the N-type well 302, an N-type well 403 is formed. Further, an N-type source diffusion 406a, an N-type drain diffusion 406b, and LOCOS oxide films 407a and 407b are formed on the surface of the N-type well 403. Further, a P-type channel stop diffusion layer 404 and an N-type channel stop diffusion layer 405 are formed under the LOCOS oxide films 407a and 407b. A gate electrode polysilicon 408 is formed on the gate oxide film 411. The low breakdown voltage NchMOSFET and the low breakdown voltage PchMOSFET have the above-described configuration.

  Here, as shown in FIG. 6, the depth of the P-type well 103 formed in the high breakdown voltage Nch MOSFET and the depth of the N type well 203 formed in the high breakdown voltage Pch MOSFET is D3, and the P type well formed in the low breakdown voltage Nch MOSFET. 303 and the depth of the N-type well 403 formed in the low breakdown voltage PchMOSFET is D4. Comparing D3 and D4, D3 is larger than D4, as shown in FIG. The reason why the MOSFET has the above structure is to prevent the occurrence of a leakage current. This will be described in detail below with reference to FIG.

  First, the drain electrode of the high breakdown voltage MOSFET (that means the electrodes of the drain diffusions 107b and 207b; hereinafter the same) means the drain electrode of the low breakdown voltage MOSFET (that is, the electrodes of the drain diffusions 306b and 406b. ) Higher voltage is applied. Further, in the conventional MOSFET driving method, the N-type well 102 and the semiconductor substrate 101 are set to the ground potential. Also, the P-type well 103 is often set to the ground potential. Therefore, the P-type well 103 formed in the high breakdown voltage MOSFET is more easily depleted than the P-type well 303 and the N-type well 403 formed in the low breakdown voltage MOSFET.

  As a result, there is a problem that leakage current tends to occur between the drain electrode of the high breakdown voltage Nch MOSFET and the N-type well 102. On the other hand, in the case of a high breakdown voltage PchMOSFET, the N-type well 203 and the N-type well 102 are of the same conductivity type. Therefore, depending on the depletion of the N-type well 203, there is a gap between the drain electrode of the PchMOSFET and the N-type well 102. It is difficult for leak current to occur.

  In order to solve such a problem, in the MOSFET of FIG. 6, the depth D3 of the P-type well 103 is made deeper than the depth D4 of the P-type well 303. This prevents the P-type well 103 from being completely depleted even when a high voltage is applied to the drain electrode of the high voltage NchMOSFET.

Moreover, as prior art in the said field | area, the invention shown, for example in patent document 1 also exists.
JP-A-11-204786

  However, as described above, when manufacturing MOSFETs having different well depths depending on regions, the large number of manufacturing steps becomes a problem. This will be described in detail below.

  In the MOSFET shown in FIG. 6, as described above, the depth D3 of the well formed in the region where the high breakdown voltage MOSFET is formed and the depth D4 of the well formed in the region where the low breakdown voltage MOSFET is formed. Different. As described above, if the depth of the well is different for each region, the processing conditions in the ion implantation processing and thermal diffusion processing for forming each well are different. Therefore, the well in the region where the high breakdown voltage MOSFET is formed and the well in the region where the low breakdown voltage MOSFET is formed cannot be formed in a common process. As a result, the number of steps for manufacturing the MOSFET increases.

  Therefore, the depth D3 of the P-type well 103 and the N-type well 203 is set to such a depth that the P-type well 103 and the N-type well 203 are not depleted even when a high voltage is applied to the drain electrode of the high voltage MOSFET. In addition, it is conceivable to make the depth D3 of the P-type well 103 and the N-type well 203 equal to the depth D4 of the P-type well 303 and the N-type well 403. As described above, by determining D3 and D4, it is possible to suppress a leakage current generated due to depletion of the P-type well 103 and the N-type well 203. Further, since the P-type well 103, the N-type well 203, the P-type well 303, and the N-type well 403 have the same depth, these wells can be formed by the same thermal diffusion treatment, and the MOSFET is formed. The number of manufacturing processes is reduced.

  However, the depth D3 of the P-type well 103 and the N-type well 203 is set to such a depth that the P-type well 103 and the N-type well 203 are not completely depleted even when a high voltage is applied to the high voltage MOSFET. As a result, the interval D5 between the N-type wells 102 becomes small. As a result, there is no problem when the potential of the P-type well 103 is set to the ground potential when the N-type well 102 and the semiconductor substrate 101 are at the ground potential, but in the case where the P-type well 103 is set to a negative high voltage. When the MOSFET is driven, a new problem arises that leakage current is likely to occur between the semiconductor substrate 101 and the P-type well 103. Further, since the depth of each formed well is relatively deep, there is a problem that the time required for the thermal diffusion treatment of the well 103 becomes long.

  Accordingly, an object of the present invention is to reduce the thermal diffusion time of the well when a high voltage is applied to the high voltage MOSFET, and to generate a leakage current even at a well depth that is completely depleted. It is an object of the present invention to provide a driving method of a semiconductor device that can be suppressed and the number of manufacturing steps of the semiconductor device can be reduced.

  In the present invention, when the semiconductor device is driven, a voltage having the same sign as the drain voltage applied to the drain region of the transistor is applied to a region existing around the well and having the same conductivity type as the drain region. Applied.

  The region present around the well may be a well having the same conductivity type as the drain region or a semiconductor substrate.

  Further, it is desirable that the voltage applied to the region existing around the well is a voltage having the same magnitude as the drain voltage.

  Here, the present invention is directed not only to the method for driving the semiconductor device but also to the semiconductor device. Specifically, the semiconductor device includes a well formed in the vicinity of the surface of the semiconductor substrate, a transistor formed in the surface of the well, a periphery of the well, and the same conductivity type as the drain region of the transistor. A region and an electrode for applying the same voltage to a region existing around the well simultaneously with the drain region of the transistor are provided.

  In addition, a low breakdown voltage well having substantially the same depth as the well and formed near the surface of the semiconductor substrate, and a low breakdown voltage transistor formed on the surface of the low breakdown voltage well and driven at a lower voltage than the transistor Further, it may be provided.

  The present invention is directed not only to a semiconductor device but also to a method for manufacturing a semiconductor device. Specifically, a first well for forming the first transistor and a second well for forming the second transistor are simultaneously formed in predetermined regions of the semiconductor substrate, respectively. Formed in the first well, the second transistor is formed in the second well, is formed in the semiconductor substrate and is present in the periphery of the first well, and the drain region of the transistor An electrode for applying a voltage having the same sign as the drain voltage of the first transistor is formed in a region having the same conductivity type.

  In the present invention, a voltage having the same sign as the voltage applied to the drain region is applied to a region that exists around the well where the transistor is formed and has the same conductivity type as the drain region. It is trying to apply. For this reason, the potential of the region existing around the well becomes higher than that of the well. As a result, even if a high voltage that completely depletes the well is applied to the drain region, leakage current is prevented from occurring between the drain region and the region existing around the well. In other words, by applying the driving method, it is possible to prevent the occurrence of leakage current even if the depth of the well is reduced. Therefore, the well depth of the high breakdown voltage MOSFET can be made equal to the well depth of the low breakdown voltage MOSFET, and these two wells can be formed by the same process.

  Further, since the voltage applied to the region existing around the well and the drain voltage are set to be approximately the same, the potentials of these two regions become substantially equal. As a result, the occurrence of leakage current in the region between these two is further suppressed.

  A semiconductor device and a driving method thereof according to an embodiment of the present invention will be described below with reference to the drawings. The semiconductor device is a device in which a high breakdown voltage MOSFET and a low breakdown voltage MOSFET are formed on the same semiconductor substrate. In the semiconductor device according to the present embodiment, the depth of the well in the region where the high breakdown voltage MOSFET is formed is shallow according to the depth of the well in the region where the low breakdown voltage MOSFET is formed. This is different from the conventional semiconductor device described above. Furthermore, the semiconductor device according to the present embodiment is different from the conventional semiconductor device in the voltage application method during driving. Here, FIG. 1 is a diagram showing a cross-sectional structure of the semiconductor device. Specifically, FIG. 1A shows a cross-sectional structure of a high voltage MOSFET, and FIG. 1B shows a cross-sectional structure of a low voltage MOSFET. In FIG. 1, the high breakdown voltage MOSFET and the low breakdown voltage MOSFET are described separately, but these are formed on the same semiconductor substrate.

First, the structure of the high voltage MOSFET will be described with reference to FIG. The high breakdown voltage MOSFET constitutes a CMOS and is used for a peripheral circuit that connects the inside of the semiconductor chip and an external circuit. The high voltage MOSFET is driven at a higher voltage than the low voltage MOSFET.

  An N-type well 2 is formed on a P-type semiconductor substrate 1 in a region where a high voltage MOSFET is formed. A high breakdown voltage Nch MOSFET is formed in the left half of the N type well 2, and a high breakdown voltage Pch MOSFET is formed in the right half of the N type well 2. That is, in FIG. 1A, the left transistor is a high breakdown voltage Nch MOSFET and the right transistor is a high breakdown voltage Pch MOSFET.

  The high breakdown voltage Nch MOSFET is formed on the P-type well 3 formed on the N-type well 2, and includes N-type offset diffusion layers 4a to 4d, P-type channel stop diffusion layers 5a to 5e, N-type channel stop diffusion layer 6, N-type source diffusion 7, N-type drain diffusion 8, gate electrode polysilicon 9, gate oxide film 10, guard band P-type diffusion layers 11a and b, and LOCOS oxide films 12a to 12f are provided. Below, arrangement | positioning of each structure part is demonstrated.

  First, the guard band P-type diffusion layer 11a, the N-type source diffusion 7, the N-type drain diffusion 8, and the guard band P-type diffusion layer 11b are arranged on the surface of the P-type well 3 in a state of being separated from each other. LOCOS oxide films 12b to 12e are formed between the guard band P-type diffusion layer 11a, the N-type source diffusion 7, the N-type drain diffusion 8, and the guard band P-type diffusion layer 11b. Thereby, each of the guard band P-type diffusion layer 11a, the N-type source diffusion 7, the N-type drain diffusion 8, and the guard band P-type diffusion layer 11b is insulated.

  Further, a gate oxide film 10 is formed on the surface of the P-type well 3 between the LOCOS oxide films 12c and 12d. The gate electrode polysilicon 9 is formed so as to cover a part of the LOCOS oxide films 12c and 12d and the entire gate oxide film 10.

  N-type offset diffusion layers 4b and c are formed under LOCOS oxide films 12c and d. Under the LOCOS oxide films 12b and c, N-type offset diffusion layers 4a and d and P-type channel stop diffusion layers 5c and d are arranged. The N-type offset diffusion layer 4 is a diffusion layer formed with a lower impurity concentration than the N-type source diffusion 7 and the N-type drain diffusion 8 and plays a role in increasing the breakdown voltage of the transistor.

  LOCOS oxide films 12a and f are formed on the left and right ends of the high breakdown voltage Nch MOSFET. As a result, the high breakdown voltage Nch MOSFET is isolated from adjacent elements such as transistors. Under the LOCOS oxide films 12a and f, P-type channel stop diffusion layers 5a, b and e and an N-type channel stop diffusion layer 6 are formed. In addition, an electrode (not shown) for applying a voltage is provided in the N-type well 2 almost directly below the N-type drain diffusion 8.

  Next, the high breakdown voltage PchMOSFET is formed on the N-type well 23 formed on the N-type well 2, and the P-type offset diffusion layers 24a to 24d, the P-type channel stop diffusion layer 25, and the N-type channel stop diffusion layer 26a. -D, P-type source diffusion 27, P-type drain diffusion 28, gate electrode polysilicon 29, gate oxide film 30, guard band N-type diffusion layers 31a and b, and LOCOS oxide films 32a-f. Below, arrangement | positioning of each structure part is demonstrated.

  First, the guard band N-type diffusion layer 31a, the P-type source diffusion 27, the P-type drain diffusion 28, and the guard band N-type diffusion layer 31b are arranged on the surface of the N-type well 23 in a state of being separated from each other. LOCOS oxide films 32b to 32e are formed between the guard band N-type diffusion layer 31a, the P-type source diffusion 27, the P-type drain diffusion 28, and the guard band N-type diffusion layer 31b. Thereby, each of the guard band N-type diffusion layer 31a, the P-type source diffusion 27, the P-type drain diffusion 28, and the guard band N-type diffusion layer 31b is insulated.

  Further, a gate oxide film 30 is formed on the N-type well 23 between the LOCOS oxide films 32c and d. The gate electrode polysilicon 29 is formed so as to cover part of the LOCOS oxide films 32 c and d and the entire gate oxide film 30.

  Further, P-type offset diffusion layers 24b and c are formed under the LOCOS oxide films 32c and d. P-type offset diffusion layers 24a and 24d and N-type channel stop diffusion layers 26b and 26c are arranged under the LOCOS oxide films 32b and e. The P-type offset diffusion layer 24 is a diffusion layer formed with a lower impurity concentration than the P-type source diffusion 27 and the P-type drain diffusion 28, and plays a role in increasing the breakdown voltage of the transistor.

  LOCOS oxide films 32a and f are formed on the left and right ends of the high breakdown voltage Nch MOSFET. As a result, the high breakdown voltage Nch MOSFET is isolated from adjacent elements such as transistors. A P-type channel stop diffusion layer 25 and N-type channel stop diffusion layers 26a and d are formed under the LOCOS oxide films 32a and f. The LOCOS oxide film 12f and the LOCOS oxide film 32a existing at the center of FIG. 1A are the same LOCOS oxide film. In order to simplify the explanation, two reference signs are used properly.

  Next, the structure of the low breakdown voltage MOSFET will be described with reference to FIG. The low breakdown voltage MOSFET constitutes a CMOS and is used in a circuit for controlling the high breakdown voltage MOSFET. The low breakdown voltage MOSFET is driven at a lower voltage than the high breakdown voltage MOSFET.

  An N-type well 2 having the same depth as that of the N-type well 2 in FIG. 1A is formed on the semiconductor substrate 1 in the region where the low breakdown voltage MOSFET is formed. Further, a low breakdown voltage Nch MOSFET is formed in the left half of the N-type well 2, and a low breakdown voltage Pch MOSFET is formed in the right half of the N-type well 2. That is, in FIG. 1B, the left transistor is a low breakdown voltage NchMOSFET, and the right transistor is a low breakdown voltage PchMOSFET.

  The low breakdown voltage NchMOSFET is formed on a P-type well 43 formed on the N-type well 2, and includes P-type channel stop diffusion layers 45a and 45b, an N-type channel stop diffusion layer 46, an N-type source diffusion 47, an N-type drain. Diffusion 48, gate electrode polysilicon 49, gate oxide film 50, and LOCOS oxide films 52a and 52b are provided. Below, arrangement | positioning of each structure part is demonstrated.

  First, the N-type source diffusion 47 and the N-type drain diffusion 48 are spaced apart. A gate oxide film 50 is formed between the N-type source diffusion 47 and the N-type drain diffusion 48, and a gate electrode polysilicon 49 is formed on the gate oxide film 50.

  LOCOS oxide films 52a and 52b are formed on the left and right ends of the low breakdown voltage Nch MOSFET. As a result, the low breakdown voltage Nch MOSFET is isolated from other adjacent transistors.

  P-type channel stop diffusion layers 45a to 45c and N-type channel stop diffusion layer 46 are formed under LOCOS oxide films 52a and 52b.

  Next, the low breakdown voltage PchMOSFET is formed on the N-type well 63 formed on the N-type well 2, and the P-type channel stop diffusion layer 65, the N-type channel stop diffusion layers 66a and b, the N-type source diffusion 67, N-type drain diffusion 68, gate electrode polysilicon 69, gate oxide film 70, and LOCOS oxide films 72a and 72b are provided. Below, arrangement | positioning of each structure part is demonstrated.

  First, the N-type source diffusion 67 and the N-type drain diffusion 68 are spaced apart and arranged on the surface of the N-type well 63. A gate oxide film 70 is formed between the N-type source diffusion 67 and the N-type drain diffusion 68, and a gate electrode polysilicon 69 is formed on the gate oxide film 70.

  LOCOS oxide films 72a and 72b are formed on the left and right ends of the low breakdown voltage Nch MOSFET. As a result, the low breakdown voltage Pch MOSFET is isolated from other adjacent transistors and the like.

  A P-type channel stop diffusion layer 65 and N-type channel stop diffusion layers 66a and 66b are formed under the LOCOS oxide films 72a and 72b.

  Here, the depth of the well, which is a characteristic part of the semiconductor device according to the present embodiment, will be described. Conventionally, the depth of the P-type well is relatively deep in the region where the high breakdown voltage MOSFET is formed, and is relatively shallow in the region where the low breakdown voltage MOSFET is formed. On the other hand, in this embodiment, the well depth D1 of the P-type well in the region where the high breakdown voltage MOSFET of FIG. 1A is formed is equal to that of the region where the low breakdown voltage MOSFET of FIG. In accordance with the well depth D2 of the P-type well, it is formed relatively shallow. Thus, by making the well depth of the two regions the same, these wells can be formed in a common process, and the number of processes is reduced. Further, the N-type wells 23 and 63 can be formed in one common process by making the well depth the same, and the number of processes can be reduced similarly. This will be described in detail later in a method for manufacturing a semiconductor device.

  Hereinafter, a driving method of the semiconductor device according to the present embodiment configured as described above will be described with reference to the drawings. FIG. 2 is a graph showing the potential of each part of the semiconductor device when the semiconductor device is driven by the driving method according to the present embodiment. The horizontal axis indicates the depth when the surface of the semiconductor device is used as a reference, and the vertical axis indicates the potential at each point.

  In the semiconductor device according to the present embodiment, a positive drain voltage is applied to the N-type drain diffusion 8. Specifically, a voltage of about 40 V is applied to the N-type drain diffusion 8. Further, a positive voltage substantially equal to the drain voltage is also applied to an electrode (not shown) provided in the N-type well 2 existing under the high breakdown voltage Nch MOSFET. Specifically, a voltage of about 40 V is applied to the electrode provided in the N-type well 2. The reason why the voltage is applied also to the N-type well 2 in this way is that the drain voltage is applied to the N-type drain diffusion 8 to prevent the P-type well 3 from being depleted and generating a leak current. It is to do. Hereinafter, it will be described in detail with reference to the drawings.

  When a semiconductor device in which the depth of the P-type well of the high breakdown voltage NchMOSFET is the same as that of the P-type well of the low breakdown voltage NchMOSFET is driven by the conventional driving method in which only the drain voltage is applied, the high breakdown voltage NchMOSFET There is a problem that the P-type well is completely depleted, and a leak current flows from the N-type drain diffusion to the N-type well.

  On the other hand, in the method for driving the semiconductor device according to the present embodiment, a voltage having substantially the same magnitude as the drain voltage is applied to the N-type well 2 as described above. Therefore, the potential of each portion under the N-type drain diffusion 8 is as shown in FIG. Specifically, the potential of the N-type drain diffusion 8 and the potential of the N-type well 2 are substantially equal, and the potential of the portion between the N-type drain diffusion 8 and the N-type well 2 is lowered. Thereby, even if the P-type well 3 is completely depleted by applying a voltage to the N-type drain diffusion 8 and the N-type well 2, the N-type drain diffusion 8 leaks to the N-type well 2. Current is prevented from flowing. At this time, the semiconductor substrate 1 can be at a ground potential, and the P-type well 3 itself can be set to any high voltage within a range in which the N-type drain diffusion 8 does not become a forward bias.

  Finally, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to the drawings. 3 and 4 show process cross-sectional views in each process when the semiconductor device according to the present embodiment is manufactured.

  First, a silicon oxide film 80 and a silicon nitride film 81 are sequentially formed on a P-type semiconductor substrate 1 using thermal oxidation and a CVD method. Next, a photoresist film 82 having an opening in a region where the N-type well 2 is to be formed is formed on the silicon nitride film 81. As a result, the semiconductor device has the structure shown in FIG.

  Next, using the photoresist film 82 as a mask, the silicon nitride film 81 in the opening region is removed by dry etching. Thereafter, P (phosphorus) is implanted into the semiconductor substrate 1 using the photoresist film 82 and the silicon nitride film 81 as a protective mask. As a result, the semiconductor device has the structure shown in FIG.

  Next, the photoresist film 82 is removed by ashing or the like. Then, thermal oxidation treatment is performed on the silicon oxide film 80 that is not covered with the silicon nitride film 81. As a result, as shown in FIG. 3C, the film thickness of a part of the silicon oxide film 80 is increased. Thereafter, the silicon nitride film 81 is removed by wet etching or the like.

  When the removal of the silicon nitride film 81 is completed, B (boron) is implanted using the silicon oxide film 80 as a protective mask. Here, the silicon oxide film 80 has a thick film thickness in a region where P is implanted, and a thin film thickness in a region where P is not implanted. For this reason, B is implanted into a thin region (that is, a region where P is not implanted), and B is not implanted into a thick region (that is, a region where P is implanted). As a result, the semiconductor device has a structure as shown in FIG.

  Next, the semiconductor substrate 1 is subjected to a heat treatment to diffuse the impurities (P and B) implanted in FIGS. 3B and 3D. Thereby, the N-type well 2 is formed in each of the high breakdown voltage MOSFET region and the low breakdown voltage MOSFET region. The heat treatment conditions are, for example, a processing time of about 30 hours when the substrate temperature is about 1200 ° C. As a result, an N-type well 2 having a depth of about 12 μm is formed. When the heat treatment is completed, the silicon oxide film 80 is removed by wet etching. Here, as a chemical | medical agent used for a wet etching process, a hydrofluoric acid is mentioned, for example. Thereafter, as shown in FIG. 4E, a silicon oxide film 83 is formed on the surface of the semiconductor substrate 1 by thermal oxidation.

  Next, a photoresist film 84 having openings in regions where the N-type well 23 and the N-type well 63 are to be formed is formed on the silicon oxide film 83. Thereafter, as shown in FIG. 4F, P is implanted into the semiconductor substrate 1 using the photoresist film 84 as a protective mask. Thereafter, the photoresist film 84 is removed by ashing or the like.

  Next, a photoresist film 85 having an opening in a region where the P-type well 3 and the P-type well 43 are to be formed is formed on the silicon oxide film 83. Thereafter, as shown in FIG. 4G, B is implanted into the semiconductor substrate 1 using the photoresist film 85 as a protective mask. Thereafter, the protective mask is removed by ashing or the like.

  Next, the semiconductor substrate 1 is subjected to heat treatment to diffuse the impurities (P and B) implanted in FIGS. 4F and 4G. As a result, as shown in FIG. 4H, the P-type well 3, the P-type well 43, the N-type well 23, and the N-type well 63 are formed. The heat treatment conditions are, for example, that the substrate temperature is about 1150 ° C. and the processing time is about 105 minutes.

Here, since the P-type well 3, the P-type well 43, the N-type well 23, and the N-type well 63 are formed by the same thermal diffusion process, unlike the well of the conventional semiconductor device, the P-type well. 3. All P-type wells 43 have a uniform well depth (approximately 2.0 μm). The impurity concentration of the P-type wells 3 and 43 is about 2.4 × 10 ¹⁶ / cm ³ , and the impurity concentration of the N-type wells 23 and 63 is about 5.8 × 10 ¹⁶ / cm ³ .

  Thereafter, the silicon oxide film 83 is removed, and high breakdown voltage Nch MOSFET, high breakdown voltage Pch MOSFET, low breakdown voltage Nch MOSFET and low breakdown voltage Nch MOSFET are formed on the surface of each well.

  Further, an electrode (not shown) for applying a voltage substantially equal to the drain voltage applied to the N-type drain diffusion 8 is formed in the N-type well 2. Thereby, the semiconductor device as shown in FIG. 1 is completed.

  As described above, according to the method for driving a semiconductor device according to the present embodiment, a voltage having substantially the same magnitude as the drain voltage is applied to the N-type well existing under the P-type well in which the high voltage NchMOSFET is formed. Applied to. As a result, the potentials of the N-type drain diffusion and the N-type well are equalized, and leakage current is prevented from occurring between them.

  In addition, according to the method for driving a semiconductor device according to the present embodiment, even if the P-type well of the high breakdown voltage NchMOSFET is completely depleted, the generation of leakage current can be suppressed, so the depth of the well of the high breakdown voltage NchMOSFET. Can be made shallower than before. Therefore, the depth of the P-type well of the high breakdown voltage NchMOSFET can be made equal to the depth of the P-type well of the low breakdown voltage NchMOSFET and the N-type well of the low breakdown voltage PchMOSFET. As a result, the thermal diffusion process (the process of FIG. 4H) for forming these wells can be performed once, and the number of manufacturing steps of the semiconductor device is reduced.

  In the present embodiment, the high-breakdown-voltage Nch MOSFET has been described. However, the semiconductor device driving method according to the present embodiment can also be applied to the high-breakdown-voltage Pch MOSFET. However, when the driving method of the semiconductor device according to the present embodiment is applied to the high breakdown voltage Pch MOSFET, a negative charge is applied to the P-type semiconductor substrate. That is, the voltage applied to the well must have the same sign as the voltage applied to the drain electrode of the high voltage MOSFET. Furthermore, in this case, an electrode (not shown) for applying a voltage having the same sign as the drain voltage applied to the P-type drain diffusion 28 needs to be formed on the semiconductor substrate.

  Further, although the semiconductor device driving method according to the present embodiment is described as being applied to the N-type well existing under the P-type well, the region to which the voltage is applied is not limited to this. That is, the region to which the voltage is applied may be a region having the same conductivity type as that of the drain region and existing under the drain diffusion region. However, a well having a conductivity type different from that of the drain region needs to be present between the drain region and a region having the same conductivity type as the drain region.

  In the present embodiment, in the high breakdown voltage NchMOSFET, the magnitude of the voltage applied to the drain electrode and the magnitude of the voltage applied to the N-type well are substantially the same. The relationship is not limited to this. That is, the voltage applied to the drain electrode may be larger than the voltage applied to the N-type well. FIG. 5 is a graph showing the potential of each part of the semiconductor device when a voltage of 40 V is applied to the drain electrode and a voltage of 30 V is applied to the N-type well. The horizontal axis indicates the depth when the surface of the semiconductor device is used as a reference, and the vertical axis indicates the potential at each point.

  As shown in FIG. 5, even when the voltage applied to the N-type well is smaller than the voltage applied to the drain electrode, the potential distribution has a shape that is depressed at the center. That is, the potential of the N-type well to which the voltage is applied and the drain electrode are increased, and the potential of the P-type well to which no voltage is applied is decreased. Therefore, even when a voltage is applied as described above, it is possible to prevent a leak current from occurring.

  The driving method of the semiconductor device according to the present embodiment has been described as being applied to a semiconductor device in which a high breakdown voltage MOSFET and a low breakdown voltage MOSFET are formed on a single semiconductor substrate. However, the driving method is applied. The possible semiconductor devices are not limited to this. For example, the driving method of the semiconductor device according to the present embodiment can be applied to a semiconductor device in which only a high voltage MOSFET is formed on one chip.

  According to the semiconductor device driving method of the present invention, when a high voltage is applied to the high breakdown voltage MOSFET, the generation of a leakage current can be suppressed even when the well depth is sufficient to be depleted, and the semiconductor device This is effective as a method for driving a semiconductor device in which a transistor is formed on a semiconductor substrate.

The figure which showed the cross-section of the semiconductor device which concerns on this invention The figure which showed the electric potential of each part of the said semiconductor device when driving a semiconductor device with the drive method of the semiconductor device which concerns on this invention The figure which showed the manufacturing process of the semiconductor device based on this invention The figure which showed the manufacturing process of the semiconductor device based on this invention The figure which showed the electric potential of each part of the said semiconductor device when driving a semiconductor device with the drive method of the semiconductor device which concerns on this invention The figure which showed the section structure of the conventional semiconductor device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 N type well 3 P type well 4 N type offset diffused layer 5 P type channel stop diffused layer 6 N type channel stop diffused layer 7 N type source diffused 8 N type drain diffused 9 Gate electrode polysilicon 10 Gate oxide film 11 Guard band P type diffusion layer 12 LOCOS oxide film 23 N type well 24 P type offset diffusion layer 25 P type channel stop diffusion layer 26 N type channel stop diffusion layer 27 P type source diffusion 28 P type drain diffusion 29 Gate electrode polysilicon 30 Gate oxide film 31 Guard band N-type diffusion layer 32 LOCOS oxide film 43 P-type well 45 P-type channel stop diffusion layer 46 N-type channel stop diffusion layer 47 N-type source diffusion 48 N-type drain diffusion 49 Gate electrode polysilicon 50 Gate Oxide film 52 LOCOS oxide film 6 N-type well 65 P-type channel stop diffusion layer 66 N-type channel stop diffusion layer 67 N-type source diffusion 68 N-type drain diffusion 69 Gate electrode polysilicon 70 Gate oxide film 72 LOCOS oxide films 80 and 83 Silicon oxide film 81 Silicon nitride film 82, 84, 85 Photoresist film

Claims (7)

A method for driving a semiconductor device in which a transistor is formed on a semiconductor substrate,
The transistor is formed on a well formed near the surface of the semiconductor substrate,
When driving the semiconductor device, a voltage having the same sign as the drain voltage applied to the drain region of the transistor is applied to a region existing around the well and having the same conductivity type as the drain region. A method for driving a semiconductor device.   2. The method of driving a semiconductor device according to claim 1, wherein the region present around the well is a well having the same conductivity type as that of the drain region. The semiconductor substrate has a different conductivity type from the well;
2. The method of driving a semiconductor device according to claim 1, wherein the region existing around the well is the semiconductor substrate.   The method of driving a semiconductor device according to claim 1, wherein a voltage applied to a region existing around the well is a voltage substantially equal to the drain voltage. A semiconductor substrate;
A well formed near the surface of the semiconductor substrate;
A transistor formed on the surface of the well;
A region present around the well and having the same conductivity type as the drain region of the transistor;
A semiconductor device comprising: an electrode for applying a voltage having the same sign as a drain voltage applied to a drain region of the transistor to a region existing around the well. A low breakdown voltage well having substantially the same depth as the well and formed near the surface of the semiconductor substrate;
The semiconductor device according to claim 5, further comprising a low breakdown voltage transistor formed on a surface of the low breakdown voltage well and driven at a voltage lower than that of the transistor. A method of manufacturing a semiconductor device in which one or more first transistors and one or more second transistors driven at a lower voltage than the first transistor are formed on the same semiconductor substrate,
Simultaneously forming a first well for forming the first transistor and a second well for forming the second transistor;
Forming the first transistor in the first well;
Forming the second transistor in the second well;
A voltage having the same sign as the drain voltage of the first transistor is applied to a region existing around the first well and having the same conductivity type as the drain region of the first transistor. Forming an electrode for forming a semiconductor device.

Images