JP2006060192A - Semiconductor device and fabricating method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving a PN-junction breakdown voltage and increasing a switching speed, and to provide a fabricating method therefor. <P>SOLUTION: A gate electrode 109 has an end extending over on a part of a LOCOS oxide film 107. A source electrode 111 has an end extending further than the gate electrode 109 over on the part of the LOCOS oxide film 107. An insulating film covering the gate electrode 109 and the LOCOS oxide film 107 is formed such that the film thickness between the gate electrode 109 and the source electrode 111 at an end region T, a region from the end of the gate electrode 109 at the side of the LOCOS oxide film 107 to a body region side of the gate electrode 109, as viewed from a main surface of a support substrate 101, is smaller than the thickness of an insulating film below the side end of a drain region 104 of the source electrode 111 and smaller than the thickness of an insulating film above the side end of a body region 105 of the gate electrode 109. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a high breakdown voltage lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is formed on an SOI (Silicon On Insulator) substrate and a manufacturing method thereof.

  In recent years, a semiconductor device in which an IC circuit and a high breakdown voltage element are combined is used for various applications. In particular, a high breakdown voltage lateral MOSFET is employed in a semiconductor device used for a plasma display drive circuit. The structure of a conventional high breakdown voltage lateral MOSFET will be described in detail below with reference to the drawings.

  FIG. 5 is a cross-sectional view showing a configuration of a conventional high breakdown voltage lateral MOSFET formed on an SOI substrate. In FIG. 5, a support substrate 101 is a substrate serving as a base for forming a lateral MOSFET, and a buried oxide film 102 is formed thereon. An SOI layer 103 is formed on the buried oxide film 102. Although the support substrate 101 and the SOI layer 103 are originally individual silicon single crystal substrates, they are bonded together via the buried oxide film 102 to constitute one substrate. Hereinafter, the substrate having such a configuration is referred to as an SOI substrate.

  The drain region 104 is formed by injecting a relatively low concentration N-type impurity into the SOI layer 103. Body region 105 is formed by injecting P-type impurities into SOI layer 103. The source region 106 is formed by implanting a high concentration N-type impurity into the body region 105. A LOCOS (Local Oxidation of Silicon) oxide film 107 is an element isolation film formed on the main surface of the SOI layer 103, and is an oxide film formed by a thermal oxidation method. The gate oxide film 108 is an insulating film formed on the drain region 104 and the body region 105 between the source region 106 and the LOCOS oxide film 107, and is formed in contact with the LOCOS oxide film 107.

  The gate electrode 109 is an electrode made of polycrystalline silicon and is formed on the gate oxide film 108. Interlayer insulating films 110a, 110b and 110c are formed on the main surface of the SOI substrate so as to cover gate electrode 109, LOCOS oxide film 107, and the like. The source electrode 111 is a metal electrode formed on the interlayer insulating films 110 a and 110 b, and part of the source electrode 111 is connected to the source region 106. The drain electrode 112 is a metal electrode formed on the interlayer insulating films 110 a and 110 c, and a part of the drain electrode 112 is connected to the drain region 104. The separation groove 113 is a groove for electrically separating adjacent elements. The filling insulating film 114 is an insulating film that fills the isolation trench 113.

  In the high breakdown voltage lateral MOSFET configured as described above, when a high voltage is applied to the drain electrode 112 while the source electrode 111 and the gate electrode 109 are grounded, a PN junction between the body region 105 and the drain region 104 is obtained. The electric field increases and a depletion layer spreads on the drain region 104 side having a lower impurity concentration than the body region 105. At this time, the spread of the depletion layer on the main surface of the drain region 104 is suppressed by the influence of the fixed charge existing in the drain region 104 and the interface charge existing at the interface between the drain region 104 and the LOCOS oxide film 107. The electric field concentrates on the PN junction, and the PN junction breakdown voltage tends to deteriorate.

  Therefore, a field plate structure is applied to the gate electrode 109 and the source electrode 111 in order to improve the PN junction breakdown voltage. In the case of the gate electrode 109, the field plate structure is a structure in which one end on the drain region 104 side is extended to the LOCOS oxide film 107 to provide a field plate portion 109a. Are integrally formed. In the case of the source electrode 111, a structure in which one end on the drain region 104 side is extended to the LOCOS oxide film 107 and the field plate portion 111a is provided is called a field plate structure, and the source electrode 111 and the field plate portion 111a are provided. And are integrally formed.

  In this way, by applying the field plate structure to the gate electrode 109 and the source electrode 111, the spread of the depletion layer in the main surface of the drain region 104 is promoted, and the concentration of the electric field in the PN junction is reduced. Thus, the PN junction breakdown voltage between the body region 105 and the drain region 104 can be improved. Such an effect is hereinafter referred to as a field plate effect.

  Further, if the field plate portion 111 a of the source electrode 111 is further extended in the drain region direction (the arrow direction shown in FIG. 5) than the field plate portion 109 a of the gate electrode 109, the field plate portion 109 is formed only by the gate electrode 109. When formed or when viewed from the main surface direction of the support substrate 101, the field plate effect can be enhanced as compared with the case where the field plate portion 109a extends in the drain region direction from the field plate portion 111a. .

  In FIG. 5, a broken line a <b> 5 indicates an equipotential line in the drain region 104 around the point A below the end of the field plate portion 111 a of the source electrode 111, and a broken line b <b> 5 indicates the end of the field plate portion 109 a of the gate electrode 109. An equipotential line in the drain region 104 centering on the underlying point B is shown. If the field plate portion 111a of the source electrode 111 extends further in the direction of the drain region than the field plate portion 109a of the gate electrode 109, the film thickness of the insulating film below the end of the field plate portion 111a, that is, the LOCOS oxide film 107 And the interlayer insulating film 110a are thicker than the thickness of the insulating film under the end of the field plate portion 109a of the gate electrode 109, that is, the thickness of the LOCOS oxide film 107. Therefore, the equipotential line (broken line b5) is drawn to the field plate portion 111a side, and a decrease in curvature is prevented. Thereby, the field plate effect can be further improved by suppressing an increase in the electric field at the point B below the end of the field plate portion 109a of the gate electrode 109.

  However, when a further high voltage is applied to the drain electrode 112, the electric field at the point A under the end of the field plate portion 111a of the source electrode 111 increases rapidly. In such a case, as shown in FIG. 6, the electric field at point A is increased by increasing the thickness of the insulating film below the end of the field plate portion 111a, particularly the thickness d1 of the interlayer insulating film 110a. Can be suppressed (see, for example, Patent Document 1).

  This is because by increasing the thickness d1 of the interlayer insulating film 110a, the distance from the depletion layer boundary in the drain region 104 to the source electrode 111 is increased, and equipotential lines (in the drain region centered on the point A) ( This is because the curvature of the broken line a6) is increased, and the effect of relaxing the electric field concentration is obtained. In addition, since the electric field is borne by the interlayer insulating film 110a, the LOCOS oxide film 107, and the drain region 104, an oxide film having a relative dielectric constant lower than that of silicon under the end of the field plate 111a of the source electrode 111, etc. This is also because the burden on the electric field in the drain region 104 can be reduced by increasing the film thickness of the interlayer insulating film 110a and the LOCOS oxide film 107 configured as described above.

  In FIG. 6, the equipotential line (broken line b <b> 6) is drawn to the field plate portion 111 a side of the source electrode 111 due to the field plate effect of the source electrode 111, so that the field plate portion 109 a is formed only by the gate electrode 109. As a result, the effect of preventing the curvature of the equipotential line (broken line b6) in the drain region around the point B from being lowered can be obtained, and the increase in the electric field below the end of the gate electrode 109 indicated by the point B can be suppressed. it can. Further, when the thickness d1 of the interlayer insulating film 110a is increased, the capacitance between the gate electrode 109 and the source electrode 111 is reduced, so that an effect of improving the switching speed can be obtained.

Further, in Patent Document 1, in order to further improve the PN junction breakdown voltage between the body region 105 and the drain region 104, in addition to the configuration of the semiconductor device shown in FIG. There has also been proposed a method in which an insulating plate (not shown) is partially provided on the PN junction to improve the PN junction breakdown voltage.
JP-A-9-289305

  However, as shown in FIG. 6, in the method of increasing the thickness d1 of the interlayer insulating film 110a below the end of the field plate portion 111a, the interlayer insulation formed inevitably above the end of the field plate portion 109a of the gate electrode 109. The thickness d2 of the film 110a is also increased. As a result, the field plate effect due to the source electrode 111 is reduced, and the equipotential line indicated by the broken line b6 greatly depends on the field plate effect due to the gate electrode 109. Further, since the insulating film under the end of the field plate portion 109a of the gate electrode 109, that is, the LOCOS oxide film 107 is thin, the electric field at the point B increases rapidly.

  FIG. 7 shows the result of analyzing the electric field distribution of the high breakdown voltage lateral MOSFET shown in FIGS. 5 and 6 by a two-dimensional simulation. In FIG. 7, the vertical axis of the graph represents the electric field (V / cm), the horizontal axis represents the measurement position of the electric field, and A and B on the horizontal axis represent points A and B in FIGS. 5 and 6. Respectively. In FIG. 7, the broken line indicates the analysis result when the film thickness of the interlayer insulating film 110a is 1.0 μm in the high breakdown voltage lateral MOSFET shown in FIG. 5, and the solid line indicates the high breakdown voltage lateral MOSFET shown in FIG. Shows the analysis result when the film thickness of the interlayer insulating film 110a is 2.0 μm.

  From the analysis result shown in FIG. 7, if the interlayer insulating film 110a is thickened, an increase in electric field at the point A below the end of the field plate portion 111a of the source electrode 111 can be suppressed, but the end of the field plate portion 109a of the gate electrode 109 is suppressed. It is clear that the electric field at point B below increases. Therefore, when the thickness of the interlayer insulating film 110a is equal to or less than a certain thickness, the PN junction breakdown voltage can be improved by increasing the thickness of the interlayer insulating film 110a. It can be seen that the PN junction breakdown voltage tends to deteriorate when the thickness of the film becomes a certain thickness or more. Therefore, there is a problem that the PN junction breakdown voltage cannot be further improved only by adjusting the thickness of the interlayer insulating film 110a.

  Further, as described in Patent Document 1, when an insulator plate is formed below the end of the field plate 111a of the source electrode 111, a process for depositing a new insulating film is required, which increases processing costs. Have the problem of Further, even if such an insulator plate is provided, the thickness of the insulating film between the gate electrode 109 and the source electrode 111 does not change, so that the switching speed is improved by reducing the capacitance between the gate electrode 109 and the source electrode 111. There is no effect.

  Therefore, an object of the present invention is to provide a semiconductor device that can improve the PN junction breakdown voltage and increase the switching speed, and a method for manufacturing the same.

  An invention for solving the above-described problems is directed to a semiconductor device, and the semiconductor device is an SOI layer formed on a supporting substrate through a buried oxide film, and is selectively formed on a main surface of the SOI layer. A first conductivity type body region; a second conductivity type source region formed on the main surface of the body region; a second conductivity type drain region formed on the main surface of the SOI layer so as to be adjacent to the body region; and a drain region The device isolation film formed above, the gate oxide film formed on the main surface of the SOI layer between the source region and the device isolation film, formed on the gate oxide film, one end extending over the device isolation film A gate electrode, an insulating film covering the gate electrode and the element isolation film, a source electrode formed on the insulating film, connected to the source region and having one end extending further in the direction of the drain region than the gate electrode, And Comprises a drain electrode connected to the drain region. Here, the insulating film is on the gate electrode extended on the element isolation film when viewed from the main surface direction of the support substrate, from the drain region side end of the gate electrode to the body region side. Is formed so that the film thickness in the end region is thinner than the film thickness of the insulating film under the drain region side end of the source electrode and the film thickness on the body region side end of the gate electrode.

  In this way, by making the thickness of the insulating film formed on the end region of the gate electrode thinner than other portions, while increasing the breakdown voltage under the end portion of the source electrode extended on the element isolation film, The breakdown voltage under the end of the gate electrode extending on the element isolation film can also be increased. In addition, the switching speed can be increased by reducing the capacitance between the gate electrode and the source electrode.

  In order to obtain the insulating film having the thickness as described above, the insulating film includes a first insulating film formed on the gate electrode and the element isolation film, and a second insulating film covering the first insulating film. The drain region side end of the first insulating film formed on the gate electrode does not overlap with the drain region side end of the gate electrode when viewed from the main surface direction of the support substrate. It is preferable to be in the state. Thereby, it is possible to increase the thickness of the insulating film related to the PN junction breakdown voltage and the switching speed while reducing only the thickness of the insulating film on the end region of the gate electrode.

  When viewed from the main surface direction of the support substrate, the separation distance between the drain region side end of the gate electrode and the body region side end of the first insulating film formed on the element isolation film is When it is larger than twice the film thickness of the insulating film 2, the PN junction breakdown voltage can be further increased and the switching speed can be increased. Further, an isolation groove reaching the buried oxide film may be further formed in the SOI layer, and this isolation groove is preferably filled with the first filling film.

  The present invention is also directed to a method for manufacturing a semiconductor device comprising the following steps. That is, first, a first conductivity type body region is selectively formed on the main surface of the SOI layer formed on the support substrate via the buried oxide film. Next, a second conductivity type source region is formed on the main surface of the body region. Next, a drain region of the second conductivity type adjacent to the body region is formed on the main surface of the SOI layer. Next, an element isolation film is formed on the drain region. Next, a gate oxide film is formed on the main surface of the SOI layer between the source region and the element isolation film. Next, a gate electrode having one end extending to the element isolation film is formed on the gate oxide film. Next, an insulating film that covers the gate electrode and the element isolation film is formed. Next, a source electrode connected to the source region and having one end extending further in the direction of the drain region than the gate electrode is formed on the insulating film. Next, a drain electrode connected to the drain region is formed. Then, in the step of forming the insulating film, when viewed from the main surface direction of the support substrate, on the gate electrode extending on the element isolation film, the body region extends from the drain region side end of the gate electrode. The insulating film is formed so that the thickness of the insulating film in the end region toward the side is smaller than the thickness of the source electrode below the end of the drain region and the thickness of the gate electrode on the end of the body region.

  Specifically, in the step of forming the insulating film, first, a first insulating film that covers the gate electrode and the element isolation film is formed. Next, by selectively etching the first insulating film covering the end region, the drain region of the first insulating film formed on the gate electrode when viewed from the main surface direction of the support substrate The side end and the drain region side end of the gate electrode are positioned so as not to overlap. Next, a second insulating film that covers the first insulating film and the element isolation film is formed.

  In addition, in the etching process, in addition to the end region, at least a part of the first insulating film formed on the element isolation film adjacent to the end region is etched, so that the main substrate of the support substrate is etched. When viewed from the surface direction, the second insulating film has a thickness that the drain region side end portion of the gate electrode and the body region side end portion of the first insulating film formed on the element isolation film have. It is preferable that the distance is larger than twice.

  Prior to forming the insulating film, an isolation groove extending from the main surface of the SOI layer to the buried oxide film may be formed. Then, when forming the first insulating film, the first insulating film is formed so as to fill the inside of the isolation trench and cover the gate electrode and the element isolation film. In this way, by using the first insulating film as the insulating film filling the isolation trench, it is not necessary to increase the number of processes as in the above-described conventional example, so that it is possible to prevent an increase in processing costs due to the addition of processes. it can.

  As described above, according to the present invention, without increasing the thickness of the insulating film on the end region of the gate electrode, the insulating film on the lower end of the field plate portion of the source electrode and on the end portion on the body region side of the gate electrode. Therefore, the PN junction breakdown voltage between the body region and the drain region can be improved. In addition, since the thickness of the insulating film between the gate electrode and the source electrode excluding the end region can be increased, the capacitance between the gate electrode and the source electrode can be reduced and the switching speed can be increased.

  Hereinafter, the semiconductor device and the manufacturing method thereof according to the present embodiment will be specifically described by taking an N-channel high breakdown voltage lateral MOSFET as an example. FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the present embodiment. 1 includes a support substrate 101, a buried oxide film 102, an SOI layer 103, a drain region 104, a body region 105, a source region 106, a LOCOS oxide film 107, a gate oxide film 108, a gate electrode 109, and an interlayer insulating film. 110a, 110b and 11c, a source electrode 111, a drain electrode 112, a separation trench 113, and filling insulating films 114a, 114b, 114c and 114d.

  The semiconductor device shown in FIG. 1 is formed on an SOI substrate. As described above, the SOI substrate is formed by bonding the support substrate 101 and the SOI layer 103, which were originally individual silicon single crystal substrates, through the buried oxide film 102 having a thickness of about 1 to 2 μm. The In such an SOI substrate, the SOI layer 103 is polished to a thickness of about 3 to 5 μm from the main surface and subjected to a planarization process.

  In the SOI layer 103, a drain region 104, a body region 105, and a source region 106 are formed. The drain region 104 is an impurity region formed by a relatively low concentration N-type impurity, the body region 105 is an impurity region formed by a P-type impurity, and the drain region 104 and the body region 105 are adjacent to each other. It is formed to do. The source region 106 is an impurity region formed by injecting a high concentration N-type impurity into the body region 105.

  The LOCOS oxide film 107 as an element isolation film is an oxide film for separating adjacent elements, and is formed on the main surface of the SOI layer 103 by a thermal oxidation method. The thickness of the LOCOS oxide film 107 is 200 to 600 nm. The gate oxide film 108 is an insulating film formed in a region to be a channel, and is formed in contact with the LOCOS oxide film 107 by a thermal oxidation method. The isolation trench 113 is a trench for electrically isolating adjacent elements, and is formed in a part of the body region 105 so as to reach the buried oxide film 102 from the main surface of the SOI layer 103. The drain electrode 112 is a metal electrode, and a part thereof is connected to the drain region 104.

  The gate electrode 109 is a polycrystalline silicon electrode formed on the drain region 104 and the body region 105 via the gate oxide film 108, and the source electrode 111 is partially connected to the source region 106. It is the metal electrode formed in this. In this embodiment, a field plate structure is applied to the gate electrode 109 and the source electrode 111 in order to improve the PN junction breakdown voltage. That is, the gate electrode 109 is provided with a field plate portion 109a having one end on the drain region 104 side extending to the LOCOS oxide film 107. The gate electrode 109 and the field plate portion 109a are integrally formed. Has been. The source electrode 111 is provided with a field plate portion 111a having one end on the drain region 104 side extending to the LOCOS oxide film 107. The source electrode 111 and the field plate portion 111a are integrally formed. ing. In addition, the field plate portion 111a of the source electrode 111 has a drain region direction (in the direction of the arrow shown in FIG. 1, which is closer to the drain electrode 112 than the field plate portion 109a of the gate electrode 109 in order to further increase the PN junction breakdown voltage. It extends in the direction of approach.

  Here, an insulating film, which is a characteristic part of the present embodiment, in particular, an insulating film formed between the gate electrode 109 and the source electrode 111 will be described in detail. In this embodiment, as an insulating film formed between the gate electrode 109 and the source electrode 111, an insulating film composed of a first insulating film and a second insulating film will be described as an example. The first insulating film is formed on the gate electrode 109 and the LOCOS oxide film 107. In this embodiment, the filling insulating films 114a and 114b for filling the inside of the isolation trench 113 are provided. 114c and 114d are used as the first insulating film. That is, the filling insulating films 114a, 114b, 114c, and 114d are formed so as to fill the isolation trench 113 and selectively cover each part of the SOI layer 103, the gate electrode 109, and the LOCOS oxide film 107. A TEOS (Tetra Ethyl Ortho Silicate) film is formed to a thickness of about 300 nm to 1000 nm.

  The second insulating film covers the first insulating film. Here, the interlayer insulating films 110a, 110b, and 110c will be described as examples. Interlayer insulating films 110a, 110b, and 110c are formed so as to cover filling insulating films 114a, 114b, 114c, and 114d, and selectively cover each part of SOI layer 103, gate electrode 109, and LOCOS oxide film 107. The The film thickness of the interlayer insulating films 110a, 110b, and 110c may be any film thickness that ensures a dielectric strength voltage between the gate electrode 109 and the source electrode 111, and is formed to be, for example, about 300 nm to 1000 nm.

  The first and second insulating films described above are on the gate electrode 109 extending on the LOCOS oxide film 107 when viewed from the main surface direction of the support substrate 101, and on the drain region side end of the gate electrode 109. The film thickness D1 in the region from the portion to the body region 105 side (hereinafter referred to as the end region T) is the thickness D2 of the insulating film below the end of the field plate portion 111a of the source electrode 111 and the body of the gate electrode 109. It is formed to be thinner than the film thickness D3 of the insulating film on the end portion on the region 105 side. In other words, the end region T is on the field plate portion 109a of the gate electrode 109 and is at least a partial region from the end portion of the field plate portion 109 to the body region 105 side.

  As described above, in the end region T of the gate electrode 109, only the interlayer insulating film 110a is provided as the insulating film, so that the electric field is relaxed under the field plate portion 109a end (point B) of the gate electrode 109. . Further, a filling insulating film 114a and an interlayer insulating film 110a are provided as insulating films below the end of the field plate portion 111a of the source electrode 111 so that the film thickness D2 is larger than the film thickness D1 and the electric field is reduced at the point A. I am trying. With such a configuration, in addition to the field plate effect, the PN junction breakdown voltage can be further improved.

  Further, a filling insulating film 114a and an interlayer insulating film 110a are provided as insulating films on the end of the gate electrode 109 on the body region 105 side to increase the thickness D3 of the insulating film, whereby the gate electrode 109 and the source electrode are formed. The capacity between the power supply 111 and the power supply 111 can be reduced, and the switching speed can be increased.

  Further, in the semiconductor device according to the present embodiment, when viewed from the main surface direction of the support substrate 101, the end of the filling insulating film 114 c formed on the LOCOS oxide film 107 on the gate electrode 109 side, and the gate electrode 109 The distance P from the end of the field plate portion 109a is preferably as large as possible. Specifically, it is preferably larger than twice the film thickness of the interlayer insulating film 110a. By providing such a separation distance P, the interlayer insulating film 110a can be formed between the source electrode 111 and the filling insulating film 114c without increasing the film thickness, and the electric field at the lower end (point B) of the field plate portion 109a. A relaxation effect is obtained and the PN junction breakdown voltage can be further improved.

  A method for manufacturing a lateral MOSFET having the above-described configuration will be described with reference to FIGS. 2A to 2D are cross-sectional views of the semiconductor substrate and its upper surface at each stage in the process of manufacturing the lateral MOSFET shown in FIG. FIG. 2A shows a state in which the gate insulating film 108, the gate electrode 109, and the LOCOS oxide film 107 are formed on the main surface of the SOI substrate. In order to obtain an SOI substrate in such a state, first, a P-type impurity such as boron is selectively introduced into the main surface of the SOI layer 103 by an ion implantation method, and the temperature is increased to about 1000 ° C. to 1200 ° C. Heat. As a result, the implanted impurities are diffused, and a body region 105 is formed in the SOI layer 103.

  Next, phosphorus and arsenic, which are N-type impurities, are selectively introduced into the main surface of the body region 105 by an ion implantation method and annealed at a high temperature of about 900.degree. As a result, a source region 106 that is a high-concentration N-type impurity region is formed in the body region 105. Further, phosphorus, which is an N-type impurity, is selectively introduced into the main surface of the SOI layer 103 by an ion implantation method and heated to a high temperature of 1000 ° C. to 1200 ° C., so that the implanted impurity is adjacent to the body region 105. By diffusing in this manner, the drain region 104 is formed in the SOI layer 103.

  Next, a LOCOS oxide film 107 is formed on the main surface of the drain region 104 by a thermal oxidation method. Further, a gate oxide film 108 is formed by thermal oxidation on the drain region 104 and the body region 105 that serve as channel regions. A gate electrode 109 made of polycrystalline silicon is formed on the gate oxide film 108. Here, the gate electrode 109 extends at one end on the drain region 104 side to the LOCOS oxide film 107 to simultaneously form a field plate portion 109a.

  FIG. 2B shows a state where the main surface of the SOI substrate is covered with the filling insulating film 114. In order to obtain an SOI substrate in such a state, first, RIE (Reactive Ion Etching) is performed from the main surface of the SOI layer 103 to the buried oxide film 102 in the peripheral portion of the element so as to separate adjacent elements. The separation groove 113 is formed. Next, a filling insulating film 114 such as a TEOS film is formed by CVD (Chemical Vapor Deposition) so as to fill the isolation trench 113 and cover the entire surface of the SOI substrate. The thickness of the filling insulating film 114 is about 1000 nm in the isolation trench 113, and is about 300 nm in other locations.

  FIG. 2C shows a state in which the filling insulating film 114 is patterned into a desired shape. In order to obtain an SOI substrate in such a state, first, a resist is applied on the filling insulating film 114 to form a resist film (not shown). The resist film is exposed and developed to form a resist pattern patterned into a desired shape. Then, by using this resist pattern as a mask, the filling insulating film 114 is etched by etching using RIE or hydrogen fluoride solution, so that the filling insulating films 114a, 114b, 114c, and 114d patterned in a desired shape are formed. Is formed. The resist pattern is removed by ashing or the like.

  Here, when patterning the filling insulating film 114, the distance P between the end of the filling insulating film 114c on the gate electrode 109 side and the field plate portion 109a of the gate electrode 109 is as large as possible. The interlayer insulating film 110a to be formed is preferably formed to be larger than twice the film thickness. This is due to the following reason. On the portion of the LOCOS oxide film 107 where the separation distance P is provided, film material is deposited from both the end of the field plate portion 109a of the gate electrode 109 and the end portion of the filling insulating film 114c on the gate electrode 109 side. An insulating film 110a is formed. Therefore, when the separation distance P is too small, the film materials deposited from both sides of the gate electrode 109 and the filling insulating film 114c come into contact with each other, and the thick interlayer insulating film 110a is formed on the LOCOS oxide film 107. It is formed. Thereby, since the electric field relaxation effect under the end of the field plate portion 109a (point B) is reduced, it is preferable that the separation distance P be as large as possible.

  FIG. 2D shows a state in which the lateral MOSFET according to this embodiment is formed. In order to obtain the semiconductor device in such a state, first, a BPSG (Boron Phosphorous Silicate Glass) film is formed on the entire surface of the substrate by the CVD method. Next, the interlayer insulating films 110a, 110b, and 110c are formed by annealing the BPSG film at a high temperature. Here, the end portions of the interlayer insulating films 110a, 110b, and 110c formed on the filling insulating films 114a, 114b, 114c, and 114d are preferably tapered in order to ensure coverage.

  Next, the source electrode 111 and the drain electrode 112 are formed on the interlayer insulating films 110a, 110b, and 110c. The source electrode 111 is connected to a part of the source region 106 and extends further on the LOCOS oxide film 107 in the direction of the drain region than the gate electrode 109. The drain electrode 112 is formed so as to be connected to the drain region 104.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, in order to adjust the thickness of the insulating film between the gate electrode 109 and the source electrode 111, the isolation groove 113 is formed as the first insulating film. By using the filling insulating film 114 to be filled, it is not necessary to newly form an insulating film by deposition as described in Patent Document 1 described in the above conventional example, and the manufacturing cost can be reduced. Further, the thickness of the insulating film between the gate electrode 109 and the source electrode 111 can be easily set to a desired thickness by a simple process of patterning the first insulating film into a desired shape by etching. .

  Using the high breakdown voltage lateral MOSFET according to the present embodiment configured as described above and the conventional high breakdown voltage lateral MOSFET shown in FIG. 6, the interlayer insulating films 110a, 110b, and 110c have a thickness of 2.0 μm. The electric field distribution at a certain time was analyzed by two-dimensional simulation. The obtained analysis results are shown in FIG. In FIG. 3, the vertical axis represents the electric field (V / cm), and the horizontal axis represents the measurement position of the electric field. A and B on the horizontal axis indicate points A and B in FIGS. 1 and 6, respectively. In FIG. 3, the broken line shows the electric field distribution of the high breakdown voltage lateral MOSFET of the present embodiment shown in FIG. 1, and the solid line shows the electric field distribution of the high breakdown voltage lateral MOSFET shown in FIG.

  As is clear from the analysis results shown in FIG. 3, the high breakdown voltage lateral MOSFET according to the present embodiment has an electric field relaxation effect below the end of the field plate portion 109a (point B) of the gate electrode 109, as compared with the conventional structure. Is obtained.

  Further, using the high breakdown voltage lateral MOSFET according to the present embodiment configured as described above and the conventional high breakdown voltage lateral MOSFET shown in FIGS. 5 and 6, the film thickness of the interlayer insulating films 110a, 110b, and 110c. The PN junction withstand voltage when V is changed from 0.5 μm to 2.0 μm was examined. As the conventional high breakdown voltage lateral MOSFET, the high breakdown voltage lateral MOSFET shown in FIG. 5 is used when the interlayer insulating films 110a, 110b, and 110c have a film thickness of 0.5 μm to 1.5 μm. For the film thicknesses of 110a, 110b, and 110c of 2.0 μm, the high voltage lateral MOSFET shown in FIG. 6 was used. The obtained measurement results are shown in FIG.

  In FIG. 4, the vertical axis of the graph indicates the PN junction breakdown voltage (V), and the horizontal axis indicates the film thickness (μm) of the interlayer insulating films 110a, 110b, and 110c. In FIG. 4, black circles indicate the PN junction breakdown voltage of the high breakdown voltage lateral MOSFET of the present embodiment illustrated in FIG. 1, and white circles indicate the PN junction breakdown voltage of the high breakdown voltage lateral MOSFET illustrated in FIGS. 5 and 6. From the measurement results shown in FIG. 4, it is clear that the high breakdown voltage lateral MOSFET according to the present embodiment can improve the PN junction breakdown voltage as compared with the conventional structure, and in particular, the interlayer insulating films 110a and 110b. It can be seen that the tendency is remarkable when the film thicknesses of 110 and 110c are increased.

  In the above description, as the insulating film formed between the gate electrode 109 and the source electrode 111, the filling insulating film 114a as the first insulating film and the interlayer insulating film 110a as the second insulating film are used. Although described as an example, the present invention is not limited to this, and the film thickness on the end region T of the gate electrode 109 is determined depending on the film thickness and the gate electrode below the end of the field plate portion 111a of the source electrode 111. The insulating film may have a single-layer structure or a laminated structure of three or more layers as long as it is configured to be thinner than the film thickness on the body region side end portion 109. In the above description, the LOCOS oxide film 107 is not included as an insulating film, but the PN junction breakdown voltage can be further improved by increasing the thickness of the LOCOS oxide film 107 as in the conventional example. Can do.

  In the above description, the semiconductor device in which the separation groove 113 is formed has been described as an example, but the present invention can also be applied to a semiconductor device in which the separation groove 113 is not formed. However, for a semiconductor device in which the isolation trench 113 is formed, if the filling insulating film filling the isolation trench 113 is used as the first insulating film, an insulating film having a desired thickness can be easily formed without increasing the number of processes. This is preferable because it is possible.

  Furthermore, in the above description, an N-channel lateral MOSFET has been described as an example. However, the present invention is not limited to this, and can be applied to a P-channel lateral MOSFET. Further, a lateral diode or a lateral IGBT (Insulated Gate) is applicable. The present invention can also be applied to a semiconductor device in which a high voltage element such as a bipolar transistor) and a TC circuit are combined.

  The semiconductor device and the method of manufacturing the semiconductor device according to the present invention are useful for a semiconductor device in which an IC circuit and a high voltage element are combined.

Sectional drawing which shows the structure of the high voltage | pressure-resistant lateral MOSFET which concerns on embodiment of this invention The figure which shows the manufacturing process of the high voltage | pressure-resistant lateral MOSFET shown in FIG. The graph which shows the analysis result of the electric field distribution of the high voltage | pressure-resistant lateral MOSFET which concerns on this embodiment, and the conventional high voltage | pressure-resistant lateral MOSFET Graph showing the relationship between the PN junction breakdown voltage and the interlayer insulating film in the high breakdown voltage lateral MOSFET according to the present embodiment and the conventional high breakdown voltage lateral MOSFET Sectional view showing the structure of a conventional high voltage lateral MOSFET Sectional drawing which shows the structure of the high voltage | pressure-resistant lateral MOSFET which shows the prior art example different from FIG. The graph which shows the analysis result of the electric field distribution of the high voltage | pressure-resistant lateral MOSFET shown to FIG. 5 and FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Support substrate 102 Embedded oxide film 103 SOI layer 104 Drain region 105 Body region 106 Source region 107 LOCOS oxide film 108 Gate oxide film 109 Gate electrode 109a Field plate portions 110a, 110b, 110c Interlayer insulating film 111 Source electrode 111a Field plate portion 112 Drain electrode 113 Separation groove 114, 114a, 114b, 114c, 114d Filling insulating film

Claims (8)

An SOI layer formed on the support substrate through a buried oxide film;
A first conductivity type body region selectively formed on a main surface of the SOI layer;
A source region of a second conductivity type formed on the main surface of the body region;
A drain region of a second conductivity type formed on the main surface of the SOI layer so as to be adjacent to the body region;
An element isolation film formed on the drain region;
A gate oxide film formed on the main surface of the SOI layer between the source region and the element isolation film;
A gate electrode formed on the gate oxide film and having one end extending to the element isolation film;
An insulating film covering the gate electrode and the element isolation film;
A source electrode formed on the insulating film, connected to the source region, and having one end extending further in the direction of the drain region than the gate electrode;
A drain electrode connected to the drain region,
When viewed from the main surface direction of the support substrate, the insulating film is on the gate electrode extending on the element isolation film, from the drain region side end of the gate electrode to the body region side. The semiconductor device is characterized in that the film thickness in the end region is smaller than the film thickness under the drain region side end of the source electrode and the film thickness over the body region side end of the gate electrode. The insulating film includes a first insulating film formed on the gate electrode and the element isolation film, and a second insulating film covering the first insulating film,
The drain region side end portion of the first insulating film formed on the gate electrode is positioned so as not to overlap the drain region side end portion of the gate electrode when viewed from the main surface direction of the support substrate. The semiconductor device according to claim 1, wherein the semiconductor device is provided.   The distance between the drain region side end of the gate electrode and the body region side end of the first insulating film formed on the element isolation film when viewed from the main surface direction of the support substrate The semiconductor device according to claim 2, wherein is larger than twice the film thickness of the second insulating film.   The semiconductor device according to claim 2, wherein the SOI layer further includes an isolation trench reaching the buried oxide film, and the isolation trench is filled with the first insulating film. Selectively forming a body region of the first conductivity type on the main surface of the SOI layer formed on the support substrate via the buried oxide film;
Forming a second conductivity type source region on the main surface of the body region;
Forming a drain region of a second conductivity type adjacent to the body region on the main surface of the SOI layer;
Forming an element isolation film on the drain region;
Forming a gate oxide film on a main surface of the SOI layer between the source region and the element isolation film;
Forming a gate electrode having one end extended to the element isolation film on the gate oxide film;
Forming an insulating film covering the gate electrode and the element isolation film;
Forming a source electrode connected to the source region on the insulating film and having one end extending further in the direction of the drain region than the gate electrode;
Forming a drain electrode connected to the drain region,
The step of forming the insulating film is performed on the gate electrode extending on the element isolation film when viewed from the main surface direction of the support substrate, from the drain region side end of the gate electrode. The film thickness of the insulating film in the end region toward the body region side is smaller than the film thickness under the drain region side end of the source electrode and the film thickness on the body region side end of the gate electrode. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device. The step of forming the insulating film includes
Forming a first insulating film covering the gate electrode and the element isolation film;
By selectively etching the first insulating film covering the end region, the first insulating film formed on the gate electrode when viewed from the main surface direction of the support substrate. A step of making the drain region side end and the drain region side end of the gate electrode not overlap each other;
The method of manufacturing a semiconductor device according to claim 5, further comprising: forming a second insulating film that covers the first insulating film and the element isolation film.   In the etching process, in addition to the end region, at least a part of the first insulating film formed on the element isolation film adjacent to the end region is etched, thereby the support substrate. When viewed from the main surface direction of the first insulating film, the drain region side end of the gate electrode and the body region side end of the first insulating film formed on the element isolation film are connected to the second insulation. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor device is spaced apart by more than twice the thickness of the film. Prior to the step of forming the insulating film,
Forming a separation groove extending from the main surface of the SOI layer to the buried oxide film;
The step of forming the first insulating film is characterized in that the first insulating film is formed so as to fill the isolation trench and cover the gate electrode and the element isolation film. Item 7. A method for manufacturing a semiconductor device according to Item 6.

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