JP2003332577A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that can be improved in short- circuit resistance while contact resistance against an emitter electrode is maintained at a low level and the fall of avalanche resistance is prevented, and to provide a method of manufacturing the device. <P>SOLUTION: In this semiconductor device, an n-type electrical conductivity modulating layer 2 is formed on a p-type collector layer 1 and a p-type channel layer 3 is formed in a well-like state on the surface of the modulating layer 2. In addition, two emitter layers 9 are formed in parallel with each other in well-like states and stripe-like states on the surface of the channel layer 3 and, at the same time, a p+-type diffusion layer 5 is formed between the emitter layers 9. Each emitter layer 9 is has n+-type high-resistance regions 10 and n+-type low-resistance regions 11 alternately arranged along the length direction. Moreover, gas electrodes 7 are formed astride the electrical conductivity modulating layer 2 and emitter layers 9, and an emitter electrode 8 is formed astride the p+-type diffusion layer 5 and both the emitter layers 9. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a large current type semiconductor device in which an emitter layer is formed in a well and stripe shape on the surface of a channel layer and a method for manufacturing the same. .

[0002]

2. Description of the Related Art The structure of a conventional insulated gate bipolar transistor (IGBT) is shown in FIG. An n-type conductivity modulation layer 2 is formed on a p-type collector layer 1 having a collector electrode formed on its back surface, and a p-type channel layer 3 is formed in a well shape on the surface of the conductivity modulation layer 2. There is. Channel layer 3
On the surface of the two n + type emitter layers 4 parallel to each other.
Are formed in a well shape and in a stripe shape, and a p + diffusion layer 5 is formed between these emitter layers 4.
Further, a gate oxide film 6 is formed across the conductivity modulation layer 2 and the emitter layer 4, and a gate electrode 7 is formed thereon. Further, an emitter electrode 8 is formed across the p + diffusion layer 5 and both emitter layers 4.

When a positive bias voltage is applied between the gate electrode 7 and the emitter electrode 8, an n channel is formed on the surface of the channel layer 3 located immediately below the gate electrode 7, and FIG.
, An electron current passes from the collector electrode through the collector layer 1 and the conductivity modulation layer 2, and further to the channel layer 3
From the n channel of the emitter electrode 4 through the emitter layer 4
Flows to. Further, a hole current flows through the collector layer 1, the conductivity modulation layer 2 and the emitter electrode 8.

[0004]

However, since the emitter layer 4 is formed in the n + type having a small specific resistance in order to reduce the contact resistance with the emitter electrode 8, the voltage drop of the emitter layer 4 occurs when the load is short-circuited. A small and large electron current flows. In addition, there is a problem that the hole current induced by it also increases, resulting in a high saturation current value and a reduction in short circuit withstand capability. Here, if the specific resistance of the emitter layer 4 is increased, the voltage drop of the emitter layer 4 at the time of a large current becomes large, and the saturation current value can be decreased to improve the short circuit withstand capability. This causes a problem that contact resistance increases.

Further, without directly contacting the emitter electrode with the emitter layer, a plurality of comb-shaped branch portions are extended from the stripe-shaped emitter layer in the width direction and the emitter electrode is formed on the branch portions. By doing so, it has been proposed to increase the voltage drop due to the diffusion resistance parasitic on the branch portion. However, in order to secure the distance of the branch portion and increase the resistance value, the distance between the gate electrode and the emitter electrode is widened, and as a result, the base resistance of the parasitic transistor is increased and the avalanche withstand capability is reduced. Resulting in.

The present invention has been made in order to solve such a problem, and a semiconductor device capable of maintaining a low contact resistance with an emitter electrode and preventing a decrease in avalanche withstand capability while improving a short circuit withstand capability. And its manufacturing method.

[0007]

According to another aspect of the present invention, there is provided a semiconductor device having a second conductive layer formed on a first conductive type collector layer.
The first conductivity type channel layer is formed in a well shape on the surface of the second conductivity type conductivity modulation layer, and the second conductivity type emitter layer is formed in a well shape and in a stripe shape on the surface of the channel layer. In a semiconductor device in which a gate electrode is formed across a conductivity modulation layer and an emitter layer and an emitter electrode is formed across a channel layer and an emitter layer, the emitter layers are alternately arranged along the longitudinal direction. And a high resistance region and a low resistance region.

A method of manufacturing a semiconductor device according to the present invention is
In a method of manufacturing a semiconductor device in which a second conductive type emitter layer is formed in a well-like and stripe-like shape on a surface of a first conductive type channel layer, an oxide film is formed on the surface of the channel layer and oxidation is performed. The film is etched so that the thick film region and the thin film region are alternately arranged, and the high resistance region and the low resistance region are alternately arranged by implanting and diffusing the second conductivity type impurity from above the oxide film. Formed emitter layer,
This is a method of removing the oxide film.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows the configuration of a semiconductor device according to an embodiment of the present invention applied to an insulated gate bipolar transistor (IGBT). An n-type conductivity modulation layer 2 is formed on a p-type collector layer 1 having a collector electrode formed on its back surface, and a p-type channel layer 3 is formed in a well shape on the surface of the conductivity modulation layer 2. There is. On the surface of the channel layer 3, two emitter layers 9 are formed in parallel with each other in a well shape and in a stripe shape, and a p + diffusion layer 5 is formed between these emitter layers 9. Each emitter layer 9 has a structure in which n − type high resistance regions 10 and n + type low resistance regions 11 are alternately arranged along the longitudinal direction. Further, a gate oxide film 6 is formed across the conductivity modulation layer 2 and the emitter layer 9, and a gate electrode 7 is formed thereon. Further, an emitter electrode 8 is formed across the p + diffusion layer 5 and both emitter layers 9.

Next, the operation of this IGBT will be described. When a positive bias voltage is applied between the gate electrode 7 and the emitter electrode 8, an n channel is formed on the surface of the channel layer 3 located immediately below the gate electrode 7, and an electron current flows from the collector electrode to the collector layer 1 and the conductivity. The current flows from the n-channel on the surface of the channel layer 3 to the emitter electrode 8 through the emitter layer 9 through the modulation layer 2.

Here, since the emitter layer 9 has not only the n + type low resistance regions 11 but also the n− type high resistance regions 10 alternately arranged with the low resistance regions 11, an electron current is generated. The voltage drop increases when flowing through the emitter layer 9,
As a result, the saturation current value is reduced and the short circuit withstand capability is improved. On the other hand, since the emitter layer 9 has the n + type low resistance regions 11 alternately arranged with the n− type high resistance regions 10, the contact resistance between the emitter layer 9 and the emitter electrode 8 is kept low. A low on-voltage can be realized.

Since the emitter electrode 8 is in direct contact with the emitter layer 9, the distance between the gate electrode 7 and the emitter electrode 8 does not increase, and therefore the emitter layer 9 and the channel layer 3 are electrically connected. It is prevented that the base resistance of the parasitic transistor composed of the frequency modulation layer 2 and the avalanche resistance is lowered.

A method of manufacturing such a semiconductor device will be described. First, the n-type conductivity modulation layer 2 is laminated on the p-type collector layer 1, and the gate oxide film 6 is formed on the surface of the conductivity modulation layer 2. A gate electrode 7 is formed on this gate oxide film 6. Further, using the gate electrode 7 as a mask, for example, boron B is ion-implanted and then thermally diffused to form the p-type channel layer 3 in a well shape.

Next, as shown in FIG.
Silicon oxide SiO on the flannel layer 3 _TwoForming the membrane 12,
As shown in FIG. 2B, the thick film region 13 and the thin film region
Silicon oxide SiO so that 14 and 14 are alternately arranged._Two
The film 12 is etched. In FIG. 2B, the thin film region 1
4 has a film thickness of 0, that is, silicon oxide SiO_TwoThe membrane 12
It has been completely removed. In this state, as shown in FIG.
Ion implantation using arsenic As as an impurity.
Then, the thick film region 13 has a low concentration on the surface of the channel layer 3.
In addition, the thin film region 14 is heavily implanted with arsenic As.
Will be done. Furthermore, by applying an annealing treatment,
As shown in FIG. 2D, the n-type high resistance region
10 and n + type low resistance regions 11 are alternately arranged.
It Incidentally, when arsenic As is diffused, it is already formed.
The gate electrode 7 serves as a mask, and self-alignment
A resistance region 10 and a low resistance region 11 are formed. Furthermore
In addition, as shown in FIG.
_TwoThe film 12 is removed.

After that, boron B, for example, is ion-implanted by using a resist mask, and after removing the resist mask, annealing treatment is performed to form the p + diffusion layer 5. The p + diffusion layer 5 is for reducing the p-type contact resistance or the base resistance of the parasitic transistor. In addition, this p
The + diffusion layer 5 may be formed after the channel layer 3 is formed and before the emitter layer 9 is formed. Further, after forming an insulating film (not shown) so as to cover the gate electrode 7, the emitter electrode 8 is formed.

As described above, the silicon oxide SiO ₂ film 1
By utilizing the film thickness difference of 2, it becomes possible to form the high resistance regions 10 and the low resistance regions 11 alternately arranged in one silicon oxide SiO ₂ film 12. Although arsenic As was used as the n-type impurity and boron B was used as the p-type impurity, the present invention is not limited to this, and various known impurities can be used. Although an n-channel type IGBT is shown in FIG. 1, it may be a p-channel type. Further, the present invention is not limited to the IGBT, but can be applied to other semiconductor devices such as a power MOSFET. When applied to a power MOSFET, in the above description, the drain electrode and the drain layer may be used instead of the collector electrode and the collector layer 1, and the source electrode and the source layer may be used instead of the emitter electrode 8 and the emitter layer 9, respectively. .

[0017]

As described above, according to the present invention, the high resistance region and the low resistance region in which the emitter layers formed in stripes on the surface of the channel layer are alternately arranged along the longitudinal direction thereof are provided. Therefore, it becomes possible to maintain the contact resistance with the emitter electrode low and prevent the avalanche withstand capability from lowering while lowering the saturation current value and improving the short-circuit withstand capability.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a part of the manufacturing process of the semiconductor device according to the embodiment in the order of processes.

FIG. 3 is a sectional view showing a configuration of a conventional semiconductor device.

FIG. 4 is a cross-sectional view showing a path of an electron current in a semiconductor device.

[Explanation of Codes] 1 collector layer, 2 conductivity modulation layer, 3 channel layer,
7 gate electrode, 8 emitter electrode, 9 emitter layer, 1
0 high resistance region, 11 low resistance region, 12 silicon oxide film, 13 thick film region, 14 thin film region.

Claims (2)

[Claims] 1. A channel layer of a first conductivity type is formed on a surface of a conductivity modulation layer of a second conductivity type formed on a collector layer of the first conductivity type, and has a well shape. A second conductivity type emitter layer is formed in a well shape and in a stripe shape on the surface of the, a gate electrode is formed across the conductivity modulation layer and the emitter layer, and an emitter electrode is formed across the channel layer and the emitter layer. In the semiconductor device having the structure described above, the emitter layer includes high resistance regions and low resistance regions arranged alternately along the longitudinal direction thereof. 2. A second conductive layer is formed on the surface of the first conductive type channel layer.
In a method of manufacturing a semiconductor device in which a conductive type emitter layer is formed in a well shape and in a stripe shape, an oxide film is formed on a surface of a channel layer, and the oxide film is alternately arranged in a thick film region and a thin film region. As described above, the second conductivity type impurity is injected and diffused from above the oxide film to form an emitter layer in which high resistance regions and low resistance regions are alternately arranged, and the oxide film is removed. A method of manufacturing a semiconductor device, comprising: